drivers/dma/dma-jz4780.c

   1 /*
   2  * Ingenic JZ4780 DMA controller
   3  *
   4  * Copyright (c) 2015 Imagination Technologies
   5  * Author: Alex Smith <alex@alex-smith.me.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/dmapool.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_device.h>
  20 #include <linux/of_dma.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23
  24 #include "dmaengine.h"
  25 #include "virt-dma.h"
  26
  27 /* Global registers. */
  28 #define JZ_DMA_REG_DMAC         0x00
  29 #define JZ_DMA_REG_DIRQP        0x04
  30 #define JZ_DMA_REG_DDR          0x08
  31 #define JZ_DMA_REG_DDRS         0x0c
  32 #define JZ_DMA_REG_DCKE         0x10
  33 #define JZ_DMA_REG_DCKES        0x14
  34 #define JZ_DMA_REG_DCKEC        0x18
  35 #define JZ_DMA_REG_DMACP        0x1c
  36 #define JZ_DMA_REG_DSIRQP       0x20
  37 #define JZ_DMA_REG_DSIRQM       0x24
  38 #define JZ_DMA_REG_DCIRQP       0x28
  39 #define JZ_DMA_REG_DCIRQM       0x2c
  40
  41 /* Per-channel registers. */
  42 #define JZ_DMA_REG_CHAN(n)      (n * 0x20)
  43 #define JZ_DMA_REG_DSA          0x00
  44 #define JZ_DMA_REG_DTA          0x04
  45 #define JZ_DMA_REG_DTC          0x08
  46 #define JZ_DMA_REG_DRT          0x0c
  47 #define JZ_DMA_REG_DCS          0x10
  48 #define JZ_DMA_REG_DCM          0x14
  49 #define JZ_DMA_REG_DDA          0x18
  50 #define JZ_DMA_REG_DSD          0x1c
  51
  52 #define JZ_DMA_DMAC_DMAE        BIT(0)
  53 #define JZ_DMA_DMAC_AR          BIT(2)
  54 #define JZ_DMA_DMAC_HLT         BIT(3)
  55 #define JZ_DMA_DMAC_FMSC        BIT(31)
  56
  57 #define JZ_DMA_DRT_AUTO         0x8
  58
  59 #define JZ_DMA_DCS_CTE          BIT(0)
  60 #define JZ_DMA_DCS_HLT          BIT(2)
  61 #define JZ_DMA_DCS_TT           BIT(3)
  62 #define JZ_DMA_DCS_AR           BIT(4)
  63 #define JZ_DMA_DCS_DES8         BIT(30)
  64
  65 #define JZ_DMA_DCM_LINK         BIT(0)
  66 #define JZ_DMA_DCM_TIE          BIT(1)
  67 #define JZ_DMA_DCM_STDE         BIT(2)
  68 #define JZ_DMA_DCM_TSZ_SHIFT    8
  69 #define JZ_DMA_DCM_TSZ_MASK     (0x7 << JZ_DMA_DCM_TSZ_SHIFT)
  70 #define JZ_DMA_DCM_DP_SHIFT     12
  71 #define JZ_DMA_DCM_SP_SHIFT     14
  72 #define JZ_DMA_DCM_DAI          BIT(22)
  73 #define JZ_DMA_DCM_SAI          BIT(23)
  74
  75 #define JZ_DMA_SIZE_4_BYTE      0x0
  76 #define JZ_DMA_SIZE_1_BYTE      0x1
  77 #define JZ_DMA_SIZE_2_BYTE      0x2
  78 #define JZ_DMA_SIZE_16_BYTE     0x3
  79 #define JZ_DMA_SIZE_32_BYTE     0x4
  80 #define JZ_DMA_SIZE_64_BYTE     0x5
  81 #define JZ_DMA_SIZE_128_BYTE    0x6
  82
  83 #define JZ_DMA_WIDTH_32_BIT     0x0
  84 #define JZ_DMA_WIDTH_8_BIT      0x1
  85 #define JZ_DMA_WIDTH_16_BIT     0x2
  86
  87 #define JZ_DMA_BUSWIDTHS        (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)  | \
  88                                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  89                                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
  90
  91 #define JZ4780_DMA_CTRL_OFFSET  0x1000
  92
  93 /* macros for use with jz4780_dma_soc_data.flags */
  94 #define JZ_SOC_DATA_ALLOW_LEGACY_DT     BIT(0)
  95 #define JZ_SOC_DATA_PROGRAMMABLE_DMA    BIT(1)
  96 #define JZ_SOC_DATA_PER_CHAN_PM         BIT(2)
  97 #define JZ_SOC_DATA_NO_DCKES_DCKEC      BIT(3)
  98
  99 /**
 100  * struct jz4780_dma_hwdesc - descriptor structure read by the DMA controller.
 101  * @dcm: value for the DCM (channel command) register
 102  * @dsa: source address
 103  * @dta: target address
 104  * @dtc: transfer count (number of blocks of the transfer size specified in DCM
 105  * to transfer) in the low 24 bits, offset of the next descriptor from the
 106  * descriptor base address in the upper 8 bits.
 107  */
 108 struct jz4780_dma_hwdesc {
 109         uint32_t dcm;
 110         uint32_t dsa;
 111         uint32_t dta;
 112         uint32_t dtc;
 113 };
 114
 115 /* Size of allocations for hardware descriptor blocks. */
 116 #define JZ_DMA_DESC_BLOCK_SIZE  PAGE_SIZE
 117 #define JZ_DMA_MAX_DESC         \
 118         (JZ_DMA_DESC_BLOCK_SIZE / sizeof(struct jz4780_dma_hwdesc))
 119
 120 struct jz4780_dma_desc {
 121         struct virt_dma_desc vdesc;
 122
 123         struct jz4780_dma_hwdesc *desc;
 124         dma_addr_t desc_phys;
 125         unsigned int count;
 126         enum dma_transaction_type type;
 127         uint32_t status;
 128 };
 129
 130 struct jz4780_dma_chan {
 131         struct virt_dma_chan vchan;
 132         unsigned int id;
 133         struct dma_pool *desc_pool;
 134
 135         uint32_t transfer_type;
 136         uint32_t transfer_shift;
 137         struct dma_slave_config config;
 138
 139         struct jz4780_dma_desc *desc;
 140         unsigned int curr_hwdesc;
 141 };
 142
 143 struct jz4780_dma_soc_data {
 144         unsigned int nb_channels;
 145         unsigned int transfer_ord_max;
 146         unsigned long flags;
 147 };
 148
 149 struct jz4780_dma_dev {
 150         struct dma_device dma_device;
 151         void __iomem *chn_base;
 152         void __iomem *ctrl_base;
 153         struct clk *clk;
 154         unsigned int irq;
 155         const struct jz4780_dma_soc_data *soc_data;
 156
 157         uint32_t chan_reserved;
 158         struct jz4780_dma_chan chan[];
 159 };
 160
 161 struct jz4780_dma_filter_data {
 162         struct device_node *of_node;
 163         uint32_t transfer_type;
 164         int channel;
 165 };
 166
 167 static inline struct jz4780_dma_chan *to_jz4780_dma_chan(struct dma_chan *chan)
 168 {
 169         return container_of(chan, struct jz4780_dma_chan, vchan.chan);
 170 }
 171
 172 static inline struct jz4780_dma_desc *to_jz4780_dma_desc(
 173         struct virt_dma_desc *vdesc)
 174 {
 175         return container_of(vdesc, struct jz4780_dma_desc, vdesc);
 176 }
 177
 178 static inline struct jz4780_dma_dev *jz4780_dma_chan_parent(
 179         struct jz4780_dma_chan *jzchan)
 180 {
 181         return container_of(jzchan->vchan.chan.device, struct jz4780_dma_dev,
 182                             dma_device);
 183 }
 184
 185 static inline uint32_t jz4780_dma_chn_readl(struct jz4780_dma_dev *jzdma,
 186         unsigned int chn, unsigned int reg)
 187 {
 188         return readl(jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn));
 189 }
 190
 191 static inline void jz4780_dma_chn_writel(struct jz4780_dma_dev *jzdma,
 192         unsigned int chn, unsigned int reg, uint32_t val)
 193 {
 194         writel(val, jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn));
 195 }
 196
 197 static inline uint32_t jz4780_dma_ctrl_readl(struct jz4780_dma_dev *jzdma,
 198         unsigned int reg)
 199 {
 200         return readl(jzdma->ctrl_base + reg);
 201 }
 202
 203 static inline void jz4780_dma_ctrl_writel(struct jz4780_dma_dev *jzdma,
 204         unsigned int reg, uint32_t val)
 205 {
 206         writel(val, jzdma->ctrl_base + reg);
 207 }
 208
 209 static inline void jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma,
 210         unsigned int chn)
 211 {
 212         if (jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) {
 213                 unsigned int reg;
 214
 215                 if (jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC)
 216                         reg = JZ_DMA_REG_DCKE;
 217                 else
 218                         reg = JZ_DMA_REG_DCKES;
 219
 220                 jz4780_dma_ctrl_writel(jzdma, reg, BIT(chn));
 221         }
 222 }
 223
 224 static inline void jz4780_dma_chan_disable(struct jz4780_dma_dev *jzdma,
 225         unsigned int chn)
 226 {
 227         if ((jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) &&
 228                         !(jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC))
 229                 jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKEC, BIT(chn));
 230 }
 231
 232 static struct jz4780_dma_desc *jz4780_dma_desc_alloc(
 233         struct jz4780_dma_chan *jzchan, unsigned int count,
 234         enum dma_transaction_type type)
 235 {
 236         struct jz4780_dma_desc *desc;
 237
 238         if (count > JZ_DMA_MAX_DESC)
 239                 return NULL;
 240
 241         desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
 242         if (!desc)
 243                 return NULL;
 244
 245         desc->desc = dma_pool_alloc(jzchan->desc_pool, GFP_NOWAIT,
 246                                     &desc->desc_phys);
 247         if (!desc->desc) {
 248                 kfree(desc);
 249                 return NULL;
 250         }
 251
 252         desc->count = count;
 253         desc->type = type;
 254         return desc;
 255 }
 256
 257 static void jz4780_dma_desc_free(struct virt_dma_desc *vdesc)
 258 {
 259         struct jz4780_dma_desc *desc = to_jz4780_dma_desc(vdesc);
 260         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(vdesc->tx.chan);
 261
 262         dma_pool_free(jzchan->desc_pool, desc->desc, desc->desc_phys);
 263         kfree(desc);
 264 }
 265
 266 static uint32_t jz4780_dma_transfer_size(struct jz4780_dma_chan *jzchan,
 267         unsigned long val, uint32_t *shift)
 268 {
 269         struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
 270         int ord = ffs(val) - 1;
 271
 272         /*
 273          * 8 byte transfer sizes unsupported so fall back on 4. If it's larger
 274          * than the maximum, just limit it. It is perfectly safe to fall back
 275          * in this way since we won't exceed the maximum burst size supported
 276          * by the device, the only effect is reduced efficiency. This is better
 277          * than refusing to perform the request at all.
 278          */
 279         if (ord == 3)
 280                 ord = 2;
 281         else if (ord > jzdma->soc_data->transfer_ord_max)
 282                 ord = jzdma->soc_data->transfer_ord_max;
 283
 284         *shift = ord;
 285
 286         switch (ord) {
 287         case 0:
 288                 return JZ_DMA_SIZE_1_BYTE;
 289         case 1:
 290                 return JZ_DMA_SIZE_2_BYTE;
 291         case 2:
 292                 return JZ_DMA_SIZE_4_BYTE;
 293         case 4:
 294                 return JZ_DMA_SIZE_16_BYTE;
 295         case 5:
 296                 return JZ_DMA_SIZE_32_BYTE;
 297         case 6:
 298                 return JZ_DMA_SIZE_64_BYTE;
 299         default:
 300                 return JZ_DMA_SIZE_128_BYTE;
 301         }
 302 }
 303
 304 static int jz4780_dma_setup_hwdesc(struct jz4780_dma_chan *jzchan,
 305         struct jz4780_dma_hwdesc *desc, dma_addr_t addr, size_t len,
 306         enum dma_transfer_direction direction)
 307 {
 308         struct dma_slave_config *config = &jzchan->config;
 309         uint32_t width, maxburst, tsz;
 310
 311         if (direction == DMA_MEM_TO_DEV) {
 312                 desc->dcm = JZ_DMA_DCM_SAI;
 313                 desc->dsa = addr;
 314                 desc->dta = config->dst_addr;
 315
 316                 width = config->dst_addr_width;
 317                 maxburst = config->dst_maxburst;
 318         } else {
 319                 desc->dcm = JZ_DMA_DCM_DAI;
 320                 desc->dsa = config->src_addr;
 321                 desc->dta = addr;
 322
 323                 width = config->src_addr_width;
 324                 maxburst = config->src_maxburst;
 325         }
 326
 327         /*
 328          * This calculates the maximum transfer size that can be used with the
 329          * given address, length, width and maximum burst size. The address
 330          * must be aligned to the transfer size, the total length must be
 331          * divisible by the transfer size, and we must not use more than the
 332          * maximum burst specified by the user.
 333          */
 334         tsz = jz4780_dma_transfer_size(jzchan, addr | len | (width * maxburst),
 335                                        &jzchan->transfer_shift);
 336
 337         switch (width) {
 338         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 339         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 340                 break;
 341         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 342                 width = JZ_DMA_WIDTH_32_BIT;
 343                 break;
 344         default:
 345                 return -EINVAL;
 346         }
 347
 348         desc->dcm |= tsz << JZ_DMA_DCM_TSZ_SHIFT;
 349         desc->dcm |= width << JZ_DMA_DCM_SP_SHIFT;
 350         desc->dcm |= width << JZ_DMA_DCM_DP_SHIFT;
 351
 352         desc->dtc = len >> jzchan->transfer_shift;
 353         return 0;
 354 }
 355
 356 static struct dma_async_tx_descriptor *jz4780_dma_prep_slave_sg(
 357         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
 358         enum dma_transfer_direction direction, unsigned long flags,
 359         void *context)
 360 {
 361         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 362         struct jz4780_dma_desc *desc;
 363         unsigned int i;
 364         int err;
 365
 366         desc = jz4780_dma_desc_alloc(jzchan, sg_len, DMA_SLAVE);
 367         if (!desc)
 368                 return NULL;
 369
 370         for (i = 0; i < sg_len; i++) {
 371                 err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i],
 372                                               sg_dma_address(&sgl[i]),
 373                                               sg_dma_len(&sgl[i]),
 374                                               direction);
 375                 if (err < 0) {
 376                         jz4780_dma_desc_free(&jzchan->desc->vdesc);
 377                         return NULL;
 378                 }
 379
 380                 desc->desc[i].dcm |= JZ_DMA_DCM_TIE;
 381
 382                 if (i != (sg_len - 1)) {
 383                         /* Automatically proceeed to the next descriptor. */
 384                         desc->desc[i].dcm |= JZ_DMA_DCM_LINK;
 385
 386                         /*
 387                          * The upper 8 bits of the DTC field in the descriptor
 388                          * must be set to (offset from descriptor base of next
 389                          * descriptor >> 4).
 390                          */
 391                         desc->desc[i].dtc |=
 392                                 (((i + 1) * sizeof(*desc->desc)) >> 4) << 24;
 393                 }
 394         }
 395
 396         return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);
 397 }
 398
 399 static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_cyclic(
 400         struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 401         size_t period_len, enum dma_transfer_direction direction,
 402         unsigned long flags)
 403 {
 404         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 405         struct jz4780_dma_desc *desc;
 406         unsigned int periods, i;
 407         int err;
 408
 409         if (buf_len % period_len)
 410                 return NULL;
 411
 412         periods = buf_len / period_len;
 413
 414         desc = jz4780_dma_desc_alloc(jzchan, periods, DMA_CYCLIC);
 415         if (!desc)
 416                 return NULL;
 417
 418         for (i = 0; i < periods; i++) {
 419                 err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i], buf_addr,
 420                                               period_len, direction);
 421                 if (err < 0) {
 422                         jz4780_dma_desc_free(&jzchan->desc->vdesc);
 423                         return NULL;
 424                 }
 425
 426                 buf_addr += period_len;
 427
 428                 /*
 429                  * Set the link bit to indicate that the controller should
 430                  * automatically proceed to the next descriptor. In
 431                  * jz4780_dma_begin(), this will be cleared if we need to issue
 432                  * an interrupt after each period.
 433                  */
 434                 desc->desc[i].dcm |= JZ_DMA_DCM_TIE | JZ_DMA_DCM_LINK;
 435
 436                 /*
 437                  * The upper 8 bits of the DTC field in the descriptor must be
 438                  * set to (offset from descriptor base of next descriptor >> 4).
 439                  * If this is the last descriptor, link it back to the first,
 440                  * i.e. leave offset set to 0, otherwise point to the next one.
 441                  */
 442                 if (i != (periods - 1)) {
 443                         desc->desc[i].dtc |=
 444                                 (((i + 1) * sizeof(*desc->desc)) >> 4) << 24;
 445                 }
 446         }
 447
 448         return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);
 449 }
 450
 451 static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_memcpy(
 452         struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 453         size_t len, unsigned long flags)
 454 {
 455         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 456         struct jz4780_dma_desc *desc;
 457         uint32_t tsz;
 458
 459         desc = jz4780_dma_desc_alloc(jzchan, 1, DMA_MEMCPY);
 460         if (!desc)
 461                 return NULL;
 462
 463         tsz = jz4780_dma_transfer_size(jzchan, dest | src | len,
 464                                        &jzchan->transfer_shift);
 465
 466         jzchan->transfer_type = JZ_DMA_DRT_AUTO;
 467
 468         desc->desc[0].dsa = src;
 469         desc->desc[0].dta = dest;
 470         desc->desc[0].dcm = JZ_DMA_DCM_TIE | JZ_DMA_DCM_SAI | JZ_DMA_DCM_DAI |
 471                             tsz << JZ_DMA_DCM_TSZ_SHIFT |
 472                             JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_SP_SHIFT |
 473                             JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_DP_SHIFT;
 474         desc->desc[0].dtc = len >> jzchan->transfer_shift;
 475
 476         return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);
 477 }
 478
 479 static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan)
 480 {
 481         struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
 482         struct virt_dma_desc *vdesc;
 483         unsigned int i;
 484         dma_addr_t desc_phys;
 485
 486         if (!jzchan->desc) {
 487                 vdesc = vchan_next_desc(&jzchan->vchan);
 488                 if (!vdesc)
 489                         return;
 490
 491                 list_del(&vdesc->node);
 492
 493                 jzchan->desc = to_jz4780_dma_desc(vdesc);
 494                 jzchan->curr_hwdesc = 0;
 495
 496                 if (jzchan->desc->type == DMA_CYCLIC && vdesc->tx.callback) {
 497                         /*
 498                          * The DMA controller doesn't support triggering an
 499                          * interrupt after processing each descriptor, only
 500                          * after processing an entire terminated list of
 501                          * descriptors. For a cyclic DMA setup the list of
 502                          * descriptors is not terminated so we can never get an
 503                          * interrupt.
 504                          *
 505                          * If the user requested a callback for a cyclic DMA
 506                          * setup then we workaround this hardware limitation
 507                          * here by degrading to a set of unlinked descriptors
 508                          * which we will submit in sequence in response to the
 509                          * completion of processing the previous descriptor.
 510                          */
 511                         for (i = 0; i < jzchan->desc->count; i++)
 512                                 jzchan->desc->desc[i].dcm &= ~JZ_DMA_DCM_LINK;
 513                 }
 514         } else {
 515                 /*
 516                  * There is an existing transfer, therefore this must be one
 517                  * for which we unlinked the descriptors above. Advance to the
 518                  * next one in the list.
 519                  */
 520                 jzchan->curr_hwdesc =
 521                         (jzchan->curr_hwdesc + 1) % jzchan->desc->count;
 522         }
 523
 524         /* Enable the channel's clock. */
 525         jz4780_dma_chan_enable(jzdma, jzchan->id);
 526
 527         /* Use 4-word descriptors. */
 528         jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
 529
 530         /* Set transfer type. */
 531         jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DRT,
 532                               jzchan->transfer_type);
 533
 534         /* Write descriptor address and initiate descriptor fetch. */
 535         desc_phys = jzchan->desc->desc_phys +
 536                     (jzchan->curr_hwdesc * sizeof(*jzchan->desc->desc));
 537         jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DDA, desc_phys);
 538         jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DDRS, BIT(jzchan->id));
 539
 540         /* Enable the channel. */
 541         jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS,
 542                               JZ_DMA_DCS_CTE);
 543 }
 544
 545 static void jz4780_dma_issue_pending(struct dma_chan *chan)
 546 {
 547         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 548         unsigned long flags;
 549
 550         spin_lock_irqsave(&jzchan->vchan.lock, flags);
 551
 552         if (vchan_issue_pending(&jzchan->vchan) && !jzchan->desc)
 553                 jz4780_dma_begin(jzchan);
 554
 555         spin_unlock_irqrestore(&jzchan->vchan.lock, flags);
 556 }
 557
 558 static int jz4780_dma_terminate_all(struct dma_chan *chan)
 559 {
 560         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 561         struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
 562         unsigned long flags;
 563         LIST_HEAD(head);
 564
 565         spin_lock_irqsave(&jzchan->vchan.lock, flags);
 566
 567         /* Clear the DMA status and stop the transfer. */
 568         jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
 569         if (jzchan->desc) {
 570                 vchan_terminate_vdesc(&jzchan->desc->vdesc);
 571                 jzchan->desc = NULL;
 572         }
 573
 574         jz4780_dma_chan_disable(jzdma, jzchan->id);
 575
 576         vchan_get_all_descriptors(&jzchan->vchan, &head);
 577
 578         spin_unlock_irqrestore(&jzchan->vchan.lock, flags);
 579
 580         vchan_dma_desc_free_list(&jzchan->vchan, &head);
 581         return 0;
 582 }
 583
 584 static void jz4780_dma_synchronize(struct dma_chan *chan)
 585 {
 586         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 587         struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
 588
 589         vchan_synchronize(&jzchan->vchan);
 590         jz4780_dma_chan_disable(jzdma, jzchan->id);
 591 }
 592
 593 static int jz4780_dma_config(struct dma_chan *chan,
 594         struct dma_slave_config *config)
 595 {
 596         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 597
 598         if ((config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
 599            || (config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES))
 600                 return -EINVAL;
 601
 602         /* Copy the reset of the slave configuration, it is used later. */
 603         memcpy(&jzchan->config, config, sizeof(jzchan->config));
 604
 605         return 0;
 606 }
 607
 608 static size_t jz4780_dma_desc_residue(struct jz4780_dma_chan *jzchan,
 609         struct jz4780_dma_desc *desc, unsigned int next_sg)
 610 {
 611         struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
 612         unsigned int residue, count;
 613         unsigned int i;
 614
 615         residue = 0;
 616
 617         for (i = next_sg; i < desc->count; i++)
 618                 residue += desc->desc[i].dtc << jzchan->transfer_shift;
 619
 620         if (next_sg != 0) {
 621                 count = jz4780_dma_chn_readl(jzdma, jzchan->id,
 622                                          JZ_DMA_REG_DTC);
 623                 residue += count << jzchan->transfer_shift;
 624         }
 625
 626         return residue;
 627 }
 628
 629 static enum dma_status jz4780_dma_tx_status(struct dma_chan *chan,
 630         dma_cookie_t cookie, struct dma_tx_state *txstate)
 631 {
 632         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 633         struct virt_dma_desc *vdesc;
 634         enum dma_status status;
 635         unsigned long flags;
 636
 637         status = dma_cookie_status(chan, cookie, txstate);
 638         if ((status == DMA_COMPLETE) || (txstate == NULL))
 639                 return status;
 640
 641         spin_lock_irqsave(&jzchan->vchan.lock, flags);
 642
 643         vdesc = vchan_find_desc(&jzchan->vchan, cookie);
 644         if (vdesc) {
 645                 /* On the issued list, so hasn't been processed yet */
 646                 txstate->residue = jz4780_dma_desc_residue(jzchan,
 647                                         to_jz4780_dma_desc(vdesc), 0);
 648         } else if (cookie == jzchan->desc->vdesc.tx.cookie) {
 649                 txstate->residue = jz4780_dma_desc_residue(jzchan, jzchan->desc,
 650                           (jzchan->curr_hwdesc + 1) % jzchan->desc->count);
 651         } else
 652                 txstate->residue = 0;
 653
 654         if (vdesc && jzchan->desc && vdesc == &jzchan->desc->vdesc
 655             && jzchan->desc->status & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT))
 656                 status = DMA_ERROR;
 657
 658         spin_unlock_irqrestore(&jzchan->vchan.lock, flags);
 659         return status;
 660 }
 661
 662 static void jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma,
 663         struct jz4780_dma_chan *jzchan)
 664 {
 665         uint32_t dcs;
 666
 667         spin_lock(&jzchan->vchan.lock);
 668
 669         dcs = jz4780_dma_chn_readl(jzdma, jzchan->id, JZ_DMA_REG_DCS);
 670         jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
 671
 672         if (dcs & JZ_DMA_DCS_AR) {
 673                 dev_warn(&jzchan->vchan.chan.dev->device,
 674                          "address error (DCS=0x%x)\n", dcs);
 675         }
 676
 677         if (dcs & JZ_DMA_DCS_HLT) {
 678                 dev_warn(&jzchan->vchan.chan.dev->device,
 679                          "channel halt (DCS=0x%x)\n", dcs);
 680         }
 681
 682         if (jzchan->desc) {
 683                 jzchan->desc->status = dcs;
 684
 685                 if ((dcs & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT)) == 0) {
 686                         if (jzchan->desc->type == DMA_CYCLIC) {
 687                                 vchan_cyclic_callback(&jzchan->desc->vdesc);
 688                         } else {
 689                                 vchan_cookie_complete(&jzchan->desc->vdesc);
 690                                 jzchan->desc = NULL;
 691                         }
 692
 693                         jz4780_dma_begin(jzchan);
 694                 }
 695         } else {
 696                 dev_err(&jzchan->vchan.chan.dev->device,
 697                         "channel IRQ with no active transfer\n");
 698         }
 699
 700         spin_unlock(&jzchan->vchan.lock);
 701 }
 702
 703 static irqreturn_t jz4780_dma_irq_handler(int irq, void *data)
 704 {
 705         struct jz4780_dma_dev *jzdma = data;
 706         uint32_t pending, dmac;
 707         int i;
 708
 709         pending = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DIRQP);
 710
 711         for (i = 0; i < jzdma->soc_data->nb_channels; i++) {
 712                 if (!(pending & (1<<i)))
 713                         continue;
 714
 715                 jz4780_dma_chan_irq(jzdma, &jzdma->chan[i]);
 716         }
 717
 718         /* Clear halt and address error status of all channels. */
 719         dmac = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DMAC);
 720         dmac &= ~(JZ_DMA_DMAC_HLT | JZ_DMA_DMAC_AR);
 721         jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMAC, dmac);
 722
 723         /* Clear interrupt pending status. */
 724         jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DIRQP, 0);
 725
 726         return IRQ_HANDLED;
 727 }
 728
 729 static int jz4780_dma_alloc_chan_resources(struct dma_chan *chan)
 730 {
 731         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 732
 733         jzchan->desc_pool = dma_pool_create(dev_name(&chan->dev->device),
 734                                             chan->device->dev,
 735                                             JZ_DMA_DESC_BLOCK_SIZE,
 736                                             PAGE_SIZE, 0);
 737         if (!jzchan->desc_pool) {
 738                 dev_err(&chan->dev->device,
 739                         "failed to allocate descriptor pool\n");
 740                 return -ENOMEM;
 741         }
 742
 743         return 0;
 744 }
 745
 746 static void jz4780_dma_free_chan_resources(struct dma_chan *chan)
 747 {
 748         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 749
 750         vchan_free_chan_resources(&jzchan->vchan);
 751         dma_pool_destroy(jzchan->desc_pool);
 752         jzchan->desc_pool = NULL;
 753 }
 754
 755 static bool jz4780_dma_filter_fn(struct dma_chan *chan, void *param)
 756 {
 757         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 758         struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
 759         struct jz4780_dma_filter_data *data = param;
 760
 761         if (jzdma->dma_device.dev->of_node != data->of_node)
 762                 return false;
 763
 764         if (data->channel > -1) {
 765                 if (data->channel != jzchan->id)
 766                         return false;
 767         } else if (jzdma->chan_reserved & BIT(jzchan->id)) {
 768                 return false;
 769         }
 770
 771         jzchan->transfer_type = data->transfer_type;
 772
 773         return true;
 774 }
 775
 776 static struct dma_chan *jz4780_of_dma_xlate(struct of_phandle_args *dma_spec,
 777         struct of_dma *ofdma)
 778 {
 779         struct jz4780_dma_dev *jzdma = ofdma->of_dma_data;
 780         dma_cap_mask_t mask = jzdma->dma_device.cap_mask;
 781         struct jz4780_dma_filter_data data;
 782
 783         if (dma_spec->args_count != 2)
 784                 return NULL;
 785
 786         data.of_node = ofdma->of_node;
 787         data.transfer_type = dma_spec->args[0];
 788         data.channel = dma_spec->args[1];
 789
 790         if (data.channel > -1) {
 791                 if (data.channel >= jzdma->soc_data->nb_channels) {
 792                         dev_err(jzdma->dma_device.dev,
 793                                 "device requested non-existent channel %u\n",
 794                                 data.channel);
 795                         return NULL;
 796                 }
 797
 798                 /* Can only select a channel marked as reserved. */
 799                 if (!(jzdma->chan_reserved & BIT(data.channel))) {
 800                         dev_err(jzdma->dma_device.dev,
 801                                 "device requested unreserved channel %u\n",
 802                                 data.channel);
 803                         return NULL;
 804                 }
 805
 806                 jzdma->chan[data.channel].transfer_type = data.transfer_type;
 807
 808                 return dma_get_slave_channel(
 809                         &jzdma->chan[data.channel].vchan.chan);
 810         } else {
 811                 return dma_request_channel(mask, jz4780_dma_filter_fn, &data);
 812         }
 813 }
 814
 815 static int jz4780_dma_probe(struct platform_device *pdev)
 816 {
 817         struct device *dev = &pdev->dev;
 818         const struct jz4780_dma_soc_data *soc_data;
 819         struct jz4780_dma_dev *jzdma;
 820         struct jz4780_dma_chan *jzchan;
 821         struct dma_device *dd;
 822         struct resource *res;
 823         int i, ret;
 824
 825         if (!dev->of_node) {
 826                 dev_err(dev, "This driver must be probed from devicetree\n");
 827                 return -EINVAL;
 828         }
 829
 830         soc_data = device_get_match_data(dev);
 831         if (!soc_data)
 832                 return -EINVAL;
 833
 834         jzdma = devm_kzalloc(dev, sizeof(*jzdma)
 835                                 + sizeof(*jzdma->chan) * soc_data->nb_channels,
 836                                 GFP_KERNEL);
 837         if (!jzdma)
 838                 return -ENOMEM;
 839
 840         jzdma->soc_data = soc_data;
 841         platform_set_drvdata(pdev, jzdma);
 842
 843         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 844         if (!res) {
 845                 dev_err(dev, "failed to get I/O memory\n");
 846                 return -EINVAL;
 847         }
 848
 849         jzdma->chn_base = devm_ioremap_resource(dev, res);
 850         if (IS_ERR(jzdma->chn_base))
 851                 return PTR_ERR(jzdma->chn_base);
 852
 853         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 854         if (res) {
 855                 jzdma->ctrl_base = devm_ioremap_resource(dev, res);
 856                 if (IS_ERR(jzdma->ctrl_base))
 857                         return PTR_ERR(jzdma->ctrl_base);
 858         } else if (soc_data->flags & JZ_SOC_DATA_ALLOW_LEGACY_DT) {
 859                 /*
 860                  * On JZ4780, if the second memory resource was not supplied,
 861                  * assume we're using an old devicetree, and calculate the
 862                  * offset to the control registers.
 863                  */
 864                 jzdma->ctrl_base = jzdma->chn_base + JZ4780_DMA_CTRL_OFFSET;
 865         } else {
 866                 dev_err(dev, "failed to get I/O memory\n");
 867                 return -EINVAL;
 868         }
 869
 870         ret = platform_get_irq(pdev, 0);
 871         if (ret < 0) {
 872                 dev_err(dev, "failed to get IRQ: %d\n", ret);
 873                 return ret;
 874         }
 875
 876         jzdma->irq = ret;
 877
 878         ret = request_irq(jzdma->irq, jz4780_dma_irq_handler, 0, dev_name(dev),
 879                           jzdma);
 880         if (ret) {
 881                 dev_err(dev, "failed to request IRQ %u!\n", jzdma->irq);
 882                 return ret;
 883         }
 884
 885         jzdma->clk = devm_clk_get(dev, NULL);
 886         if (IS_ERR(jzdma->clk)) {
 887                 dev_err(dev, "failed to get clock\n");
 888                 ret = PTR_ERR(jzdma->clk);
 889                 goto err_free_irq;
 890         }
 891
 892         clk_prepare_enable(jzdma->clk);
 893
 894         /* Property is optional, if it doesn't exist the value will remain 0. */
 895         of_property_read_u32_index(dev->of_node, "ingenic,reserved-channels",
 896                                    0, &jzdma->chan_reserved);
 897
 898         dd = &jzdma->dma_device;
 899
 900         dma_cap_set(DMA_MEMCPY, dd->cap_mask);
 901         dma_cap_set(DMA_SLAVE, dd->cap_mask);
 902         dma_cap_set(DMA_CYCLIC, dd->cap_mask);
 903
 904         dd->dev = dev;
 905         dd->copy_align = DMAENGINE_ALIGN_4_BYTES;
 906         dd->device_alloc_chan_resources = jz4780_dma_alloc_chan_resources;
 907         dd->device_free_chan_resources = jz4780_dma_free_chan_resources;
 908         dd->device_prep_slave_sg = jz4780_dma_prep_slave_sg;
 909         dd->device_prep_dma_cyclic = jz4780_dma_prep_dma_cyclic;
 910         dd->device_prep_dma_memcpy = jz4780_dma_prep_dma_memcpy;
 911         dd->device_config = jz4780_dma_config;
 912         dd->device_terminate_all = jz4780_dma_terminate_all;
 913         dd->device_synchronize = jz4780_dma_synchronize;
 914         dd->device_tx_status = jz4780_dma_tx_status;
 915         dd->device_issue_pending = jz4780_dma_issue_pending;
 916         dd->src_addr_widths = JZ_DMA_BUSWIDTHS;
 917         dd->dst_addr_widths = JZ_DMA_BUSWIDTHS;
 918         dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
 919         dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
 920
 921         /*
 922          * Enable DMA controller, mark all channels as not programmable.
 923          * Also set the FMSC bit - it increases MSC performance, so it makes
 924          * little sense not to enable it.
 925          */
 926         jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMAC,
 927                           JZ_DMA_DMAC_DMAE | JZ_DMA_DMAC_FMSC);
 928
 929         if (soc_data->flags & JZ_SOC_DATA_PROGRAMMABLE_DMA)
 930                 jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMACP, 0);
 931
 932         INIT_LIST_HEAD(&dd->channels);
 933
 934         for (i = 0; i < soc_data->nb_channels; i++) {
 935                 jzchan = &jzdma->chan[i];
 936                 jzchan->id = i;
 937
 938                 vchan_init(&jzchan->vchan, dd);
 939                 jzchan->vchan.desc_free = jz4780_dma_desc_free;
 940         }
 941
 942         ret = dma_async_device_register(dd);
 943         if (ret) {
 944                 dev_err(dev, "failed to register device\n");
 945                 goto err_disable_clk;
 946         }
 947
 948         /* Register with OF DMA helpers. */
 949         ret = of_dma_controller_register(dev->of_node, jz4780_of_dma_xlate,
 950                                          jzdma);
 951         if (ret) {
 952                 dev_err(dev, "failed to register OF DMA controller\n");
 953                 goto err_unregister_dev;
 954         }
 955
 956         dev_info(dev, "JZ4780 DMA controller initialised\n");
 957         return 0;
 958
 959 err_unregister_dev:
 960         dma_async_device_unregister(dd);
 961
 962 err_disable_clk:
 963         clk_disable_unprepare(jzdma->clk);
 964
 965 err_free_irq:
 966         free_irq(jzdma->irq, jzdma);
 967         return ret;
 968 }
 969
 970 static int jz4780_dma_remove(struct platform_device *pdev)
 971 {
 972         struct jz4780_dma_dev *jzdma = platform_get_drvdata(pdev);
 973         int i;
 974
 975         of_dma_controller_free(pdev->dev.of_node);
 976
 977         free_irq(jzdma->irq, jzdma);
 978
 979         for (i = 0; i < jzdma->soc_data->nb_channels; i++)
 980                 tasklet_kill(&jzdma->chan[i].vchan.task);
 981
 982         dma_async_device_unregister(&jzdma->dma_device);
 983         return 0;
 984 }
 985
 986 static const struct jz4780_dma_soc_data jz4740_dma_soc_data = {
 987         .nb_channels = 6,
 988         .transfer_ord_max = 5,
 989 };
 990
 991 static const struct jz4780_dma_soc_data jz4725b_dma_soc_data = {
 992         .nb_channels = 6,
 993         .transfer_ord_max = 5,
 994         .flags = JZ_SOC_DATA_PER_CHAN_PM | JZ_SOC_DATA_NO_DCKES_DCKEC,
 995 };
 996
 997 static const struct jz4780_dma_soc_data jz4770_dma_soc_data = {
 998         .nb_channels = 6,
 999         .transfer_ord_max = 6,
1000         .flags = JZ_SOC_DATA_PER_CHAN_PM,
1001 };
1002
1003 static const struct jz4780_dma_soc_data jz4780_dma_soc_data = {
1004         .nb_channels = 32,
1005         .transfer_ord_max = 7,
1006         .flags = JZ_SOC_DATA_ALLOW_LEGACY_DT | JZ_SOC_DATA_PROGRAMMABLE_DMA,
1007 };
1008
1009 static const struct of_device_id jz4780_dma_dt_match[] = {
1010         { .compatible = "ingenic,jz4740-dma", .data = &jz4740_dma_soc_data },
1011         { .compatible = "ingenic,jz4725b-dma", .data = &jz4725b_dma_soc_data },
1012         { .compatible = "ingenic,jz4770-dma", .data = &jz4770_dma_soc_data },
1013         { .compatible = "ingenic,jz4780-dma", .data = &jz4780_dma_soc_data },
1014         {},
1015 };
1016 MODULE_DEVICE_TABLE(of, jz4780_dma_dt_match);
1017
1018 static struct platform_driver jz4780_dma_driver = {
1019         .probe          = jz4780_dma_probe,
1020         .remove         = jz4780_dma_remove,
1021         .driver = {
1022                 .name   = "jz4780-dma",
1023                 .of_match_table = of_match_ptr(jz4780_dma_dt_match),
1024         },
1025 };
1026
1027 static int __init jz4780_dma_init(void)
1028 {
1029         return platform_driver_register(&jz4780_dma_driver);
1030 }
1031 subsys_initcall(jz4780_dma_init);
1032
1033 static void __exit jz4780_dma_exit(void)
1034 {
1035         platform_driver_unregister(&jz4780_dma_driver);
1036 }
1037 module_exit(jz4780_dma_exit);
1038
1039 MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
1040 MODULE_DESCRIPTION("Ingenic JZ4780 DMA controller driver");
1041 MODULE_LICENSE("GPL");