2 * driver/dma/coh901318.c
4 * Copyright (C) 2007-2009 ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 * DMA driver for COH 901 318
7 * Author: Per Friden <per.friden@stericsson.com>
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h> /* printk() */
13 #include <linux/fs.h> /* everything... */
14 #include <linux/scatterlist.h>
15 #include <linux/slab.h> /* kmalloc() */
16 #include <linux/dmaengine.h>
17 #include <linux/platform_device.h>
18 #include <linux/device.h>
19 #include <linux/irqreturn.h>
20 #include <linux/interrupt.h>
22 #include <linux/uaccess.h>
23 #include <linux/debugfs.h>
24 #include <mach/coh901318.h>
26 #include "coh901318_lli.h"
27 #include "dmaengine.h"
29 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
32 #define COH_DBG(x) ({ if (1) x; 0; })
34 #define COH_DBG(x) ({ if (0) x; 0; })
37 struct coh901318_desc {
38 struct dma_async_tx_descriptor desc;
39 struct list_head node;
40 struct scatterlist *sg;
42 struct coh901318_lli *lli;
43 enum dma_transfer_direction dir;
49 struct coh901318_base {
51 void __iomem *virtbase;
52 struct coh901318_pool pool;
54 struct dma_device dma_slave;
55 struct dma_device dma_memcpy;
56 struct coh901318_chan *chans;
57 struct coh901318_platform *platform;
60 struct coh901318_chan {
66 struct work_struct free_work;
69 struct tasklet_struct tasklet;
71 struct list_head active;
72 struct list_head queue;
73 struct list_head free;
75 unsigned long nbr_active_done;
81 struct coh901318_base *base;
84 static void coh901318_list_print(struct coh901318_chan *cohc,
85 struct coh901318_lli *lli)
87 struct coh901318_lli *l = lli;
91 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
92 ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
93 i, l, l->control, l->src_addr, l->dst_addr,
94 l->link_addr, l->virt_link_addr);
96 l = l->virt_link_addr;
100 #ifdef CONFIG_DEBUG_FS
102 #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
104 static struct coh901318_base *debugfs_dma_base;
105 static struct dentry *dma_dentry;
107 static int coh901318_debugfs_open(struct inode *inode, struct file *file)
110 file->private_data = inode->i_private;
114 static int coh901318_debugfs_read(struct file *file, char __user *buf,
115 size_t count, loff_t *f_pos)
117 u64 started_channels = debugfs_dma_base->pm.started_channels;
118 int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
125 dev_buf = kmalloc(4*1024, GFP_KERNEL);
130 tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
132 for (i = 0; i < debugfs_dma_base->platform->max_channels; i++)
133 if (started_channels & (1 << i))
134 tmp += sprintf(tmp, "channel %d\n", i);
136 tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
137 dev_size = tmp - dev_buf;
139 /* No more to read if offset != 0 */
140 if (*f_pos > dev_size)
143 if (count > dev_size - *f_pos)
144 count = dev_size - *f_pos;
146 if (copy_to_user(buf, dev_buf + *f_pos, count))
159 static const struct file_operations coh901318_debugfs_status_operations = {
160 .owner = THIS_MODULE,
161 .open = coh901318_debugfs_open,
162 .read = coh901318_debugfs_read,
163 .llseek = default_llseek,
167 static int __init init_coh901318_debugfs(void)
170 dma_dentry = debugfs_create_dir("dma", NULL);
172 (void) debugfs_create_file("status",
175 &coh901318_debugfs_status_operations);
179 static void __exit exit_coh901318_debugfs(void)
181 debugfs_remove_recursive(dma_dentry);
184 module_init(init_coh901318_debugfs);
185 module_exit(exit_coh901318_debugfs);
188 #define COH901318_DEBUGFS_ASSIGN(x, y)
190 #endif /* CONFIG_DEBUG_FS */
192 static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
194 return container_of(chan, struct coh901318_chan, chan);
197 static inline dma_addr_t
198 cohc_dev_addr(struct coh901318_chan *cohc)
200 /* Runtime supplied address will take precedence */
201 if (cohc->runtime_addr)
202 return cohc->runtime_addr;
203 return cohc->base->platform->chan_conf[cohc->id].dev_addr;
206 static inline const struct coh901318_params *
207 cohc_chan_param(struct coh901318_chan *cohc)
209 return &cohc->base->platform->chan_conf[cohc->id].param;
212 static inline const struct coh_dma_channel *
213 cohc_chan_conf(struct coh901318_chan *cohc)
215 return &cohc->base->platform->chan_conf[cohc->id];
218 static void enable_powersave(struct coh901318_chan *cohc)
221 struct powersave *pm = &cohc->base->pm;
223 spin_lock_irqsave(&pm->lock, flags);
225 pm->started_channels &= ~(1ULL << cohc->id);
227 if (!pm->started_channels) {
228 /* DMA no longer intends to access memory */
229 cohc->base->platform->access_memory_state(cohc->base->dev,
233 spin_unlock_irqrestore(&pm->lock, flags);
235 static void disable_powersave(struct coh901318_chan *cohc)
238 struct powersave *pm = &cohc->base->pm;
240 spin_lock_irqsave(&pm->lock, flags);
242 if (!pm->started_channels) {
243 /* DMA intends to access memory */
244 cohc->base->platform->access_memory_state(cohc->base->dev,
248 pm->started_channels |= (1ULL << cohc->id);
250 spin_unlock_irqrestore(&pm->lock, flags);
253 static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
255 int channel = cohc->id;
256 void __iomem *virtbase = cohc->base->virtbase;
259 virtbase + COH901318_CX_CTRL +
260 COH901318_CX_CTRL_SPACING * channel);
264 static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
266 int channel = cohc->id;
267 void __iomem *virtbase = cohc->base->virtbase;
270 virtbase + COH901318_CX_CFG +
271 COH901318_CX_CFG_SPACING*channel);
276 static int coh901318_start(struct coh901318_chan *cohc)
279 int channel = cohc->id;
280 void __iomem *virtbase = cohc->base->virtbase;
282 disable_powersave(cohc);
284 val = readl(virtbase + COH901318_CX_CFG +
285 COH901318_CX_CFG_SPACING * channel);
288 val |= COH901318_CX_CFG_CH_ENABLE;
289 writel(val, virtbase + COH901318_CX_CFG +
290 COH901318_CX_CFG_SPACING * channel);
295 static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
296 struct coh901318_lli *lli)
298 int channel = cohc->id;
299 void __iomem *virtbase = cohc->base->virtbase;
301 BUG_ON(readl(virtbase + COH901318_CX_STAT +
302 COH901318_CX_STAT_SPACING*channel) &
303 COH901318_CX_STAT_ACTIVE);
305 writel(lli->src_addr,
306 virtbase + COH901318_CX_SRC_ADDR +
307 COH901318_CX_SRC_ADDR_SPACING * channel);
309 writel(lli->dst_addr, virtbase +
310 COH901318_CX_DST_ADDR +
311 COH901318_CX_DST_ADDR_SPACING * channel);
313 writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
314 COH901318_CX_LNK_ADDR_SPACING * channel);
316 writel(lli->control, virtbase + COH901318_CX_CTRL +
317 COH901318_CX_CTRL_SPACING * channel);
322 static struct coh901318_desc *
323 coh901318_desc_get(struct coh901318_chan *cohc)
325 struct coh901318_desc *desc;
327 if (list_empty(&cohc->free)) {
328 /* alloc new desc because we're out of used ones
329 * TODO: alloc a pile of descs instead of just one,
330 * avoid many small allocations.
332 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
335 INIT_LIST_HEAD(&desc->node);
336 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
338 /* Reuse an old desc. */
339 desc = list_first_entry(&cohc->free,
340 struct coh901318_desc,
342 list_del(&desc->node);
343 /* Initialize it a bit so it's not insane */
346 desc->desc.callback = NULL;
347 desc->desc.callback_param = NULL;
355 coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
357 list_add_tail(&cohd->node, &cohc->free);
360 /* call with irq lock held */
362 coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
364 list_add_tail(&desc->node, &cohc->active);
367 static struct coh901318_desc *
368 coh901318_first_active_get(struct coh901318_chan *cohc)
370 struct coh901318_desc *d;
372 if (list_empty(&cohc->active))
375 d = list_first_entry(&cohc->active,
376 struct coh901318_desc,
382 coh901318_desc_remove(struct coh901318_desc *cohd)
384 list_del(&cohd->node);
388 coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
390 list_add_tail(&desc->node, &cohc->queue);
393 static struct coh901318_desc *
394 coh901318_first_queued(struct coh901318_chan *cohc)
396 struct coh901318_desc *d;
398 if (list_empty(&cohc->queue))
401 d = list_first_entry(&cohc->queue,
402 struct coh901318_desc,
407 static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
409 struct coh901318_lli *lli = in_lli;
413 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
414 lli = lli->virt_link_addr;
420 * Get the number of bytes left to transfer on this channel,
421 * it is unwise to call this before stopping the channel for
422 * absolute measures, but for a rough guess you can still call
425 static u32 coh901318_get_bytes_left(struct dma_chan *chan)
427 struct coh901318_chan *cohc = to_coh901318_chan(chan);
428 struct coh901318_desc *cohd;
429 struct list_head *pos;
434 spin_lock_irqsave(&cohc->lock, flags);
437 * If there are many queued jobs, we iterate and add the
438 * size of them all. We take a special look on the first
439 * job though, since it is probably active.
441 list_for_each(pos, &cohc->active) {
443 * The first job in the list will be working on the
444 * hardware. The job can be stopped but still active,
445 * so that the transfer counter is somewhere inside
448 cohd = list_entry(pos, struct coh901318_desc, node);
451 struct coh901318_lli *lli;
454 /* Read current transfer count value */
455 left = readl(cohc->base->virtbase +
457 COH901318_CX_CTRL_SPACING * cohc->id) &
458 COH901318_CX_CTRL_TC_VALUE_MASK;
460 /* See if the transfer is linked... */
461 ladd = readl(cohc->base->virtbase +
462 COH901318_CX_LNK_ADDR +
463 COH901318_CX_LNK_ADDR_SPACING *
465 ~COH901318_CX_LNK_LINK_IMMEDIATE;
466 /* Single transaction */
471 * Linked transaction, follow the lli, find the
472 * currently processing lli, and proceed to the next
475 while (lli && lli->link_addr != ladd)
476 lli = lli->virt_link_addr;
479 lli = lli->virt_link_addr;
482 * Follow remaining lli links around to count the total
483 * number of bytes left
485 left += coh901318_get_bytes_in_lli(lli);
487 left += coh901318_get_bytes_in_lli(cohd->lli);
492 /* Also count bytes in the queued jobs */
493 list_for_each(pos, &cohc->queue) {
494 cohd = list_entry(pos, struct coh901318_desc, node);
495 left += coh901318_get_bytes_in_lli(cohd->lli);
498 spin_unlock_irqrestore(&cohc->lock, flags);
504 * Pauses a transfer without losing data. Enables power save.
505 * Use this function in conjunction with coh901318_resume.
507 static void coh901318_pause(struct dma_chan *chan)
511 struct coh901318_chan *cohc = to_coh901318_chan(chan);
512 int channel = cohc->id;
513 void __iomem *virtbase = cohc->base->virtbase;
515 spin_lock_irqsave(&cohc->lock, flags);
517 /* Disable channel in HW */
518 val = readl(virtbase + COH901318_CX_CFG +
519 COH901318_CX_CFG_SPACING * channel);
521 /* Stopping infinite transfer */
522 if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
523 (val & COH901318_CX_CFG_CH_ENABLE))
527 val &= ~COH901318_CX_CFG_CH_ENABLE;
528 /* Enable twice, HW bug work around */
529 writel(val, virtbase + COH901318_CX_CFG +
530 COH901318_CX_CFG_SPACING * channel);
531 writel(val, virtbase + COH901318_CX_CFG +
532 COH901318_CX_CFG_SPACING * channel);
534 /* Spin-wait for it to actually go inactive */
535 while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
536 channel) & COH901318_CX_STAT_ACTIVE)
539 /* Check if we stopped an active job */
540 if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
541 channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
544 enable_powersave(cohc);
546 spin_unlock_irqrestore(&cohc->lock, flags);
549 /* Resumes a transfer that has been stopped via 300_dma_stop(..).
550 Power save is handled.
552 static void coh901318_resume(struct dma_chan *chan)
556 struct coh901318_chan *cohc = to_coh901318_chan(chan);
557 int channel = cohc->id;
559 spin_lock_irqsave(&cohc->lock, flags);
561 disable_powersave(cohc);
564 /* Enable channel in HW */
565 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
566 COH901318_CX_CFG_SPACING * channel);
568 val |= COH901318_CX_CFG_CH_ENABLE;
570 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
571 COH901318_CX_CFG_SPACING*channel);
576 spin_unlock_irqrestore(&cohc->lock, flags);
579 bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
581 unsigned int ch_nr = (unsigned int) chan_id;
583 if (ch_nr == to_coh901318_chan(chan)->id)
588 EXPORT_SYMBOL(coh901318_filter_id);
591 * DMA channel allocation
593 static int coh901318_config(struct coh901318_chan *cohc,
594 struct coh901318_params *param)
597 const struct coh901318_params *p;
598 int channel = cohc->id;
599 void __iomem *virtbase = cohc->base->virtbase;
601 spin_lock_irqsave(&cohc->lock, flags);
606 p = &cohc->base->platform->chan_conf[channel].param;
608 /* Clear any pending BE or TC interrupt */
610 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
611 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
613 writel(1 << (channel - 32), virtbase +
614 COH901318_BE_INT_CLEAR2);
615 writel(1 << (channel - 32), virtbase +
616 COH901318_TC_INT_CLEAR2);
619 coh901318_set_conf(cohc, p->config);
620 coh901318_set_ctrl(cohc, p->ctrl_lli_last);
622 spin_unlock_irqrestore(&cohc->lock, flags);
627 /* must lock when calling this function
628 * start queued jobs, if any
629 * TODO: start all queued jobs in one go
631 * Returns descriptor if queued job is started otherwise NULL.
632 * If the queue is empty NULL is returned.
634 static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
636 struct coh901318_desc *cohd;
639 * start queued jobs, if any
640 * TODO: transmit all queued jobs in one go
642 cohd = coh901318_first_queued(cohc);
645 /* Remove from queue */
646 coh901318_desc_remove(cohd);
647 /* initiate DMA job */
650 coh901318_desc_submit(cohc, cohd);
652 /* Program the transaction head */
653 coh901318_set_conf(cohc, cohd->head_config);
654 coh901318_set_ctrl(cohc, cohd->head_ctrl);
655 coh901318_prep_linked_list(cohc, cohd->lli);
657 /* start dma job on this channel */
658 coh901318_start(cohc);
666 * This tasklet is called from the interrupt handler to
667 * handle each descriptor (DMA job) that is sent to a channel.
669 static void dma_tasklet(unsigned long data)
671 struct coh901318_chan *cohc = (struct coh901318_chan *) data;
672 struct coh901318_desc *cohd_fin;
674 dma_async_tx_callback callback;
675 void *callback_param;
677 dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
678 " nbr_active_done %ld\n", __func__,
679 cohc->id, cohc->nbr_active_done);
681 spin_lock_irqsave(&cohc->lock, flags);
683 /* get first active descriptor entry from list */
684 cohd_fin = coh901318_first_active_get(cohc);
686 if (cohd_fin == NULL)
689 /* locate callback to client */
690 callback = cohd_fin->desc.callback;
691 callback_param = cohd_fin->desc.callback_param;
693 /* sign this job as completed on the channel */
694 dma_cookie_complete(&cohd_fin->desc);
696 /* release the lli allocation and remove the descriptor */
697 coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
699 /* return desc to free-list */
700 coh901318_desc_remove(cohd_fin);
701 coh901318_desc_free(cohc, cohd_fin);
703 spin_unlock_irqrestore(&cohc->lock, flags);
705 /* Call the callback when we're done */
707 callback(callback_param);
709 spin_lock_irqsave(&cohc->lock, flags);
712 * If another interrupt fired while the tasklet was scheduling,
713 * we don't get called twice, so we have this number of active
714 * counter that keep track of the number of IRQs expected to
715 * be handled for this channel. If there happen to be more than
716 * one IRQ to be ack:ed, we simply schedule this tasklet again.
718 cohc->nbr_active_done--;
719 if (cohc->nbr_active_done) {
720 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
721 "came in while we were scheduling this tasklet\n");
722 if (cohc_chan_conf(cohc)->priority_high)
723 tasklet_hi_schedule(&cohc->tasklet);
725 tasklet_schedule(&cohc->tasklet);
728 spin_unlock_irqrestore(&cohc->lock, flags);
733 spin_unlock_irqrestore(&cohc->lock, flags);
734 dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
738 /* called from interrupt context */
739 static void dma_tc_handle(struct coh901318_chan *cohc)
742 * If the channel is not allocated, then we shouldn't have
743 * any TC interrupts on it.
745 if (!cohc->allocated) {
746 dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
747 "unallocated channel\n");
751 spin_lock(&cohc->lock);
754 * When we reach this point, at least one queue item
755 * should have been moved over from cohc->queue to
756 * cohc->active and run to completion, that is why we're
757 * getting a terminal count interrupt is it not?
758 * If you get this BUG() the most probable cause is that
759 * the individual nodes in the lli chain have IRQ enabled,
760 * so check your platform config for lli chain ctrl.
762 BUG_ON(list_empty(&cohc->active));
764 cohc->nbr_active_done++;
767 * This attempt to take a job from cohc->queue, put it
768 * into cohc->active and start it.
770 if (coh901318_queue_start(cohc) == NULL)
773 spin_unlock(&cohc->lock);
776 * This tasklet will remove items from cohc->active
777 * and thus terminates them.
779 if (cohc_chan_conf(cohc)->priority_high)
780 tasklet_hi_schedule(&cohc->tasklet);
782 tasklet_schedule(&cohc->tasklet);
786 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
792 struct coh901318_base *base = dev_id;
793 struct coh901318_chan *cohc;
794 void __iomem *virtbase = base->virtbase;
796 status1 = readl(virtbase + COH901318_INT_STATUS1);
797 status2 = readl(virtbase + COH901318_INT_STATUS2);
799 if (unlikely(status1 == 0 && status2 == 0)) {
800 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
804 /* TODO: consider handle IRQ in tasklet here to
805 * minimize interrupt latency */
807 /* Check the first 32 DMA channels for IRQ */
809 /* Find first bit set, return as a number. */
810 i = ffs(status1) - 1;
813 cohc = &base->chans[ch];
814 spin_lock(&cohc->lock);
816 /* Mask off this bit */
817 status1 &= ~(1 << i);
818 /* Check the individual channel bits */
819 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
820 dev_crit(COHC_2_DEV(cohc),
821 "DMA bus error on channel %d!\n", ch);
823 /* Clear BE interrupt */
824 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
826 /* Caused by TC, really? */
827 if (unlikely(!test_bit(i, virtbase +
828 COH901318_TC_INT_STATUS1))) {
829 dev_warn(COHC_2_DEV(cohc),
830 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
831 /* Clear TC interrupt */
833 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
835 /* Enable powersave if transfer has finished */
836 if (!(readl(virtbase + COH901318_CX_STAT +
837 COH901318_CX_STAT_SPACING*ch) &
838 COH901318_CX_STAT_ENABLED)) {
839 enable_powersave(cohc);
842 /* Must clear TC interrupt before calling
844 * in case tc_handle initiate a new dma job
846 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
851 spin_unlock(&cohc->lock);
854 /* Check the remaining 32 DMA channels for IRQ */
856 /* Find first bit set, return as a number. */
857 i = ffs(status2) - 1;
859 cohc = &base->chans[ch];
860 spin_lock(&cohc->lock);
862 /* Mask off this bit */
863 status2 &= ~(1 << i);
864 /* Check the individual channel bits */
865 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
866 dev_crit(COHC_2_DEV(cohc),
867 "DMA bus error on channel %d!\n", ch);
868 /* Clear BE interrupt */
870 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
872 /* Caused by TC, really? */
873 if (unlikely(!test_bit(i, virtbase +
874 COH901318_TC_INT_STATUS2))) {
875 dev_warn(COHC_2_DEV(cohc),
876 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
877 /* Clear TC interrupt */
878 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
881 /* Enable powersave if transfer has finished */
882 if (!(readl(virtbase + COH901318_CX_STAT +
883 COH901318_CX_STAT_SPACING*ch) &
884 COH901318_CX_STAT_ENABLED)) {
885 enable_powersave(cohc);
887 /* Must clear TC interrupt before calling
889 * in case tc_handle initiate a new dma job
891 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
896 spin_unlock(&cohc->lock);
902 static int coh901318_alloc_chan_resources(struct dma_chan *chan)
904 struct coh901318_chan *cohc = to_coh901318_chan(chan);
907 dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
910 if (chan->client_count > 1)
913 spin_lock_irqsave(&cohc->lock, flags);
915 coh901318_config(cohc, NULL);
918 chan->completed_cookie = chan->cookie = 1;
920 spin_unlock_irqrestore(&cohc->lock, flags);
926 coh901318_free_chan_resources(struct dma_chan *chan)
928 struct coh901318_chan *cohc = to_coh901318_chan(chan);
929 int channel = cohc->id;
932 spin_lock_irqsave(&cohc->lock, flags);
935 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
936 COH901318_CX_CFG_SPACING*channel);
937 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
938 COH901318_CX_CTRL_SPACING*channel);
942 spin_unlock_irqrestore(&cohc->lock, flags);
944 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
949 coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
951 struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
953 struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
957 spin_lock_irqsave(&cohc->lock, flags);
958 cookie = dma_cookie_assign(tx);
960 coh901318_desc_queue(cohc, cohd);
962 spin_unlock_irqrestore(&cohc->lock, flags);
967 static struct dma_async_tx_descriptor *
968 coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
969 size_t size, unsigned long flags)
971 struct coh901318_lli *lli;
972 struct coh901318_desc *cohd;
974 struct coh901318_chan *cohc = to_coh901318_chan(chan);
976 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
979 spin_lock_irqsave(&cohc->lock, flg);
981 dev_vdbg(COHC_2_DEV(cohc),
982 "[%s] channel %d src 0x%x dest 0x%x size %d\n",
983 __func__, cohc->id, src, dest, size);
985 if (flags & DMA_PREP_INTERRUPT)
986 /* Trigger interrupt after last lli */
987 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
989 lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
990 if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
993 lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
998 ret = coh901318_lli_fill_memcpy(
999 &cohc->base->pool, lli, src, size, dest,
1000 cohc_chan_param(cohc)->ctrl_lli_chained,
1005 COH_DBG(coh901318_list_print(cohc, lli));
1007 /* Pick a descriptor to handle this transfer */
1008 cohd = coh901318_desc_get(cohc);
1010 cohd->flags = flags;
1011 cohd->desc.tx_submit = coh901318_tx_submit;
1013 spin_unlock_irqrestore(&cohc->lock, flg);
1017 spin_unlock_irqrestore(&cohc->lock, flg);
1021 static struct dma_async_tx_descriptor *
1022 coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1023 unsigned int sg_len, enum dma_transfer_direction direction,
1024 unsigned long flags)
1026 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1027 struct coh901318_lli *lli;
1028 struct coh901318_desc *cohd;
1029 const struct coh901318_params *params;
1030 struct scatterlist *sg;
1034 u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
1035 u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
1036 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
1043 if (sgl->length == 0)
1046 spin_lock_irqsave(&cohc->lock, flg);
1048 dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
1049 __func__, sg_len, direction);
1051 if (flags & DMA_PREP_INTERRUPT)
1052 /* Trigger interrupt after last lli */
1053 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
1055 params = cohc_chan_param(cohc);
1056 config = params->config;
1058 * Add runtime-specific control on top, make
1059 * sure the bits you set per peripheral channel are
1060 * cleared in the default config from the platform.
1062 ctrl_chained |= cohc->runtime_ctrl;
1063 ctrl_last |= cohc->runtime_ctrl;
1064 ctrl |= cohc->runtime_ctrl;
1066 if (direction == DMA_MEM_TO_DEV) {
1067 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
1068 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
1070 config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
1071 ctrl_chained |= tx_flags;
1072 ctrl_last |= tx_flags;
1074 } else if (direction == DMA_DEV_TO_MEM) {
1075 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
1076 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
1078 config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
1079 ctrl_chained |= rx_flags;
1080 ctrl_last |= rx_flags;
1085 /* The dma only supports transmitting packages up to
1086 * MAX_DMA_PACKET_SIZE. Calculate to total number of
1087 * dma elemts required to send the entire sg list
1089 for_each_sg(sgl, sg, sg_len, i) {
1090 unsigned int factor;
1091 size = sg_dma_len(sg);
1093 if (size <= MAX_DMA_PACKET_SIZE) {
1098 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
1099 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
1105 pr_debug("Allocate %d lli:s for this transfer\n", len);
1106 lli = coh901318_lli_alloc(&cohc->base->pool, len);
1111 /* initiate allocated lli list */
1112 ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
1113 cohc_dev_addr(cohc),
1117 direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
1122 COH_DBG(coh901318_list_print(cohc, lli));
1124 /* Pick a descriptor to handle this transfer */
1125 cohd = coh901318_desc_get(cohc);
1126 cohd->head_config = config;
1128 * Set the default head ctrl for the channel to the one from the
1129 * lli, things may have changed due to odd buffer alignment
1132 cohd->head_ctrl = lli->control;
1133 cohd->dir = direction;
1134 cohd->flags = flags;
1135 cohd->desc.tx_submit = coh901318_tx_submit;
1138 spin_unlock_irqrestore(&cohc->lock, flg);
1144 spin_unlock_irqrestore(&cohc->lock, flg);
1149 static enum dma_status
1150 coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
1151 struct dma_tx_state *txstate)
1153 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1154 dma_cookie_t last_used;
1155 dma_cookie_t last_complete;
1158 last_complete = chan->completed_cookie;
1159 last_used = chan->cookie;
1161 ret = dma_async_is_complete(cookie, last_complete, last_used);
1163 dma_set_tx_state(txstate, last_complete, last_used,
1164 coh901318_get_bytes_left(chan));
1165 if (ret == DMA_IN_PROGRESS && cohc->stopped)
1172 coh901318_issue_pending(struct dma_chan *chan)
1174 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1175 unsigned long flags;
1177 spin_lock_irqsave(&cohc->lock, flags);
1180 * Busy means that pending jobs are already being processed,
1181 * and then there is no point in starting the queue: the
1182 * terminal count interrupt on the channel will take the next
1183 * job on the queue and execute it anyway.
1186 coh901318_queue_start(cohc);
1188 spin_unlock_irqrestore(&cohc->lock, flags);
1192 * Here we wrap in the runtime dma control interface
1194 struct burst_table {
1201 static const struct burst_table burst_sizes[] = {
1206 .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
1212 .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
1218 .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
1224 .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
1230 .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
1236 .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
1242 .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
1248 .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
1252 static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
1253 struct dma_slave_config *config)
1255 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1257 enum dma_slave_buswidth addr_width;
1259 u32 runtime_ctrl = 0;
1262 /* We only support mem to per or per to mem transfers */
1263 if (config->direction == DMA_DEV_TO_MEM) {
1264 addr = config->src_addr;
1265 addr_width = config->src_addr_width;
1266 maxburst = config->src_maxburst;
1267 } else if (config->direction == DMA_MEM_TO_DEV) {
1268 addr = config->dst_addr;
1269 addr_width = config->dst_addr_width;
1270 maxburst = config->dst_maxburst;
1272 dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
1276 dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
1278 switch (addr_width) {
1279 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1281 COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
1282 COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
1284 while (i < ARRAY_SIZE(burst_sizes)) {
1285 if (burst_sizes[i].burst_8bit <= maxburst)
1291 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1293 COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
1294 COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
1296 while (i < ARRAY_SIZE(burst_sizes)) {
1297 if (burst_sizes[i].burst_16bit <= maxburst)
1303 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1304 /* Direction doesn't matter here, it's 32/32 bits */
1306 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1307 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
1309 while (i < ARRAY_SIZE(burst_sizes)) {
1310 if (burst_sizes[i].burst_32bit <= maxburst)
1317 dev_err(COHC_2_DEV(cohc),
1318 "bad runtimeconfig: alien address width\n");
1322 runtime_ctrl |= burst_sizes[i].reg;
1323 dev_dbg(COHC_2_DEV(cohc),
1324 "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
1325 burst_sizes[i].burst_8bit, addr_width, maxburst);
1327 cohc->runtime_addr = addr;
1328 cohc->runtime_ctrl = runtime_ctrl;
1332 coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1335 unsigned long flags;
1336 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1337 struct coh901318_desc *cohd;
1338 void __iomem *virtbase = cohc->base->virtbase;
1340 if (cmd == DMA_SLAVE_CONFIG) {
1341 struct dma_slave_config *config =
1342 (struct dma_slave_config *) arg;
1344 coh901318_dma_set_runtimeconfig(chan, config);
1348 if (cmd == DMA_PAUSE) {
1349 coh901318_pause(chan);
1353 if (cmd == DMA_RESUME) {
1354 coh901318_resume(chan);
1358 if (cmd != DMA_TERMINATE_ALL)
1361 /* The remainder of this function terminates the transfer */
1362 coh901318_pause(chan);
1363 spin_lock_irqsave(&cohc->lock, flags);
1365 /* Clear any pending BE or TC interrupt */
1366 if (cohc->id < 32) {
1367 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
1368 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
1370 writel(1 << (cohc->id - 32), virtbase +
1371 COH901318_BE_INT_CLEAR2);
1372 writel(1 << (cohc->id - 32), virtbase +
1373 COH901318_TC_INT_CLEAR2);
1376 enable_powersave(cohc);
1378 while ((cohd = coh901318_first_active_get(cohc))) {
1379 /* release the lli allocation*/
1380 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1382 /* return desc to free-list */
1383 coh901318_desc_remove(cohd);
1384 coh901318_desc_free(cohc, cohd);
1387 while ((cohd = coh901318_first_queued(cohc))) {
1388 /* release the lli allocation*/
1389 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1391 /* return desc to free-list */
1392 coh901318_desc_remove(cohd);
1393 coh901318_desc_free(cohc, cohd);
1397 cohc->nbr_active_done = 0;
1400 spin_unlock_irqrestore(&cohc->lock, flags);
1405 void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
1406 struct coh901318_base *base)
1410 struct coh901318_chan *cohc;
1412 INIT_LIST_HEAD(&dma->channels);
1414 for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
1415 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
1416 cohc = &base->chans[i];
1419 cohc->chan.device = dma;
1422 /* TODO: do we really need this lock if only one
1423 * client is connected to each channel?
1426 spin_lock_init(&cohc->lock);
1428 cohc->nbr_active_done = 0;
1430 INIT_LIST_HEAD(&cohc->free);
1431 INIT_LIST_HEAD(&cohc->active);
1432 INIT_LIST_HEAD(&cohc->queue);
1434 tasklet_init(&cohc->tasklet, dma_tasklet,
1435 (unsigned long) cohc);
1437 list_add_tail(&cohc->chan.device_node,
1443 static int __init coh901318_probe(struct platform_device *pdev)
1446 struct coh901318_platform *pdata;
1447 struct coh901318_base *base;
1449 struct resource *io;
1451 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1453 goto err_get_resource;
1455 /* Map DMA controller registers to virtual memory */
1456 if (request_mem_region(io->start,
1458 pdev->dev.driver->name) == NULL) {
1460 goto err_request_mem;
1463 pdata = pdev->dev.platform_data;
1465 goto err_no_platformdata;
1467 base = kmalloc(ALIGN(sizeof(struct coh901318_base), 4) +
1468 pdata->max_channels *
1469 sizeof(struct coh901318_chan),
1472 goto err_alloc_coh_dma_channels;
1474 base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
1476 base->virtbase = ioremap(io->start, resource_size(io));
1477 if (!base->virtbase) {
1479 goto err_no_ioremap;
1482 base->dev = &pdev->dev;
1483 base->platform = pdata;
1484 spin_lock_init(&base->pm.lock);
1485 base->pm.started_channels = 0;
1487 COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
1489 platform_set_drvdata(pdev, base);
1491 irq = platform_get_irq(pdev, 0);
1495 err = request_irq(irq, dma_irq_handler, IRQF_DISABLED,
1498 dev_crit(&pdev->dev,
1499 "Cannot allocate IRQ for DMA controller!\n");
1500 goto err_request_irq;
1503 err = coh901318_pool_create(&base->pool, &pdev->dev,
1504 sizeof(struct coh901318_lli),
1507 goto err_pool_create;
1509 /* init channels for device transfers */
1510 coh901318_base_init(&base->dma_slave, base->platform->chans_slave,
1513 dma_cap_zero(base->dma_slave.cap_mask);
1514 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
1516 base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1517 base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
1518 base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
1519 base->dma_slave.device_tx_status = coh901318_tx_status;
1520 base->dma_slave.device_issue_pending = coh901318_issue_pending;
1521 base->dma_slave.device_control = coh901318_control;
1522 base->dma_slave.dev = &pdev->dev;
1524 err = dma_async_device_register(&base->dma_slave);
1527 goto err_register_slave;
1529 /* init channels for memcpy */
1530 coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy,
1533 dma_cap_zero(base->dma_memcpy.cap_mask);
1534 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
1536 base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1537 base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
1538 base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
1539 base->dma_memcpy.device_tx_status = coh901318_tx_status;
1540 base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
1541 base->dma_memcpy.device_control = coh901318_control;
1542 base->dma_memcpy.dev = &pdev->dev;
1544 * This controller can only access address at even 32bit boundaries,
1547 base->dma_memcpy.copy_align = 2;
1548 err = dma_async_device_register(&base->dma_memcpy);
1551 goto err_register_memcpy;
1553 dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
1554 (u32) base->virtbase);
1558 err_register_memcpy:
1559 dma_async_device_unregister(&base->dma_slave);
1561 coh901318_pool_destroy(&base->pool);
1563 free_irq(platform_get_irq(pdev, 0), base);
1566 iounmap(base->virtbase);
1569 err_alloc_coh_dma_channels:
1570 err_no_platformdata:
1571 release_mem_region(pdev->resource->start,
1572 resource_size(pdev->resource));
1578 static int __exit coh901318_remove(struct platform_device *pdev)
1580 struct coh901318_base *base = platform_get_drvdata(pdev);
1582 dma_async_device_unregister(&base->dma_memcpy);
1583 dma_async_device_unregister(&base->dma_slave);
1584 coh901318_pool_destroy(&base->pool);
1585 free_irq(platform_get_irq(pdev, 0), base);
1586 iounmap(base->virtbase);
1588 release_mem_region(pdev->resource->start,
1589 resource_size(pdev->resource));
1594 static struct platform_driver coh901318_driver = {
1595 .remove = __exit_p(coh901318_remove),
1597 .name = "coh901318",
1601 int __init coh901318_init(void)
1603 return platform_driver_probe(&coh901318_driver, coh901318_probe);
1605 subsys_initcall(coh901318_init);
1607 void __exit coh901318_exit(void)
1609 platform_driver_unregister(&coh901318_driver);
1611 module_exit(coh901318_exit);
1613 MODULE_LICENSE("GPL");
1614 MODULE_AUTHOR("Per Friden");