2 * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems)
4 * Copyright (C) 2008 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 * This supports the Atmel AHB DMA Controller,
14 * The driver has currently been tested with the Atmel AT91SAM9RL
15 * and AT91SAM9G45 series.
18 #include <linux/clk.h>
19 #include <linux/dmaengine.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/dmapool.h>
22 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
27 #include <linux/of_device.h>
29 #include "at_hdmac_regs.h"
30 #include "dmaengine.h"
36 * at_hdmac : Name of the ATmel AHB DMA Controller
37 * at_dma_ / atdma : ATmel DMA controller entity related
38 * atc_ / atchan : ATmel DMA Channel entity related
41 #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO)
42 #define ATC_DEFAULT_CTRLA (0)
43 #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \
44 |ATC_DIF(AT_DMA_MEM_IF))
47 * Initial number of descriptors to allocate for each channel. This could
48 * be increased during dma usage.
50 static unsigned int init_nr_desc_per_channel = 64;
51 module_param(init_nr_desc_per_channel, uint, 0644);
52 MODULE_PARM_DESC(init_nr_desc_per_channel,
53 "initial descriptors per channel (default: 64)");
57 static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx);
60 /*----------------------------------------------------------------------*/
62 static struct at_desc *atc_first_active(struct at_dma_chan *atchan)
64 return list_first_entry(&atchan->active_list,
65 struct at_desc, desc_node);
68 static struct at_desc *atc_first_queued(struct at_dma_chan *atchan)
70 return list_first_entry(&atchan->queue,
71 struct at_desc, desc_node);
75 * atc_alloc_descriptor - allocate and return an initialized descriptor
76 * @chan: the channel to allocate descriptors for
77 * @gfp_flags: GFP allocation flags
79 * Note: The ack-bit is positioned in the descriptor flag at creation time
80 * to make initial allocation more convenient. This bit will be cleared
81 * and control will be given to client at usage time (during
82 * preparation functions).
84 static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan,
87 struct at_desc *desc = NULL;
88 struct at_dma *atdma = to_at_dma(chan->device);
91 desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys);
93 memset(desc, 0, sizeof(struct at_desc));
94 INIT_LIST_HEAD(&desc->tx_list);
95 dma_async_tx_descriptor_init(&desc->txd, chan);
96 /* txd.flags will be overwritten in prep functions */
97 desc->txd.flags = DMA_CTRL_ACK;
98 desc->txd.tx_submit = atc_tx_submit;
99 desc->txd.phys = phys;
106 * atc_desc_get - get an unused descriptor from free_list
107 * @atchan: channel we want a new descriptor for
109 static struct at_desc *atc_desc_get(struct at_dma_chan *atchan)
111 struct at_desc *desc, *_desc;
112 struct at_desc *ret = NULL;
117 spin_lock_irqsave(&atchan->lock, flags);
118 list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
120 if (async_tx_test_ack(&desc->txd)) {
121 list_del(&desc->desc_node);
125 dev_dbg(chan2dev(&atchan->chan_common),
126 "desc %p not ACKed\n", desc);
128 spin_unlock_irqrestore(&atchan->lock, flags);
129 dev_vdbg(chan2dev(&atchan->chan_common),
130 "scanned %u descriptors on freelist\n", i);
132 /* no more descriptor available in initial pool: create one more */
134 ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC);
136 spin_lock_irqsave(&atchan->lock, flags);
137 atchan->descs_allocated++;
138 spin_unlock_irqrestore(&atchan->lock, flags);
140 dev_err(chan2dev(&atchan->chan_common),
141 "not enough descriptors available\n");
149 * atc_desc_put - move a descriptor, including any children, to the free list
150 * @atchan: channel we work on
151 * @desc: descriptor, at the head of a chain, to move to free list
153 static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc)
156 struct at_desc *child;
159 spin_lock_irqsave(&atchan->lock, flags);
160 list_for_each_entry(child, &desc->tx_list, desc_node)
161 dev_vdbg(chan2dev(&atchan->chan_common),
162 "moving child desc %p to freelist\n",
164 list_splice_init(&desc->tx_list, &atchan->free_list);
165 dev_vdbg(chan2dev(&atchan->chan_common),
166 "moving desc %p to freelist\n", desc);
167 list_add(&desc->desc_node, &atchan->free_list);
168 spin_unlock_irqrestore(&atchan->lock, flags);
173 * atc_desc_chain - build chain adding a descripor
174 * @first: address of first descripor of the chain
175 * @prev: address of previous descripor of the chain
176 * @desc: descriptor to queue
178 * Called from prep_* functions
180 static void atc_desc_chain(struct at_desc **first, struct at_desc **prev,
181 struct at_desc *desc)
186 /* inform the HW lli about chaining */
187 (*prev)->lli.dscr = desc->txd.phys;
188 /* insert the link descriptor to the LD ring */
189 list_add_tail(&desc->desc_node,
196 * atc_dostart - starts the DMA engine for real
197 * @atchan: the channel we want to start
198 * @first: first descriptor in the list we want to begin with
200 * Called with atchan->lock held and bh disabled
202 static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first)
204 struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
206 /* ASSERT: channel is idle */
207 if (atc_chan_is_enabled(atchan)) {
208 dev_err(chan2dev(&atchan->chan_common),
209 "BUG: Attempted to start non-idle channel\n");
210 dev_err(chan2dev(&atchan->chan_common),
211 " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n",
212 channel_readl(atchan, SADDR),
213 channel_readl(atchan, DADDR),
214 channel_readl(atchan, CTRLA),
215 channel_readl(atchan, CTRLB),
216 channel_readl(atchan, DSCR));
218 /* The tasklet will hopefully advance the queue... */
222 vdbg_dump_regs(atchan);
224 /* clear any pending interrupt */
225 while (dma_readl(atdma, EBCISR))
228 channel_writel(atchan, SADDR, 0);
229 channel_writel(atchan, DADDR, 0);
230 channel_writel(atchan, CTRLA, 0);
231 channel_writel(atchan, CTRLB, 0);
232 channel_writel(atchan, DSCR, first->txd.phys);
233 dma_writel(atdma, CHER, atchan->mask);
235 vdbg_dump_regs(atchan);
239 * atc_chain_complete - finish work for one transaction chain
240 * @atchan: channel we work on
241 * @desc: descriptor at the head of the chain we want do complete
243 * Called with atchan->lock held and bh disabled */
245 atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
247 struct dma_async_tx_descriptor *txd = &desc->txd;
249 dev_vdbg(chan2dev(&atchan->chan_common),
250 "descriptor %u complete\n", txd->cookie);
252 atchan->chan_common.completed_cookie = txd->cookie;
254 /* move children to free_list */
255 list_splice_init(&desc->tx_list, &atchan->free_list);
256 /* move myself to free_list */
257 list_move(&desc->desc_node, &atchan->free_list);
259 /* unmap dma addresses (not on slave channels) */
260 if (!atchan->chan_common.private) {
261 struct device *parent = chan2parent(&atchan->chan_common);
262 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
263 if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
264 dma_unmap_single(parent,
266 desc->len, DMA_FROM_DEVICE);
268 dma_unmap_page(parent,
270 desc->len, DMA_FROM_DEVICE);
272 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
273 if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
274 dma_unmap_single(parent,
276 desc->len, DMA_TO_DEVICE);
278 dma_unmap_page(parent,
280 desc->len, DMA_TO_DEVICE);
284 /* for cyclic transfers,
285 * no need to replay callback function while stopping */
286 if (!atc_chan_is_cyclic(atchan)) {
287 dma_async_tx_callback callback = txd->callback;
288 void *param = txd->callback_param;
291 * The API requires that no submissions are done from a
292 * callback, so we don't need to drop the lock here
298 dma_run_dependencies(txd);
302 * atc_complete_all - finish work for all transactions
303 * @atchan: channel to complete transactions for
305 * Eventually submit queued descriptors if any
307 * Assume channel is idle while calling this function
308 * Called with atchan->lock held and bh disabled
310 static void atc_complete_all(struct at_dma_chan *atchan)
312 struct at_desc *desc, *_desc;
315 dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n");
317 BUG_ON(atc_chan_is_enabled(atchan));
320 * Submit queued descriptors ASAP, i.e. before we go through
321 * the completed ones.
323 if (!list_empty(&atchan->queue))
324 atc_dostart(atchan, atc_first_queued(atchan));
325 /* empty active_list now it is completed */
326 list_splice_init(&atchan->active_list, &list);
327 /* empty queue list by moving descriptors (if any) to active_list */
328 list_splice_init(&atchan->queue, &atchan->active_list);
330 list_for_each_entry_safe(desc, _desc, &list, desc_node)
331 atc_chain_complete(atchan, desc);
335 * atc_cleanup_descriptors - cleanup up finished descriptors in active_list
336 * @atchan: channel to be cleaned up
338 * Called with atchan->lock held and bh disabled
340 static void atc_cleanup_descriptors(struct at_dma_chan *atchan)
342 struct at_desc *desc, *_desc;
343 struct at_desc *child;
345 dev_vdbg(chan2dev(&atchan->chan_common), "cleanup descriptors\n");
347 list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) {
348 if (!(desc->lli.ctrla & ATC_DONE))
349 /* This one is currently in progress */
352 list_for_each_entry(child, &desc->tx_list, desc_node)
353 if (!(child->lli.ctrla & ATC_DONE))
354 /* Currently in progress */
358 * No descriptors so far seem to be in progress, i.e.
359 * this chain must be done.
361 atc_chain_complete(atchan, desc);
366 * atc_advance_work - at the end of a transaction, move forward
367 * @atchan: channel where the transaction ended
369 * Called with atchan->lock held and bh disabled
371 static void atc_advance_work(struct at_dma_chan *atchan)
373 dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n");
375 if (list_empty(&atchan->active_list) ||
376 list_is_singular(&atchan->active_list)) {
377 atc_complete_all(atchan);
379 atc_chain_complete(atchan, atc_first_active(atchan));
381 atc_dostart(atchan, atc_first_active(atchan));
387 * atc_handle_error - handle errors reported by DMA controller
388 * @atchan: channel where error occurs
390 * Called with atchan->lock held and bh disabled
392 static void atc_handle_error(struct at_dma_chan *atchan)
394 struct at_desc *bad_desc;
395 struct at_desc *child;
398 * The descriptor currently at the head of the active list is
399 * broked. Since we don't have any way to report errors, we'll
400 * just have to scream loudly and try to carry on.
402 bad_desc = atc_first_active(atchan);
403 list_del_init(&bad_desc->desc_node);
405 /* As we are stopped, take advantage to push queued descriptors
407 list_splice_init(&atchan->queue, atchan->active_list.prev);
409 /* Try to restart the controller */
410 if (!list_empty(&atchan->active_list))
411 atc_dostart(atchan, atc_first_active(atchan));
414 * KERN_CRITICAL may seem harsh, but since this only happens
415 * when someone submits a bad physical address in a
416 * descriptor, we should consider ourselves lucky that the
417 * controller flagged an error instead of scribbling over
418 * random memory locations.
420 dev_crit(chan2dev(&atchan->chan_common),
421 "Bad descriptor submitted for DMA!\n");
422 dev_crit(chan2dev(&atchan->chan_common),
423 " cookie: %d\n", bad_desc->txd.cookie);
424 atc_dump_lli(atchan, &bad_desc->lli);
425 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
426 atc_dump_lli(atchan, &child->lli);
428 /* Pretend the descriptor completed successfully */
429 atc_chain_complete(atchan, bad_desc);
433 * atc_handle_cyclic - at the end of a period, run callback function
434 * @atchan: channel used for cyclic operations
436 * Called with atchan->lock held and bh disabled
438 static void atc_handle_cyclic(struct at_dma_chan *atchan)
440 struct at_desc *first = atc_first_active(atchan);
441 struct dma_async_tx_descriptor *txd = &first->txd;
442 dma_async_tx_callback callback = txd->callback;
443 void *param = txd->callback_param;
445 dev_vdbg(chan2dev(&atchan->chan_common),
446 "new cyclic period llp 0x%08x\n",
447 channel_readl(atchan, DSCR));
453 /*-- IRQ & Tasklet ---------------------------------------------------*/
455 static void atc_tasklet(unsigned long data)
457 struct at_dma_chan *atchan = (struct at_dma_chan *)data;
460 spin_lock_irqsave(&atchan->lock, flags);
461 if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status))
462 atc_handle_error(atchan);
463 else if (atc_chan_is_cyclic(atchan))
464 atc_handle_cyclic(atchan);
466 atc_advance_work(atchan);
468 spin_unlock_irqrestore(&atchan->lock, flags);
471 static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
473 struct at_dma *atdma = (struct at_dma *)dev_id;
474 struct at_dma_chan *atchan;
476 u32 status, pending, imr;
480 imr = dma_readl(atdma, EBCIMR);
481 status = dma_readl(atdma, EBCISR);
482 pending = status & imr;
487 dev_vdbg(atdma->dma_common.dev,
488 "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n",
489 status, imr, pending);
491 for (i = 0; i < atdma->dma_common.chancnt; i++) {
492 atchan = &atdma->chan[i];
493 if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) {
494 if (pending & AT_DMA_ERR(i)) {
495 /* Disable channel on AHB error */
496 dma_writel(atdma, CHDR,
497 AT_DMA_RES(i) | atchan->mask);
498 /* Give information to tasklet */
499 set_bit(ATC_IS_ERROR, &atchan->status);
501 tasklet_schedule(&atchan->tasklet);
512 /*-- DMA Engine API --------------------------------------------------*/
515 * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine
516 * @desc: descriptor at the head of the transaction chain
518 * Queue chain if DMA engine is working already
520 * Cookie increment and adding to active_list or queue must be atomic
522 static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx)
524 struct at_desc *desc = txd_to_at_desc(tx);
525 struct at_dma_chan *atchan = to_at_dma_chan(tx->chan);
529 spin_lock_irqsave(&atchan->lock, flags);
530 cookie = dma_cookie_assign(tx);
532 if (list_empty(&atchan->active_list)) {
533 dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
535 atc_dostart(atchan, desc);
536 list_add_tail(&desc->desc_node, &atchan->active_list);
538 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
540 list_add_tail(&desc->desc_node, &atchan->queue);
543 spin_unlock_irqrestore(&atchan->lock, flags);
549 * atc_prep_dma_memcpy - prepare a memcpy operation
550 * @chan: the channel to prepare operation on
551 * @dest: operation virtual destination address
552 * @src: operation virtual source address
553 * @len: operation length
554 * @flags: tx descriptor status flags
556 static struct dma_async_tx_descriptor *
557 atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
558 size_t len, unsigned long flags)
560 struct at_dma_chan *atchan = to_at_dma_chan(chan);
561 struct at_desc *desc = NULL;
562 struct at_desc *first = NULL;
563 struct at_desc *prev = NULL;
566 unsigned int src_width;
567 unsigned int dst_width;
571 dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n",
572 dest, src, len, flags);
574 if (unlikely(!len)) {
575 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
579 ctrla = ATC_DEFAULT_CTRLA;
580 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN
581 | ATC_SRC_ADDR_MODE_INCR
582 | ATC_DST_ADDR_MODE_INCR
586 * We can be a lot more clever here, but this should take care
587 * of the most common optimization.
589 if (!((src | dest | len) & 3)) {
590 ctrla |= ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD;
591 src_width = dst_width = 2;
592 } else if (!((src | dest | len) & 1)) {
593 ctrla |= ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD;
594 src_width = dst_width = 1;
596 ctrla |= ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE;
597 src_width = dst_width = 0;
600 for (offset = 0; offset < len; offset += xfer_count << src_width) {
601 xfer_count = min_t(size_t, (len - offset) >> src_width,
604 desc = atc_desc_get(atchan);
608 desc->lli.saddr = src + offset;
609 desc->lli.daddr = dest + offset;
610 desc->lli.ctrla = ctrla | xfer_count;
611 desc->lli.ctrlb = ctrlb;
613 desc->txd.cookie = 0;
615 atc_desc_chain(&first, &prev, desc);
618 /* First descriptor of the chain embedds additional information */
619 first->txd.cookie = -EBUSY;
622 /* set end-of-link to the last link descriptor of list*/
625 first->txd.flags = flags; /* client is in control of this ack */
630 atc_desc_put(atchan, first);
636 * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
638 * @sgl: scatterlist to transfer to/from
639 * @sg_len: number of entries in @scatterlist
640 * @direction: DMA direction
641 * @flags: tx descriptor status flags
643 static struct dma_async_tx_descriptor *
644 atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
645 unsigned int sg_len, enum dma_transfer_direction direction,
648 struct at_dma_chan *atchan = to_at_dma_chan(chan);
649 struct at_dma_slave *atslave = chan->private;
650 struct at_desc *first = NULL;
651 struct at_desc *prev = NULL;
655 unsigned int reg_width;
656 unsigned int mem_width;
658 struct scatterlist *sg;
659 size_t total_len = 0;
661 dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n",
663 direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
666 if (unlikely(!atslave || !sg_len)) {
667 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
671 reg_width = atslave->reg_width;
673 ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla;
678 ctrla |= ATC_DST_WIDTH(reg_width);
679 ctrlb |= ATC_DST_ADDR_MODE_FIXED
680 | ATC_SRC_ADDR_MODE_INCR
682 | ATC_SIF(AT_DMA_MEM_IF) | ATC_DIF(AT_DMA_PER_IF);
683 reg = atslave->tx_reg;
684 for_each_sg(sgl, sg, sg_len, i) {
685 struct at_desc *desc;
689 desc = atc_desc_get(atchan);
693 mem = sg_dma_address(sg);
694 len = sg_dma_len(sg);
696 if (unlikely(mem & 3 || len & 3))
699 desc->lli.saddr = mem;
700 desc->lli.daddr = reg;
701 desc->lli.ctrla = ctrla
702 | ATC_SRC_WIDTH(mem_width)
704 desc->lli.ctrlb = ctrlb;
706 atc_desc_chain(&first, &prev, desc);
711 ctrla |= ATC_SRC_WIDTH(reg_width);
712 ctrlb |= ATC_DST_ADDR_MODE_INCR
713 | ATC_SRC_ADDR_MODE_FIXED
715 | ATC_SIF(AT_DMA_PER_IF) | ATC_DIF(AT_DMA_MEM_IF);
717 reg = atslave->rx_reg;
718 for_each_sg(sgl, sg, sg_len, i) {
719 struct at_desc *desc;
723 desc = atc_desc_get(atchan);
727 mem = sg_dma_address(sg);
728 len = sg_dma_len(sg);
730 if (unlikely(mem & 3 || len & 3))
733 desc->lli.saddr = reg;
734 desc->lli.daddr = mem;
735 desc->lli.ctrla = ctrla
736 | ATC_DST_WIDTH(mem_width)
738 desc->lli.ctrlb = ctrlb;
740 atc_desc_chain(&first, &prev, desc);
748 /* set end-of-link to the last link descriptor of list*/
751 /* First descriptor of the chain embedds additional information */
752 first->txd.cookie = -EBUSY;
753 first->len = total_len;
755 /* first link descriptor of list is responsible of flags */
756 first->txd.flags = flags; /* client is in control of this ack */
761 dev_err(chan2dev(chan), "not enough descriptors available\n");
762 atc_desc_put(atchan, first);
767 * atc_dma_cyclic_check_values
768 * Check for too big/unaligned periods and unaligned DMA buffer
771 atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr,
772 size_t period_len, enum dma_transfer_direction direction)
774 if (period_len > (ATC_BTSIZE_MAX << reg_width))
776 if (unlikely(period_len & ((1 << reg_width) - 1)))
778 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
780 if (unlikely(!(direction & (DMA_DEV_TO_MEM | DMA_MEM_TO_DEV))))
790 * atc_dma_cyclic_fill_desc - Fill one period decriptor
793 atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
794 unsigned int period_index, dma_addr_t buf_addr,
795 size_t period_len, enum dma_transfer_direction direction)
798 unsigned int reg_width = atslave->reg_width;
800 /* prepare common CRTLA value */
801 ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla
802 | ATC_DST_WIDTH(reg_width)
803 | ATC_SRC_WIDTH(reg_width)
804 | period_len >> reg_width;
808 desc->lli.saddr = buf_addr + (period_len * period_index);
809 desc->lli.daddr = atslave->tx_reg;
810 desc->lli.ctrla = ctrla;
811 desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED
812 | ATC_SRC_ADDR_MODE_INCR
814 | ATC_SIF(AT_DMA_MEM_IF)
815 | ATC_DIF(AT_DMA_PER_IF);
819 desc->lli.saddr = atslave->rx_reg;
820 desc->lli.daddr = buf_addr + (period_len * period_index);
821 desc->lli.ctrla = ctrla;
822 desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR
823 | ATC_SRC_ADDR_MODE_FIXED
825 | ATC_SIF(AT_DMA_PER_IF)
826 | ATC_DIF(AT_DMA_MEM_IF);
837 * atc_prep_dma_cyclic - prepare the cyclic DMA transfer
838 * @chan: the DMA channel to prepare
839 * @buf_addr: physical DMA address where the buffer starts
840 * @buf_len: total number of bytes for the entire buffer
841 * @period_len: number of bytes for each period
842 * @direction: transfer direction, to or from device
844 static struct dma_async_tx_descriptor *
845 atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
846 size_t period_len, enum dma_transfer_direction direction)
848 struct at_dma_chan *atchan = to_at_dma_chan(chan);
849 struct at_dma_slave *atslave = chan->private;
850 struct at_desc *first = NULL;
851 struct at_desc *prev = NULL;
852 unsigned long was_cyclic;
853 unsigned int periods = buf_len / period_len;
856 dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n",
857 direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
859 periods, buf_len, period_len);
861 if (unlikely(!atslave || !buf_len || !period_len)) {
862 dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n");
866 was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status);
868 dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n");
872 /* Check for too big/unaligned periods and unaligned DMA buffer */
873 if (atc_dma_cyclic_check_values(atslave->reg_width, buf_addr,
874 period_len, direction))
877 /* build cyclic linked list */
878 for (i = 0; i < periods; i++) {
879 struct at_desc *desc;
881 desc = atc_desc_get(atchan);
885 if (atc_dma_cyclic_fill_desc(atslave, desc, i, buf_addr,
886 period_len, direction))
889 atc_desc_chain(&first, &prev, desc);
892 /* lets make a cyclic list */
893 prev->lli.dscr = first->txd.phys;
895 /* First descriptor of the chain embedds additional information */
896 first->txd.cookie = -EBUSY;
897 first->len = buf_len;
902 dev_err(chan2dev(chan), "not enough descriptors available\n");
903 atc_desc_put(atchan, first);
905 clear_bit(ATC_IS_CYCLIC, &atchan->status);
910 static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
913 struct at_dma_chan *atchan = to_at_dma_chan(chan);
914 struct at_dma *atdma = to_at_dma(chan->device);
915 int chan_id = atchan->chan_common.chan_id;
920 dev_vdbg(chan2dev(chan), "atc_control (%d)\n", cmd);
922 if (cmd == DMA_PAUSE) {
923 spin_lock_irqsave(&atchan->lock, flags);
925 dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id));
926 set_bit(ATC_IS_PAUSED, &atchan->status);
928 spin_unlock_irqrestore(&atchan->lock, flags);
929 } else if (cmd == DMA_RESUME) {
930 if (!atc_chan_is_paused(atchan))
933 spin_lock_irqsave(&atchan->lock, flags);
935 dma_writel(atdma, CHDR, AT_DMA_RES(chan_id));
936 clear_bit(ATC_IS_PAUSED, &atchan->status);
938 spin_unlock_irqrestore(&atchan->lock, flags);
939 } else if (cmd == DMA_TERMINATE_ALL) {
940 struct at_desc *desc, *_desc;
942 * This is only called when something went wrong elsewhere, so
943 * we don't really care about the data. Just disable the
944 * channel. We still have to poll the channel enable bit due
945 * to AHB/HSB limitations.
947 spin_lock_irqsave(&atchan->lock, flags);
949 /* disabling channel: must also remove suspend state */
950 dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask);
952 /* confirm that this channel is disabled */
953 while (dma_readl(atdma, CHSR) & atchan->mask)
956 /* active_list entries will end up before queued entries */
957 list_splice_init(&atchan->queue, &list);
958 list_splice_init(&atchan->active_list, &list);
960 /* Flush all pending and queued descriptors */
961 list_for_each_entry_safe(desc, _desc, &list, desc_node)
962 atc_chain_complete(atchan, desc);
964 clear_bit(ATC_IS_PAUSED, &atchan->status);
965 /* if channel dedicated to cyclic operations, free it */
966 clear_bit(ATC_IS_CYCLIC, &atchan->status);
968 spin_unlock_irqrestore(&atchan->lock, flags);
977 * atc_tx_status - poll for transaction completion
979 * @cookie: transaction identifier to check status of
980 * @txstate: if not %NULL updated with transaction state
982 * If @txstate is passed in, upon return it reflect the driver
983 * internal state and can be used with dma_async_is_complete() to check
984 * the status of multiple cookies without re-checking hardware state.
986 static enum dma_status
987 atc_tx_status(struct dma_chan *chan,
989 struct dma_tx_state *txstate)
991 struct at_dma_chan *atchan = to_at_dma_chan(chan);
992 dma_cookie_t last_used;
993 dma_cookie_t last_complete;
997 spin_lock_irqsave(&atchan->lock, flags);
999 last_complete = chan->completed_cookie;
1000 last_used = chan->cookie;
1002 ret = dma_async_is_complete(cookie, last_complete, last_used);
1003 if (ret != DMA_SUCCESS) {
1004 atc_cleanup_descriptors(atchan);
1006 last_complete = chan->completed_cookie;
1007 last_used = chan->cookie;
1009 ret = dma_async_is_complete(cookie, last_complete, last_used);
1012 spin_unlock_irqrestore(&atchan->lock, flags);
1014 if (ret != DMA_SUCCESS)
1015 dma_set_tx_state(txstate, last_complete, last_used,
1016 atc_first_active(atchan)->len);
1018 dma_set_tx_state(txstate, last_complete, last_used, 0);
1020 if (atc_chan_is_paused(atchan))
1023 dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d (d%d, u%d)\n",
1024 ret, cookie, last_complete ? last_complete : 0,
1025 last_used ? last_used : 0);
1031 * atc_issue_pending - try to finish work
1032 * @chan: target DMA channel
1034 static void atc_issue_pending(struct dma_chan *chan)
1036 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1037 unsigned long flags;
1039 dev_vdbg(chan2dev(chan), "issue_pending\n");
1041 /* Not needed for cyclic transfers */
1042 if (atc_chan_is_cyclic(atchan))
1045 spin_lock_irqsave(&atchan->lock, flags);
1046 if (!atc_chan_is_enabled(atchan)) {
1047 atc_advance_work(atchan);
1049 spin_unlock_irqrestore(&atchan->lock, flags);
1053 * atc_alloc_chan_resources - allocate resources for DMA channel
1054 * @chan: allocate descriptor resources for this channel
1055 * @client: current client requesting the channel be ready for requests
1057 * return - the number of allocated descriptors
1059 static int atc_alloc_chan_resources(struct dma_chan *chan)
1061 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1062 struct at_dma *atdma = to_at_dma(chan->device);
1063 struct at_desc *desc;
1064 struct at_dma_slave *atslave;
1065 unsigned long flags;
1068 LIST_HEAD(tmp_list);
1070 dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
1072 /* ASSERT: channel is idle */
1073 if (atc_chan_is_enabled(atchan)) {
1074 dev_dbg(chan2dev(chan), "DMA channel not idle ?\n");
1078 cfg = ATC_DEFAULT_CFG;
1080 atslave = chan->private;
1083 * We need controller-specific data to set up slave
1086 BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev);
1088 /* if cfg configuration specified take it instad of default */
1093 /* have we already been set up?
1094 * reconfigure channel but no need to reallocate descriptors */
1095 if (!list_empty(&atchan->free_list))
1096 return atchan->descs_allocated;
1098 /* Allocate initial pool of descriptors */
1099 for (i = 0; i < init_nr_desc_per_channel; i++) {
1100 desc = atc_alloc_descriptor(chan, GFP_KERNEL);
1102 dev_err(atdma->dma_common.dev,
1103 "Only %d initial descriptors\n", i);
1106 list_add_tail(&desc->desc_node, &tmp_list);
1109 spin_lock_irqsave(&atchan->lock, flags);
1110 atchan->descs_allocated = i;
1111 list_splice(&tmp_list, &atchan->free_list);
1112 chan->completed_cookie = chan->cookie = 1;
1113 spin_unlock_irqrestore(&atchan->lock, flags);
1115 /* channel parameters */
1116 channel_writel(atchan, CFG, cfg);
1118 dev_dbg(chan2dev(chan),
1119 "alloc_chan_resources: allocated %d descriptors\n",
1120 atchan->descs_allocated);
1122 return atchan->descs_allocated;
1126 * atc_free_chan_resources - free all channel resources
1127 * @chan: DMA channel
1129 static void atc_free_chan_resources(struct dma_chan *chan)
1131 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1132 struct at_dma *atdma = to_at_dma(chan->device);
1133 struct at_desc *desc, *_desc;
1136 dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n",
1137 atchan->descs_allocated);
1139 /* ASSERT: channel is idle */
1140 BUG_ON(!list_empty(&atchan->active_list));
1141 BUG_ON(!list_empty(&atchan->queue));
1142 BUG_ON(atc_chan_is_enabled(atchan));
1144 list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
1145 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1146 list_del(&desc->desc_node);
1147 /* free link descriptor */
1148 dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys);
1150 list_splice_init(&atchan->free_list, &list);
1151 atchan->descs_allocated = 0;
1154 dev_vdbg(chan2dev(chan), "free_chan_resources: done\n");
1158 /*-- Module Management -----------------------------------------------*/
1160 /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */
1161 static struct at_dma_platform_data at91sam9rl_config = {
1164 static struct at_dma_platform_data at91sam9g45_config = {
1168 #if defined(CONFIG_OF)
1169 static const struct of_device_id atmel_dma_dt_ids[] = {
1171 .compatible = "atmel,at91sam9rl-dma",
1172 .data = &at91sam9rl_config,
1174 .compatible = "atmel,at91sam9g45-dma",
1175 .data = &at91sam9g45_config,
1181 MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids);
1184 static const struct platform_device_id atdma_devtypes[] = {
1186 .name = "at91sam9rl_dma",
1187 .driver_data = (unsigned long) &at91sam9rl_config,
1189 .name = "at91sam9g45_dma",
1190 .driver_data = (unsigned long) &at91sam9g45_config,
1196 static inline struct at_dma_platform_data * __init at_dma_get_driver_data(
1197 struct platform_device *pdev)
1199 if (pdev->dev.of_node) {
1200 const struct of_device_id *match;
1201 match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node);
1206 return (struct at_dma_platform_data *)
1207 platform_get_device_id(pdev)->driver_data;
1211 * at_dma_off - disable DMA controller
1212 * @atdma: the Atmel HDAMC device
1214 static void at_dma_off(struct at_dma *atdma)
1216 dma_writel(atdma, EN, 0);
1218 /* disable all interrupts */
1219 dma_writel(atdma, EBCIDR, -1L);
1221 /* confirm that all channels are disabled */
1222 while (dma_readl(atdma, CHSR) & atdma->all_chan_mask)
1226 static int __init at_dma_probe(struct platform_device *pdev)
1228 struct resource *io;
1229 struct at_dma *atdma;
1234 struct at_dma_platform_data *plat_dat;
1236 /* setup platform data for each SoC */
1237 dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask);
1238 dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask);
1239 dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask);
1241 /* get DMA parameters from controller type */
1242 plat_dat = at_dma_get_driver_data(pdev);
1246 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1250 irq = platform_get_irq(pdev, 0);
1254 size = sizeof(struct at_dma);
1255 size += plat_dat->nr_channels * sizeof(struct at_dma_chan);
1256 atdma = kzalloc(size, GFP_KERNEL);
1260 /* discover transaction capabilities */
1261 atdma->dma_common.cap_mask = plat_dat->cap_mask;
1262 atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1;
1264 size = resource_size(io);
1265 if (!request_mem_region(io->start, size, pdev->dev.driver->name)) {
1270 atdma->regs = ioremap(io->start, size);
1276 atdma->clk = clk_get(&pdev->dev, "dma_clk");
1277 if (IS_ERR(atdma->clk)) {
1278 err = PTR_ERR(atdma->clk);
1281 clk_enable(atdma->clk);
1283 /* force dma off, just in case */
1286 err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma);
1290 platform_set_drvdata(pdev, atdma);
1292 /* create a pool of consistent memory blocks for hardware descriptors */
1293 atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool",
1294 &pdev->dev, sizeof(struct at_desc),
1295 4 /* word alignment */, 0);
1296 if (!atdma->dma_desc_pool) {
1297 dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
1299 goto err_pool_create;
1302 /* clear any pending interrupt */
1303 while (dma_readl(atdma, EBCISR))
1306 /* initialize channels related values */
1307 INIT_LIST_HEAD(&atdma->dma_common.channels);
1308 for (i = 0; i < plat_dat->nr_channels; i++) {
1309 struct at_dma_chan *atchan = &atdma->chan[i];
1311 atchan->chan_common.device = &atdma->dma_common;
1312 atchan->chan_common.cookie = atchan->chan_common.completed_cookie = 1;
1313 list_add_tail(&atchan->chan_common.device_node,
1314 &atdma->dma_common.channels);
1316 atchan->ch_regs = atdma->regs + ch_regs(i);
1317 spin_lock_init(&atchan->lock);
1318 atchan->mask = 1 << i;
1320 INIT_LIST_HEAD(&atchan->active_list);
1321 INIT_LIST_HEAD(&atchan->queue);
1322 INIT_LIST_HEAD(&atchan->free_list);
1324 tasklet_init(&atchan->tasklet, atc_tasklet,
1325 (unsigned long)atchan);
1326 atc_enable_chan_irq(atdma, i);
1329 /* set base routines */
1330 atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources;
1331 atdma->dma_common.device_free_chan_resources = atc_free_chan_resources;
1332 atdma->dma_common.device_tx_status = atc_tx_status;
1333 atdma->dma_common.device_issue_pending = atc_issue_pending;
1334 atdma->dma_common.dev = &pdev->dev;
1336 /* set prep routines based on capability */
1337 if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask))
1338 atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy;
1340 if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) {
1341 atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg;
1342 /* controller can do slave DMA: can trigger cyclic transfers */
1343 dma_cap_set(DMA_CYCLIC, atdma->dma_common.cap_mask);
1344 atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic;
1345 atdma->dma_common.device_control = atc_control;
1348 dma_writel(atdma, EN, AT_DMA_ENABLE);
1350 dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n",
1351 dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "",
1352 dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "",
1353 plat_dat->nr_channels);
1355 dma_async_device_register(&atdma->dma_common);
1360 platform_set_drvdata(pdev, NULL);
1361 free_irq(platform_get_irq(pdev, 0), atdma);
1363 clk_disable(atdma->clk);
1364 clk_put(atdma->clk);
1366 iounmap(atdma->regs);
1369 release_mem_region(io->start, size);
1375 static int __exit at_dma_remove(struct platform_device *pdev)
1377 struct at_dma *atdma = platform_get_drvdata(pdev);
1378 struct dma_chan *chan, *_chan;
1379 struct resource *io;
1382 dma_async_device_unregister(&atdma->dma_common);
1384 dma_pool_destroy(atdma->dma_desc_pool);
1385 platform_set_drvdata(pdev, NULL);
1386 free_irq(platform_get_irq(pdev, 0), atdma);
1388 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
1390 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1392 /* Disable interrupts */
1393 atc_disable_chan_irq(atdma, chan->chan_id);
1394 tasklet_disable(&atchan->tasklet);
1396 tasklet_kill(&atchan->tasklet);
1397 list_del(&chan->device_node);
1400 clk_disable(atdma->clk);
1401 clk_put(atdma->clk);
1403 iounmap(atdma->regs);
1406 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1407 release_mem_region(io->start, resource_size(io));
1414 static void at_dma_shutdown(struct platform_device *pdev)
1416 struct at_dma *atdma = platform_get_drvdata(pdev);
1418 at_dma_off(platform_get_drvdata(pdev));
1419 clk_disable(atdma->clk);
1422 static int at_dma_prepare(struct device *dev)
1424 struct platform_device *pdev = to_platform_device(dev);
1425 struct at_dma *atdma = platform_get_drvdata(pdev);
1426 struct dma_chan *chan, *_chan;
1428 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
1430 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1431 /* wait for transaction completion (except in cyclic case) */
1432 if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan))
1438 static void atc_suspend_cyclic(struct at_dma_chan *atchan)
1440 struct dma_chan *chan = &atchan->chan_common;
1442 /* Channel should be paused by user
1443 * do it anyway even if it is not done already */
1444 if (!atc_chan_is_paused(atchan)) {
1445 dev_warn(chan2dev(chan),
1446 "cyclic channel not paused, should be done by channel user\n");
1447 atc_control(chan, DMA_PAUSE, 0);
1450 /* now preserve additional data for cyclic operations */
1451 /* next descriptor address in the cyclic list */
1452 atchan->save_dscr = channel_readl(atchan, DSCR);
1454 vdbg_dump_regs(atchan);
1457 static int at_dma_suspend_noirq(struct device *dev)
1459 struct platform_device *pdev = to_platform_device(dev);
1460 struct at_dma *atdma = platform_get_drvdata(pdev);
1461 struct dma_chan *chan, *_chan;
1464 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
1466 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1468 if (atc_chan_is_cyclic(atchan))
1469 atc_suspend_cyclic(atchan);
1470 atchan->save_cfg = channel_readl(atchan, CFG);
1472 atdma->save_imr = dma_readl(atdma, EBCIMR);
1474 /* disable DMA controller */
1476 clk_disable(atdma->clk);
1480 static void atc_resume_cyclic(struct at_dma_chan *atchan)
1482 struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
1484 /* restore channel status for cyclic descriptors list:
1485 * next descriptor in the cyclic list at the time of suspend */
1486 channel_writel(atchan, SADDR, 0);
1487 channel_writel(atchan, DADDR, 0);
1488 channel_writel(atchan, CTRLA, 0);
1489 channel_writel(atchan, CTRLB, 0);
1490 channel_writel(atchan, DSCR, atchan->save_dscr);
1491 dma_writel(atdma, CHER, atchan->mask);
1493 /* channel pause status should be removed by channel user
1494 * We cannot take the initiative to do it here */
1496 vdbg_dump_regs(atchan);
1499 static int at_dma_resume_noirq(struct device *dev)
1501 struct platform_device *pdev = to_platform_device(dev);
1502 struct at_dma *atdma = platform_get_drvdata(pdev);
1503 struct dma_chan *chan, *_chan;
1505 /* bring back DMA controller */
1506 clk_enable(atdma->clk);
1507 dma_writel(atdma, EN, AT_DMA_ENABLE);
1509 /* clear any pending interrupt */
1510 while (dma_readl(atdma, EBCISR))
1513 /* restore saved data */
1514 dma_writel(atdma, EBCIER, atdma->save_imr);
1515 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
1517 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1519 channel_writel(atchan, CFG, atchan->save_cfg);
1520 if (atc_chan_is_cyclic(atchan))
1521 atc_resume_cyclic(atchan);
1526 static const struct dev_pm_ops at_dma_dev_pm_ops = {
1527 .prepare = at_dma_prepare,
1528 .suspend_noirq = at_dma_suspend_noirq,
1529 .resume_noirq = at_dma_resume_noirq,
1532 static struct platform_driver at_dma_driver = {
1533 .remove = __exit_p(at_dma_remove),
1534 .shutdown = at_dma_shutdown,
1535 .id_table = atdma_devtypes,
1538 .pm = &at_dma_dev_pm_ops,
1539 .of_match_table = of_match_ptr(atmel_dma_dt_ids),
1543 static int __init at_dma_init(void)
1545 return platform_driver_probe(&at_dma_driver, at_dma_probe);
1547 subsys_initcall(at_dma_init);
1549 static void __exit at_dma_exit(void)
1551 platform_driver_unregister(&at_dma_driver);
1553 module_exit(at_dma_exit);
1555 MODULE_DESCRIPTION("Atmel AHB DMA Controller driver");
1556 MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
1557 MODULE_LICENSE("GPL");
1558 MODULE_ALIAS("platform:at_hdmac");