drivers/dma/amba-pl08x.c

   1 /*
   2  * Copyright (c) 2006 ARM Ltd.
   3  * Copyright (c) 2010 ST-Ericsson SA
   4  *
   5  * Author: Peter Pearse <peter.pearse@arm.com>
   6  * Author: Linus Walleij <linus.walleij@stericsson.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License as published by the Free
  10  * Software Foundation; either version 2 of the License, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program; if not, write to the Free Software Foundation, Inc., 59
  20  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  21  *
  22  * The full GNU General Public License is in this distribution in the
  23  * file called COPYING.
  24  *
  25  * Documentation: ARM DDI 0196G == PL080
  26  * Documentation: ARM DDI 0218E == PL081
  27  *
  28  * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
  29  * any channel.
  30  *
  31  * The PL080 has 8 channels available for simultaneous use, and the PL081
  32  * has only two channels. So on these DMA controllers the number of channels
  33  * and the number of incoming DMA signals are two totally different things.
  34  * It is usually not possible to theoretically handle all physical signals,
  35  * so a multiplexing scheme with possible denial of use is necessary.
  36  *
  37  * The PL080 has a dual bus master, PL081 has a single master.
  38  *
  39  * Memory to peripheral transfer may be visualized as
  40  *      Get data from memory to DMAC
  41  *      Until no data left
  42  *              On burst request from peripheral
  43  *                      Destination burst from DMAC to peripheral
  44  *                      Clear burst request
  45  *      Raise terminal count interrupt
  46  *
  47  * For peripherals with a FIFO:
  48  * Source      burst size == half the depth of the peripheral FIFO
  49  * Destination burst size == the depth of the peripheral FIFO
  50  *
  51  * (Bursts are irrelevant for mem to mem transfers - there are no burst
  52  * signals, the DMA controller will simply facilitate its AHB master.)
  53  *
  54  * ASSUMES default (little) endianness for DMA transfers
  55  *
  56  * The PL08x has two flow control settings:
  57  *  - DMAC flow control: the transfer size defines the number of transfers
  58  *    which occur for the current LLI entry, and the DMAC raises TC at the
  59  *    end of every LLI entry.  Observed behaviour shows the DMAC listening
  60  *    to both the BREQ and SREQ signals (contrary to documented),
  61  *    transferring data if either is active.  The LBREQ and LSREQ signals
  62  *    are ignored.
  63  *
  64  *  - Peripheral flow control: the transfer size is ignored (and should be
  65  *    zero).  The data is transferred from the current LLI entry, until
  66  *    after the final transfer signalled by LBREQ or LSREQ.  The DMAC
  67  *    will then move to the next LLI entry.
  68  *
  69  * Only the former works sanely with scatter lists, so we only implement
  70  * the DMAC flow control method.  However, peripherals which use the LBREQ
  71  * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
  72  * these hardware restrictions prevents them from using scatter DMA.
  73  *
  74  * Global TODO:
  75  * - Break out common code from arch/arm/mach-s3c64xx and share
  76  */
  77 #include <linux/device.h>
  78 #include <linux/init.h>
  79 #include <linux/module.h>
  80 #include <linux/interrupt.h>
  81 #include <linux/slab.h>
  82 #include <linux/dmapool.h>
  83 #include <linux/dmaengine.h>
  84 #include <linux/amba/bus.h>
  85 #include <linux/amba/pl08x.h>
  86 #include <linux/debugfs.h>
  87 #include <linux/seq_file.h>
  88
  89 #include <asm/hardware/pl080.h>
  90
  91 #define DRIVER_NAME     "pl08xdmac"
  92
  93 /**
  94  * struct vendor_data - vendor-specific config parameters
  95  * for PL08x derivatives
  96  * @channels: the number of channels available in this variant
  97  * @dualmaster: whether this version supports dual AHB masters
  98  * or not.
  99  */
 100 struct vendor_data {
 101         u8 channels;
 102         bool dualmaster;
 103 };
 104
 105 /*
 106  * PL08X private data structures
 107  * An LLI struct - see PL08x TRM.  Note that next uses bit[0] as a bus bit,
 108  * start & end do not - their bus bit info is in cctl.  Also note that these
 109  * are fixed 32-bit quantities.
 110  */
 111 struct pl08x_lli {
 112         u32 src;
 113         u32 dst;
 114         u32 lli;
 115         u32 cctl;
 116 };
 117
 118 /**
 119  * struct pl08x_driver_data - the local state holder for the PL08x
 120  * @slave: slave engine for this instance
 121  * @memcpy: memcpy engine for this instance
 122  * @base: virtual memory base (remapped) for the PL08x
 123  * @adev: the corresponding AMBA (PrimeCell) bus entry
 124  * @vd: vendor data for this PL08x variant
 125  * @pd: platform data passed in from the platform/machine
 126  * @phy_chans: array of data for the physical channels
 127  * @pool: a pool for the LLI descriptors
 128  * @pool_ctr: counter of LLIs in the pool
 129  * @lock: a spinlock for this struct
 130  */
 131 struct pl08x_driver_data {
 132         struct dma_device slave;
 133         struct dma_device memcpy;
 134         void __iomem *base;
 135         struct amba_device *adev;
 136         const struct vendor_data *vd;
 137         struct pl08x_platform_data *pd;
 138         struct pl08x_phy_chan *phy_chans;
 139         struct dma_pool *pool;
 140         int pool_ctr;
 141         spinlock_t lock;
 142 };
 143
 144 /*
 145  * PL08X specific defines
 146  */
 147
 148 /*
 149  * Memory boundaries: the manual for PL08x says that the controller
 150  * cannot read past a 1KiB boundary, so these defines are used to
 151  * create transfer LLIs that do not cross such boundaries.
 152  */
 153 #define PL08X_BOUNDARY_SHIFT            (10)    /* 1KB 0x400 */
 154 #define PL08X_BOUNDARY_SIZE             (1 << PL08X_BOUNDARY_SHIFT)
 155
 156 /* Minimum period between work queue runs */
 157 #define PL08X_WQ_PERIODMIN      20
 158
 159 /* Size (bytes) of each LLI buffer allocated for one transfer */
 160 # define PL08X_LLI_TSFR_SIZE    0x2000
 161
 162 /* Maximum times we call dma_pool_alloc on this pool without freeing */
 163 #define PL08X_MAX_ALLOCS        0x40
 164 #define MAX_NUM_TSFR_LLIS       (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
 165 #define PL08X_ALIGN             8
 166
 167 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
 168 {
 169         return container_of(chan, struct pl08x_dma_chan, chan);
 170 }
 171
 172 /*
 173  * Physical channel handling
 174  */
 175
 176 /* Whether a certain channel is busy or not */
 177 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
 178 {
 179         unsigned int val;
 180
 181         val = readl(ch->base + PL080_CH_CONFIG);
 182         return val & PL080_CONFIG_ACTIVE;
 183 }
 184
 185 /*
 186  * Set the initial DMA register values i.e. those for the first LLI
 187  * The next LLI pointer and the configuration interrupt bit have
 188  * been set when the LLIs were constructed
 189  */
 190 static void pl08x_set_cregs(struct pl08x_driver_data *pl08x,
 191                             struct pl08x_phy_chan *ch)
 192 {
 193         /* Wait for channel inactive */
 194         while (pl08x_phy_channel_busy(ch))
 195                 cpu_relax();
 196
 197         dev_vdbg(&pl08x->adev->dev,
 198                 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
 199                  "cctl=0x%08x, clli=0x%08x, ccfg=0x%08x\n",
 200                 ch->id,
 201                 ch->csrc,
 202                 ch->cdst,
 203                 ch->cctl,
 204                 ch->clli,
 205                 ch->ccfg);
 206
 207         writel(ch->csrc, ch->base + PL080_CH_SRC_ADDR);
 208         writel(ch->cdst, ch->base + PL080_CH_DST_ADDR);
 209         writel(ch->clli, ch->base + PL080_CH_LLI);
 210         writel(ch->cctl, ch->base + PL080_CH_CONTROL);
 211         writel(ch->ccfg, ch->base + PL080_CH_CONFIG);
 212 }
 213
 214 static inline void pl08x_config_phychan_for_txd(struct pl08x_dma_chan *plchan)
 215 {
 216         struct pl08x_channel_data *cd = plchan->cd;
 217         struct pl08x_phy_chan *phychan = plchan->phychan;
 218         struct pl08x_txd *txd = plchan->at;
 219
 220         /* Copy the basic control register calculated at transfer config */
 221         phychan->csrc = txd->csrc;
 222         phychan->cdst = txd->cdst;
 223         phychan->clli = txd->clli;
 224         phychan->cctl = txd->cctl;
 225
 226         /* Assign the signal to the proper control registers */
 227         phychan->ccfg = cd->ccfg;
 228         phychan->ccfg &= ~PL080_CONFIG_SRC_SEL_MASK;
 229         phychan->ccfg &= ~PL080_CONFIG_DST_SEL_MASK;
 230         /* If it wasn't set from AMBA, ignore it */
 231         if (txd->direction == DMA_TO_DEVICE)
 232                 /* Select signal as destination */
 233                 phychan->ccfg |=
 234                         (phychan->signal << PL080_CONFIG_DST_SEL_SHIFT);
 235         else if (txd->direction == DMA_FROM_DEVICE)
 236                 /* Select signal as source */
 237                 phychan->ccfg |=
 238                         (phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT);
 239         /* Always enable error interrupts */
 240         phychan->ccfg |= PL080_CONFIG_ERR_IRQ_MASK;
 241         /* Always enable terminal interrupts */
 242         phychan->ccfg |= PL080_CONFIG_TC_IRQ_MASK;
 243 }
 244
 245 /*
 246  * Enable the DMA channel
 247  * Assumes all other configuration bits have been set
 248  * as desired before this code is called
 249  */
 250 static void pl08x_enable_phy_chan(struct pl08x_driver_data *pl08x,
 251                                   struct pl08x_phy_chan *ch)
 252 {
 253         u32 val;
 254
 255         /*
 256          * Do not access config register until channel shows as disabled
 257          */
 258         while (readl(pl08x->base + PL080_EN_CHAN) & (1 << ch->id))
 259                 cpu_relax();
 260
 261         /*
 262          * Do not access config register until channel shows as inactive
 263          */
 264         val = readl(ch->base + PL080_CH_CONFIG);
 265         while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
 266                 val = readl(ch->base + PL080_CH_CONFIG);
 267
 268         writel(val | PL080_CONFIG_ENABLE, ch->base + PL080_CH_CONFIG);
 269 }
 270
 271 /*
 272  * Overall DMAC remains enabled always.
 273  *
 274  * Disabling individual channels could lose data.
 275  *
 276  * Disable the peripheral DMA after disabling the DMAC
 277  * in order to allow the DMAC FIFO to drain, and
 278  * hence allow the channel to show inactive
 279  *
 280  */
 281 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
 282 {
 283         u32 val;
 284
 285         /* Set the HALT bit and wait for the FIFO to drain */
 286         val = readl(ch->base + PL080_CH_CONFIG);
 287         val |= PL080_CONFIG_HALT;
 288         writel(val, ch->base + PL080_CH_CONFIG);
 289
 290         /* Wait for channel inactive */
 291         while (pl08x_phy_channel_busy(ch))
 292                 cpu_relax();
 293 }
 294
 295 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
 296 {
 297         u32 val;
 298
 299         /* Clear the HALT bit */
 300         val = readl(ch->base + PL080_CH_CONFIG);
 301         val &= ~PL080_CONFIG_HALT;
 302         writel(val, ch->base + PL080_CH_CONFIG);
 303 }
 304
 305
 306 /* Stops the channel */
 307 static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
 308 {
 309         u32 val;
 310
 311         pl08x_pause_phy_chan(ch);
 312
 313         /* Disable channel */
 314         val = readl(ch->base + PL080_CH_CONFIG);
 315         val &= ~PL080_CONFIG_ENABLE;
 316         val &= ~PL080_CONFIG_ERR_IRQ_MASK;
 317         val &= ~PL080_CONFIG_TC_IRQ_MASK;
 318         writel(val, ch->base + PL080_CH_CONFIG);
 319 }
 320
 321 static inline u32 get_bytes_in_cctl(u32 cctl)
 322 {
 323         /* The source width defines the number of bytes */
 324         u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
 325
 326         switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
 327         case PL080_WIDTH_8BIT:
 328                 break;
 329         case PL080_WIDTH_16BIT:
 330                 bytes *= 2;
 331                 break;
 332         case PL080_WIDTH_32BIT:
 333                 bytes *= 4;
 334                 break;
 335         }
 336         return bytes;
 337 }
 338
 339 /* The channel should be paused when calling this */
 340 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 341 {
 342         struct pl08x_phy_chan *ch;
 343         struct pl08x_txd *txdi = NULL;
 344         struct pl08x_txd *txd;
 345         unsigned long flags;
 346         size_t bytes = 0;
 347
 348         spin_lock_irqsave(&plchan->lock, flags);
 349
 350         ch = plchan->phychan;
 351         txd = plchan->at;
 352
 353         /*
 354          * Next follow the LLIs to get the number of pending bytes in the
 355          * currently active transaction.
 356          */
 357         if (ch && txd) {
 358                 struct pl08x_lli *llis_va = txd->llis_va;
 359                 struct pl08x_lli *llis_bus = (struct pl08x_lli *) txd->llis_bus;
 360                 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
 361
 362                 /* First get the bytes in the current active LLI */
 363                 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
 364
 365                 if (clli) {
 366                         int i = 0;
 367
 368                         /* Forward to the LLI pointed to by clli */
 369                         while ((clli != (u32) &(llis_bus[i])) &&
 370                                (i < MAX_NUM_TSFR_LLIS))
 371                                 i++;
 372
 373                         while (clli) {
 374                                 bytes += get_bytes_in_cctl(llis_va[i].cctl);
 375                                 /*
 376                                  * A LLI pointer of 0 terminates the LLI list
 377                                  */
 378                                 clli = llis_va[i].lli;
 379                                 i++;
 380                         }
 381                 }
 382         }
 383
 384         /* Sum up all queued transactions */
 385         if (!list_empty(&plchan->desc_list)) {
 386                 list_for_each_entry(txdi, &plchan->desc_list, node) {
 387                         bytes += txdi->len;
 388                 }
 389
 390         }
 391
 392         spin_unlock_irqrestore(&plchan->lock, flags);
 393
 394         return bytes;
 395 }
 396
 397 /*
 398  * Allocate a physical channel for a virtual channel
 399  */
 400 static struct pl08x_phy_chan *
 401 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
 402                       struct pl08x_dma_chan *virt_chan)
 403 {
 404         struct pl08x_phy_chan *ch = NULL;
 405         unsigned long flags;
 406         int i;
 407
 408         /*
 409          * Try to locate a physical channel to be used for
 410          * this transfer. If all are taken return NULL and
 411          * the requester will have to cope by using some fallback
 412          * PIO mode or retrying later.
 413          */
 414         for (i = 0; i < pl08x->vd->channels; i++) {
 415                 ch = &pl08x->phy_chans[i];
 416
 417                 spin_lock_irqsave(&ch->lock, flags);
 418
 419                 if (!ch->serving) {
 420                         ch->serving = virt_chan;
 421                         ch->signal = -1;
 422                         spin_unlock_irqrestore(&ch->lock, flags);
 423                         break;
 424                 }
 425
 426                 spin_unlock_irqrestore(&ch->lock, flags);
 427         }
 428
 429         if (i == pl08x->vd->channels) {
 430                 /* No physical channel available, cope with it */
 431                 return NULL;
 432         }
 433
 434         return ch;
 435 }
 436
 437 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
 438                                          struct pl08x_phy_chan *ch)
 439 {
 440         unsigned long flags;
 441
 442         /* Stop the channel and clear its interrupts */
 443         pl08x_stop_phy_chan(ch);
 444         writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
 445         writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
 446
 447         /* Mark it as free */
 448         spin_lock_irqsave(&ch->lock, flags);
 449         ch->serving = NULL;
 450         spin_unlock_irqrestore(&ch->lock, flags);
 451 }
 452
 453 /*
 454  * LLI handling
 455  */
 456
 457 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
 458 {
 459         switch (coded) {
 460         case PL080_WIDTH_8BIT:
 461                 return 1;
 462         case PL080_WIDTH_16BIT:
 463                 return 2;
 464         case PL080_WIDTH_32BIT:
 465                 return 4;
 466         default:
 467                 break;
 468         }
 469         BUG();
 470         return 0;
 471 }
 472
 473 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
 474                                   size_t tsize)
 475 {
 476         u32 retbits = cctl;
 477
 478         /* Remove all src, dst and transfer size bits */
 479         retbits &= ~PL080_CONTROL_DWIDTH_MASK;
 480         retbits &= ~PL080_CONTROL_SWIDTH_MASK;
 481         retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
 482
 483         /* Then set the bits according to the parameters */
 484         switch (srcwidth) {
 485         case 1:
 486                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
 487                 break;
 488         case 2:
 489                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
 490                 break;
 491         case 4:
 492                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
 493                 break;
 494         default:
 495                 BUG();
 496                 break;
 497         }
 498
 499         switch (dstwidth) {
 500         case 1:
 501                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
 502                 break;
 503         case 2:
 504                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
 505                 break;
 506         case 4:
 507                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
 508                 break;
 509         default:
 510                 BUG();
 511                 break;
 512         }
 513
 514         retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
 515         return retbits;
 516 }
 517
 518 /*
 519  * Autoselect a master bus to use for the transfer
 520  * this prefers the destination bus if both available
 521  * if fixed address on one bus the other will be chosen
 522  */
 523 static void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
 524         struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
 525         struct pl08x_bus_data **sbus, u32 cctl)
 526 {
 527         if (!(cctl & PL080_CONTROL_DST_INCR)) {
 528                 *mbus = src_bus;
 529                 *sbus = dst_bus;
 530         } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
 531                 *mbus = dst_bus;
 532                 *sbus = src_bus;
 533         } else {
 534                 if (dst_bus->buswidth == 4) {
 535                         *mbus = dst_bus;
 536                         *sbus = src_bus;
 537                 } else if (src_bus->buswidth == 4) {
 538                         *mbus = src_bus;
 539                         *sbus = dst_bus;
 540                 } else if (dst_bus->buswidth == 2) {
 541                         *mbus = dst_bus;
 542                         *sbus = src_bus;
 543                 } else if (src_bus->buswidth == 2) {
 544                         *mbus = src_bus;
 545                         *sbus = dst_bus;
 546                 } else {
 547                         /* src_bus->buswidth == 1 */
 548                         *mbus = dst_bus;
 549                         *sbus = src_bus;
 550                 }
 551         }
 552 }
 553
 554 /*
 555  * Fills in one LLI for a certain transfer descriptor
 556  * and advance the counter
 557  */
 558 static int pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
 559                             struct pl08x_txd *txd, int num_llis, int len,
 560                             u32 cctl, u32 *remainder)
 561 {
 562         struct pl08x_lli *llis_va = txd->llis_va;
 563         dma_addr_t llis_bus = txd->llis_bus;
 564
 565         BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
 566
 567         llis_va[num_llis].cctl          = cctl;
 568         llis_va[num_llis].src           = txd->srcbus.addr;
 569         llis_va[num_llis].dst           = txd->dstbus.addr;
 570
 571         /*
 572          * On versions with dual masters, you can optionally AND on
 573          * PL080_LLI_LM_AHB2 to the LLI to tell the hardware to read
 574          * in new LLIs with that controller, but we always try to
 575          * choose AHB1 to point into memory. The idea is to have AHB2
 576          * fixed on the peripheral and AHB1 messing around in the
 577          * memory. So we don't manipulate this bit currently.
 578          */
 579
 580         llis_va[num_llis].lli = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli);
 581
 582         if (cctl & PL080_CONTROL_SRC_INCR)
 583                 txd->srcbus.addr += len;
 584         if (cctl & PL080_CONTROL_DST_INCR)
 585                 txd->dstbus.addr += len;
 586
 587         BUG_ON(*remainder < len);
 588
 589         *remainder -= len;
 590
 591         return num_llis + 1;
 592 }
 593
 594 /*
 595  * Return number of bytes to fill to boundary, or len
 596  */
 597 static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
 598 {
 599         u32 boundary;
 600
 601         boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1)
 602                 << PL08X_BOUNDARY_SHIFT;
 603
 604         if (boundary < addr + len)
 605                 return boundary - addr;
 606         else
 607                 return len;
 608 }
 609
 610 /*
 611  * This fills in the table of LLIs for the transfer descriptor
 612  * Note that we assume we never have to change the burst sizes
 613  * Return 0 for error
 614  */
 615 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 616                               struct pl08x_txd *txd)
 617 {
 618         struct pl08x_channel_data *cd = txd->cd;
 619         struct pl08x_bus_data *mbus, *sbus;
 620         size_t remainder;
 621         int num_llis = 0;
 622         u32 cctl;
 623         size_t max_bytes_per_lli;
 624         size_t total_bytes = 0;
 625         struct pl08x_lli *llis_va;
 626
 627         txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
 628                                       &txd->llis_bus);
 629         if (!txd->llis_va) {
 630                 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
 631                 return 0;
 632         }
 633
 634         pl08x->pool_ctr++;
 635
 636         /*
 637          * Initialize bus values for this transfer
 638          * from the passed optimal values
 639          */
 640         if (!cd) {
 641                 dev_err(&pl08x->adev->dev, "%s no channel data\n", __func__);
 642                 return 0;
 643         }
 644
 645         /* Get the default CCTL from the platform data */
 646         cctl = cd->cctl;
 647
 648         /*
 649          * On the PL080 we have two bus masters and we
 650          * should select one for source and one for
 651          * destination. We try to use AHB2 for the
 652          * bus which does not increment (typically the
 653          * peripheral) else we just choose something.
 654          */
 655         cctl &= ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
 656         if (pl08x->vd->dualmaster) {
 657                 if (cctl & PL080_CONTROL_SRC_INCR)
 658                         /* Source increments, use AHB2 for destination */
 659                         cctl |= PL080_CONTROL_DST_AHB2;
 660                 else if (cctl & PL080_CONTROL_DST_INCR)
 661                         /* Destination increments, use AHB2 for source */
 662                         cctl |= PL080_CONTROL_SRC_AHB2;
 663                 else
 664                         /* Just pick something, source AHB1 dest AHB2 */
 665                         cctl |= PL080_CONTROL_DST_AHB2;
 666         }
 667
 668         /* Find maximum width of the source bus */
 669         txd->srcbus.maxwidth =
 670                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
 671                                        PL080_CONTROL_SWIDTH_SHIFT);
 672
 673         /* Find maximum width of the destination bus */
 674         txd->dstbus.maxwidth =
 675                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
 676                                        PL080_CONTROL_DWIDTH_SHIFT);
 677
 678         /* Set up the bus widths to the maximum */
 679         txd->srcbus.buswidth = txd->srcbus.maxwidth;
 680         txd->dstbus.buswidth = txd->dstbus.maxwidth;
 681         dev_vdbg(&pl08x->adev->dev,
 682                  "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
 683                  __func__, txd->srcbus.buswidth, txd->dstbus.buswidth);
 684
 685
 686         /*
 687          * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
 688          */
 689         max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) *
 690                 PL080_CONTROL_TRANSFER_SIZE_MASK;
 691         dev_vdbg(&pl08x->adev->dev,
 692                  "%s max bytes per lli = %zu\n",
 693                  __func__, max_bytes_per_lli);
 694
 695         /* We need to count this down to zero */
 696         remainder = txd->len;
 697         dev_vdbg(&pl08x->adev->dev,
 698                  "%s remainder = %zu\n",
 699                  __func__, remainder);
 700
 701         /*
 702          * Choose bus to align to
 703          * - prefers destination bus if both available
 704          * - if fixed address on one bus chooses other
 705          * - modifies cctl to choose an appropriate master
 706          */
 707         pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus,
 708                                 &mbus, &sbus, cctl);
 709
 710
 711         /*
 712          * The lowest bit of the LLI register
 713          * is also used to indicate which master to
 714          * use for reading the LLIs.
 715          */
 716
 717         if (txd->len < mbus->buswidth) {
 718                 /*
 719                  * Less than a bus width available
 720                  * - send as single bytes
 721                  */
 722                 while (remainder) {
 723                         dev_vdbg(&pl08x->adev->dev,
 724                                  "%s single byte LLIs for a transfer of "
 725                                  "less than a bus width (remain 0x%08x)\n",
 726                                  __func__, remainder);
 727                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 728                         num_llis =
 729                                 pl08x_fill_lli_for_desc(pl08x, txd, num_llis, 1,
 730                                         cctl, &remainder);
 731                         total_bytes++;
 732                 }
 733         } else {
 734                 /*
 735                  *  Make one byte LLIs until master bus is aligned
 736                  *  - slave will then be aligned also
 737                  */
 738                 while ((mbus->addr) % (mbus->buswidth)) {
 739                         dev_vdbg(&pl08x->adev->dev,
 740                                 "%s adjustment lli for less than bus width "
 741                                  "(remain 0x%08x)\n",
 742                                  __func__, remainder);
 743                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 744                         num_llis = pl08x_fill_lli_for_desc
 745                                 (pl08x, txd, num_llis, 1, cctl, &remainder);
 746                         total_bytes++;
 747                 }
 748
 749                 /*
 750                  *  Master now aligned
 751                  * - if slave is not then we must set its width down
 752                  */
 753                 if (sbus->addr % sbus->buswidth) {
 754                         dev_dbg(&pl08x->adev->dev,
 755                                 "%s set down bus width to one byte\n",
 756                                  __func__);
 757
 758                         sbus->buswidth = 1;
 759                 }
 760
 761                 /*
 762                  * Make largest possible LLIs until less than one bus
 763                  * width left
 764                  */
 765                 while (remainder > (mbus->buswidth - 1)) {
 766                         size_t lli_len, target_len, tsize, odd_bytes;
 767
 768                         /*
 769                          * If enough left try to send max possible,
 770                          * otherwise try to send the remainder
 771                          */
 772                         target_len = remainder;
 773                         if (remainder > max_bytes_per_lli)
 774                                 target_len = max_bytes_per_lli;
 775
 776                         /*
 777                          * Set bus lengths for incrementing buses
 778                          * to number of bytes which fill to next memory
 779                          * boundary
 780                          */
 781                         if (cctl & PL080_CONTROL_SRC_INCR)
 782                                 txd->srcbus.fill_bytes =
 783                                         pl08x_pre_boundary(
 784                                                 txd->srcbus.addr,
 785                                                 remainder);
 786                         else
 787                                 txd->srcbus.fill_bytes =
 788                                         max_bytes_per_lli;
 789
 790                         if (cctl & PL080_CONTROL_DST_INCR)
 791                                 txd->dstbus.fill_bytes =
 792                                         pl08x_pre_boundary(
 793                                                 txd->dstbus.addr,
 794                                                 remainder);
 795                         else
 796                                 txd->dstbus.fill_bytes =
 797                                                 max_bytes_per_lli;
 798
 799                         /*
 800                          *  Find the nearest
 801                          */
 802                         lli_len = min(txd->srcbus.fill_bytes,
 803                                 txd->dstbus.fill_bytes);
 804
 805                         BUG_ON(lli_len > remainder);
 806
 807                         if (lli_len <= 0) {
 808                                 dev_err(&pl08x->adev->dev,
 809                                         "%s lli_len is %zu, <= 0\n",
 810                                                 __func__, lli_len);
 811                                 return 0;
 812                         }
 813
 814                         if (lli_len == target_len) {
 815                                 /*
 816                                  * Can send what we wanted
 817                                  */
 818                                 /*
 819                                  *  Maintain alignment
 820                                  */
 821                                 lli_len = (lli_len/mbus->buswidth) *
 822                                                         mbus->buswidth;
 823                                 odd_bytes = 0;
 824                         } else {
 825                                 /*
 826                                  * So now we know how many bytes to transfer
 827                                  * to get to the nearest boundary
 828                                  * The next LLI will past the boundary
 829                                  * - however we may be working to a boundary
 830                                  *   on the slave bus
 831                                  *   We need to ensure the master stays aligned
 832                                  */
 833                                 odd_bytes = lli_len % mbus->buswidth;
 834                                 /*
 835                                  * - and that we are working in multiples
 836                                  *   of the bus widths
 837                                  */
 838                                 lli_len -= odd_bytes;
 839
 840                         }
 841
 842                         if (lli_len) {
 843                                 /*
 844                                  * Check against minimum bus alignment:
 845                                  * Calculate actual transfer size in relation
 846                                  * to bus width an get a maximum remainder of
 847                                  * the smallest bus width - 1
 848                                  */
 849                                 /* FIXME: use round_down()? */
 850                                 tsize = lli_len / min(mbus->buswidth,
 851                                                       sbus->buswidth);
 852                                 lli_len = tsize * min(mbus->buswidth,
 853                                                       sbus->buswidth);
 854
 855                                 if (target_len != lli_len) {
 856                                         dev_vdbg(&pl08x->adev->dev,
 857                                         "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
 858                                         __func__, target_len, lli_len, txd->len);
 859                                 }
 860
 861                                 cctl = pl08x_cctl_bits(cctl,
 862                                                        txd->srcbus.buswidth,
 863                                                        txd->dstbus.buswidth,
 864                                                        tsize);
 865
 866                                 dev_vdbg(&pl08x->adev->dev,
 867                                         "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
 868                                         __func__, lli_len, remainder);
 869                                 num_llis = pl08x_fill_lli_for_desc(pl08x, txd,
 870                                                 num_llis, lli_len, cctl,
 871                                                 &remainder);
 872                                 total_bytes += lli_len;
 873                         }
 874
 875
 876                         if (odd_bytes) {
 877                                 /*
 878                                  * Creep past the boundary,
 879                                  * maintaining master alignment
 880                                  */
 881                                 int j;
 882                                 for (j = 0; (j < mbus->buswidth)
 883                                                 && (remainder); j++) {
 884                                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 885                                         dev_vdbg(&pl08x->adev->dev,
 886                                                 "%s align with boundary, single byte (remain 0x%08zx)\n",
 887                                                 __func__, remainder);
 888                                         num_llis =
 889                                                 pl08x_fill_lli_for_desc(pl08x,
 890                                                         txd, num_llis, 1,
 891                                                         cctl, &remainder);
 892                                         total_bytes++;
 893                                 }
 894                         }
 895                 }
 896
 897                 /*
 898                  * Send any odd bytes
 899                  */
 900                 while (remainder) {
 901                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 902                         dev_vdbg(&pl08x->adev->dev,
 903                                 "%s align with boundary, single odd byte (remain %zu)\n",
 904                                 __func__, remainder);
 905                         num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis,
 906                                         1, cctl, &remainder);
 907                         total_bytes++;
 908                 }
 909         }
 910         if (total_bytes != txd->len) {
 911                 dev_err(&pl08x->adev->dev,
 912                         "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
 913                         __func__, total_bytes, txd->len);
 914                 return 0;
 915         }
 916
 917         if (num_llis >= MAX_NUM_TSFR_LLIS) {
 918                 dev_err(&pl08x->adev->dev,
 919                         "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
 920                         __func__, (u32) MAX_NUM_TSFR_LLIS);
 921                 return 0;
 922         }
 923
 924         llis_va = txd->llis_va;
 925         /*
 926          * The final LLI terminates the LLI.
 927          */
 928         llis_va[num_llis - 1].lli = 0;
 929         /*
 930          * The final LLI element shall also fire an interrupt
 931          */
 932         llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
 933
 934         /* Now store the channel register values */
 935         txd->csrc = llis_va[0].src;
 936         txd->cdst = llis_va[0].dst;
 937         txd->clli = llis_va[0].lli;
 938         txd->cctl = llis_va[0].cctl;
 939         /* ccfg will be set at physical channel allocation time */
 940
 941 #ifdef VERBOSE_DEBUG
 942         {
 943                 int i;
 944
 945                 for (i = 0; i < num_llis; i++) {
 946                         dev_vdbg(&pl08x->adev->dev,
 947                                  "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
 948                                  i,
 949                                  &llis_va[i],
 950                                  llis_va[i].src,
 951                                  llis_va[i].dst,
 952                                  llis_va[i].cctl,
 953                                  llis_va[i].lli
 954                                 );
 955                 }
 956         }
 957 #endif
 958
 959         return num_llis;
 960 }
 961
 962 /* You should call this with the struct pl08x lock held */
 963 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
 964                            struct pl08x_txd *txd)
 965 {
 966         /* Free the LLI */
 967         dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
 968
 969         pl08x->pool_ctr--;
 970
 971         kfree(txd);
 972 }
 973
 974 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
 975                                 struct pl08x_dma_chan *plchan)
 976 {
 977         struct pl08x_txd *txdi = NULL;
 978         struct pl08x_txd *next;
 979
 980         if (!list_empty(&plchan->desc_list)) {
 981                 list_for_each_entry_safe(txdi,
 982                                          next, &plchan->desc_list, node) {
 983                         list_del(&txdi->node);
 984                         pl08x_free_txd(pl08x, txdi);
 985                 }
 986
 987         }
 988 }
 989
 990 /*
 991  * The DMA ENGINE API
 992  */
 993 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
 994 {
 995         return 0;
 996 }
 997
 998 static void pl08x_free_chan_resources(struct dma_chan *chan)
 999 {
1000 }
1001
1002 /*
1003  * This should be called with the channel plchan->lock held
1004  */
1005 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
1006                             struct pl08x_txd *txd)
1007 {
1008         struct pl08x_driver_data *pl08x = plchan->host;
1009         struct pl08x_phy_chan *ch;
1010         int ret;
1011
1012         /* Check if we already have a channel */
1013         if (plchan->phychan)
1014                 return 0;
1015
1016         ch = pl08x_get_phy_channel(pl08x, plchan);
1017         if (!ch) {
1018                 /* No physical channel available, cope with it */
1019                 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
1020                 return -EBUSY;
1021         }
1022
1023         /*
1024          * OK we have a physical channel: for memcpy() this is all we
1025          * need, but for slaves the physical signals may be muxed!
1026          * Can the platform allow us to use this channel?
1027          */
1028         if (plchan->slave &&
1029             ch->signal < 0 &&
1030             pl08x->pd->get_signal) {
1031                 ret = pl08x->pd->get_signal(plchan);
1032                 if (ret < 0) {
1033                         dev_dbg(&pl08x->adev->dev,
1034                                 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
1035                                 ch->id, plchan->name);
1036                         /* Release physical channel & return */
1037                         pl08x_put_phy_channel(pl08x, ch);
1038                         return -EBUSY;
1039                 }
1040                 ch->signal = ret;
1041         }
1042
1043         dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
1044                  ch->id,
1045                  ch->signal,
1046                  plchan->name);
1047
1048         plchan->phychan = ch;
1049
1050         return 0;
1051 }
1052
1053 static void release_phy_channel(struct pl08x_dma_chan *plchan)
1054 {
1055         struct pl08x_driver_data *pl08x = plchan->host;
1056
1057         if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
1058                 pl08x->pd->put_signal(plchan);
1059                 plchan->phychan->signal = -1;
1060         }
1061         pl08x_put_phy_channel(pl08x, plchan->phychan);
1062         plchan->phychan = NULL;
1063 }
1064
1065 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
1066 {
1067         struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
1068
1069         plchan->chan.cookie += 1;
1070         if (plchan->chan.cookie < 0)
1071                 plchan->chan.cookie = 1;
1072         tx->cookie = plchan->chan.cookie;
1073         /* This unlock follows the lock in the prep() function */
1074         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1075
1076         return tx->cookie;
1077 }
1078
1079 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1080                 struct dma_chan *chan, unsigned long flags)
1081 {
1082         struct dma_async_tx_descriptor *retval = NULL;
1083
1084         return retval;
1085 }
1086
1087 /*
1088  * Code accessing dma_async_is_complete() in a tight loop
1089  * may give problems - could schedule where indicated.
1090  * If slaves are relying on interrupts to signal completion this
1091  * function must not be called with interrupts disabled
1092  */
1093 static enum dma_status
1094 pl08x_dma_tx_status(struct dma_chan *chan,
1095                     dma_cookie_t cookie,
1096                     struct dma_tx_state *txstate)
1097 {
1098         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1099         dma_cookie_t last_used;
1100         dma_cookie_t last_complete;
1101         enum dma_status ret;
1102         u32 bytesleft = 0;
1103
1104         last_used = plchan->chan.cookie;
1105         last_complete = plchan->lc;
1106
1107         ret = dma_async_is_complete(cookie, last_complete, last_used);
1108         if (ret == DMA_SUCCESS) {
1109                 dma_set_tx_state(txstate, last_complete, last_used, 0);
1110                 return ret;
1111         }
1112
1113         /*
1114          * schedule(); could be inserted here
1115          */
1116
1117         /*
1118          * This cookie not complete yet
1119          */
1120         last_used = plchan->chan.cookie;
1121         last_complete = plchan->lc;
1122
1123         /* Get number of bytes left in the active transactions and queue */
1124         bytesleft = pl08x_getbytes_chan(plchan);
1125
1126         dma_set_tx_state(txstate, last_complete, last_used,
1127                          bytesleft);
1128
1129         if (plchan->state == PL08X_CHAN_PAUSED)
1130                 return DMA_PAUSED;
1131
1132         /* Whether waiting or running, we're in progress */
1133         return DMA_IN_PROGRESS;
1134 }
1135
1136 /* PrimeCell DMA extension */
1137 struct burst_table {
1138         int burstwords;
1139         u32 reg;
1140 };
1141
1142 static const struct burst_table burst_sizes[] = {
1143         {
1144                 .burstwords = 256,
1145                 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1146                         (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1147         },
1148         {
1149                 .burstwords = 128,
1150                 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1151                         (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1152         },
1153         {
1154                 .burstwords = 64,
1155                 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1156                         (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1157         },
1158         {
1159                 .burstwords = 32,
1160                 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1161                         (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1162         },
1163         {
1164                 .burstwords = 16,
1165                 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1166                         (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1167         },
1168         {
1169                 .burstwords = 8,
1170                 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1171                         (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1172         },
1173         {
1174                 .burstwords = 4,
1175                 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1176                         (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1177         },
1178         {
1179                 .burstwords = 1,
1180                 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1181                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1182         },
1183 };
1184
1185 static void dma_set_runtime_config(struct dma_chan *chan,
1186                                struct dma_slave_config *config)
1187 {
1188         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1189         struct pl08x_driver_data *pl08x = plchan->host;
1190         struct pl08x_channel_data *cd = plchan->cd;
1191         enum dma_slave_buswidth addr_width;
1192         u32 maxburst;
1193         u32 cctl = 0;
1194         /* Mask out all except src and dst channel */
1195         u32 ccfg = cd->ccfg & 0x000003DEU;
1196         int i;
1197
1198         /* Transfer direction */
1199         plchan->runtime_direction = config->direction;
1200         if (config->direction == DMA_TO_DEVICE) {
1201                 plchan->runtime_addr = config->dst_addr;
1202                 cctl |= PL080_CONTROL_SRC_INCR;
1203                 ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1204                 addr_width = config->dst_addr_width;
1205                 maxburst = config->dst_maxburst;
1206         } else if (config->direction == DMA_FROM_DEVICE) {
1207                 plchan->runtime_addr = config->src_addr;
1208                 cctl |= PL080_CONTROL_DST_INCR;
1209                 ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1210                 addr_width = config->src_addr_width;
1211                 maxburst = config->src_maxburst;
1212         } else {
1213                 dev_err(&pl08x->adev->dev,
1214                         "bad runtime_config: alien transfer direction\n");
1215                 return;
1216         }
1217
1218         switch (addr_width) {
1219         case DMA_SLAVE_BUSWIDTH_1_BYTE:
1220                 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1221                         (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1222                 break;
1223         case DMA_SLAVE_BUSWIDTH_2_BYTES:
1224                 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1225                         (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1226                 break;
1227         case DMA_SLAVE_BUSWIDTH_4_BYTES:
1228                 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1229                         (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1230                 break;
1231         default:
1232                 dev_err(&pl08x->adev->dev,
1233                         "bad runtime_config: alien address width\n");
1234                 return;
1235         }
1236
1237         /*
1238          * Now decide on a maxburst:
1239          * If this channel will only request single transfers, set this
1240          * down to ONE element.  Also select one element if no maxburst
1241          * is specified.
1242          */
1243         if (plchan->cd->single || maxburst == 0) {
1244                 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1245                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1246         } else {
1247                 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1248                         if (burst_sizes[i].burstwords <= maxburst)
1249                                 break;
1250                 cctl |= burst_sizes[i].reg;
1251         }
1252
1253         /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1254         cctl &= ~PL080_CONTROL_PROT_MASK;
1255         cctl |= PL080_CONTROL_PROT_SYS;
1256
1257         /* Modify the default channel data to fit PrimeCell request */
1258         cd->cctl = cctl;
1259         cd->ccfg = ccfg;
1260
1261         dev_dbg(&pl08x->adev->dev,
1262                 "configured channel %s (%s) for %s, data width %d, "
1263                 "maxburst %d words, LE, CCTL=0x%08x, CCFG=0x%08x\n",
1264                 dma_chan_name(chan), plchan->name,
1265                 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1266                 addr_width,
1267                 maxburst,
1268                 cctl, ccfg);
1269 }
1270
1271 /*
1272  * Slave transactions callback to the slave device to allow
1273  * synchronization of slave DMA signals with the DMAC enable
1274  */
1275 static void pl08x_issue_pending(struct dma_chan *chan)
1276 {
1277         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1278         struct pl08x_driver_data *pl08x = plchan->host;
1279         unsigned long flags;
1280
1281         spin_lock_irqsave(&plchan->lock, flags);
1282         /* Something is already active, or we're waiting for a channel... */
1283         if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1284                 spin_unlock_irqrestore(&plchan->lock, flags);
1285                 return;
1286         }
1287
1288         /* Take the first element in the queue and execute it */
1289         if (!list_empty(&plchan->desc_list)) {
1290                 struct pl08x_txd *next;
1291
1292                 next = list_first_entry(&plchan->desc_list,
1293                                         struct pl08x_txd,
1294                                         node);
1295                 list_del(&next->node);
1296                 plchan->at = next;
1297                 plchan->state = PL08X_CHAN_RUNNING;
1298
1299                 /* Configure the physical channel for the active txd */
1300                 pl08x_config_phychan_for_txd(plchan);
1301                 pl08x_set_cregs(pl08x, plchan->phychan);
1302                 pl08x_enable_phy_chan(pl08x, plchan->phychan);
1303         }
1304
1305         spin_unlock_irqrestore(&plchan->lock, flags);
1306 }
1307
1308 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1309                                         struct pl08x_txd *txd)
1310 {
1311         int num_llis;
1312         struct pl08x_driver_data *pl08x = plchan->host;
1313         int ret;
1314
1315         num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1316         if (!num_llis) {
1317                 kfree(txd);
1318                 return -EINVAL;
1319         }
1320
1321         spin_lock_irqsave(&plchan->lock, plchan->lockflags);
1322
1323         list_add_tail(&txd->node, &plchan->desc_list);
1324
1325         /*
1326          * See if we already have a physical channel allocated,
1327          * else this is the time to try to get one.
1328          */
1329         ret = prep_phy_channel(plchan, txd);
1330         if (ret) {
1331                 /*
1332                  * No physical channel available, we will
1333                  * stack up the memcpy channels until there is a channel
1334                  * available to handle it whereas slave transfers may
1335                  * have been denied due to platform channel muxing restrictions
1336                  * and since there is no guarantee that this will ever be
1337                  * resolved, and since the signal must be acquired AFTER
1338                  * acquiring the physical channel, we will let them be NACK:ed
1339                  * with -EBUSY here. The drivers can alway retry the prep()
1340                  * call if they are eager on doing this using DMA.
1341                  */
1342                 if (plchan->slave) {
1343                         pl08x_free_txd_list(pl08x, plchan);
1344                         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1345                         return -EBUSY;
1346                 }
1347                 /* Do this memcpy whenever there is a channel ready */
1348                 plchan->state = PL08X_CHAN_WAITING;
1349                 plchan->waiting = txd;
1350         } else
1351                 /*
1352                  * Else we're all set, paused and ready to roll,
1353                  * status will switch to PL08X_CHAN_RUNNING when
1354                  * we call issue_pending(). If there is something
1355                  * running on the channel already we don't change
1356                  * its state.
1357                  */
1358                 if (plchan->state == PL08X_CHAN_IDLE)
1359                         plchan->state = PL08X_CHAN_PAUSED;
1360
1361         /*
1362          * Notice that we leave plchan->lock locked on purpose:
1363          * it will be unlocked in the subsequent tx_submit()
1364          * call. This is a consequence of the current API.
1365          */
1366
1367         return 0;
1368 }
1369
1370 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan)
1371 {
1372         struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1373
1374         if (txd) {
1375                 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1376                 txd->tx.tx_submit = pl08x_tx_submit;
1377                 INIT_LIST_HEAD(&txd->node);
1378         }
1379         return txd;
1380 }
1381
1382 /*
1383  * Initialize a descriptor to be used by memcpy submit
1384  */
1385 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1386                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1387                 size_t len, unsigned long flags)
1388 {
1389         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1390         struct pl08x_driver_data *pl08x = plchan->host;
1391         struct pl08x_txd *txd;
1392         int ret;
1393
1394         txd = pl08x_get_txd(plchan);
1395         if (!txd) {
1396                 dev_err(&pl08x->adev->dev,
1397                         "%s no memory for descriptor\n", __func__);
1398                 return NULL;
1399         }
1400
1401         txd->direction = DMA_NONE;
1402         txd->srcbus.addr = src;
1403         txd->dstbus.addr = dest;
1404
1405         /* Set platform data for m2m */
1406         txd->cd = &pl08x->pd->memcpy_channel;
1407         /* Both to be incremented or the code will break */
1408         txd->cd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1409         txd->len = len;
1410
1411         ret = pl08x_prep_channel_resources(plchan, txd);
1412         if (ret)
1413                 return NULL;
1414         /*
1415          * NB: the channel lock is held at this point so tx_submit()
1416          * must be called in direct succession.
1417          */
1418
1419         return &txd->tx;
1420 }
1421
1422 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1423                 struct dma_chan *chan, struct scatterlist *sgl,
1424                 unsigned int sg_len, enum dma_data_direction direction,
1425                 unsigned long flags)
1426 {
1427         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1428         struct pl08x_driver_data *pl08x = plchan->host;
1429         struct pl08x_txd *txd;
1430         int ret;
1431
1432         /*
1433          * Current implementation ASSUMES only one sg
1434          */
1435         if (sg_len != 1) {
1436                 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1437                         __func__);
1438                 BUG();
1439         }
1440
1441         dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1442                 __func__, sgl->length, plchan->name);
1443
1444         txd = pl08x_get_txd(plchan);
1445         if (!txd) {
1446                 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1447                 return NULL;
1448         }
1449
1450         if (direction != plchan->runtime_direction)
1451                 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1452                         "the direction configured for the PrimeCell\n",
1453                         __func__);
1454
1455         /*
1456          * Set up addresses, the PrimeCell configured address
1457          * will take precedence since this may configure the
1458          * channel target address dynamically at runtime.
1459          */
1460         txd->direction = direction;
1461         if (direction == DMA_TO_DEVICE) {
1462                 txd->srcbus.addr = sgl->dma_address;
1463                 if (plchan->runtime_addr)
1464                         txd->dstbus.addr = plchan->runtime_addr;
1465                 else
1466                         txd->dstbus.addr = plchan->cd->addr;
1467         } else if (direction == DMA_FROM_DEVICE) {
1468                 if (plchan->runtime_addr)
1469                         txd->srcbus.addr = plchan->runtime_addr;
1470                 else
1471                         txd->srcbus.addr = plchan->cd->addr;
1472                 txd->dstbus.addr = sgl->dma_address;
1473         } else {
1474                 dev_err(&pl08x->adev->dev,
1475                         "%s direction unsupported\n", __func__);
1476                 return NULL;
1477         }
1478         txd->cd = plchan->cd;
1479         txd->len = sgl->length;
1480
1481         ret = pl08x_prep_channel_resources(plchan, txd);
1482         if (ret)
1483                 return NULL;
1484         /*
1485          * NB: the channel lock is held at this point so tx_submit()
1486          * must be called in direct succession.
1487          */
1488
1489         return &txd->tx;
1490 }
1491
1492 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1493                          unsigned long arg)
1494 {
1495         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1496         struct pl08x_driver_data *pl08x = plchan->host;
1497         unsigned long flags;
1498         int ret = 0;
1499
1500         /* Controls applicable to inactive channels */
1501         if (cmd == DMA_SLAVE_CONFIG) {
1502                 dma_set_runtime_config(chan,
1503                                        (struct dma_slave_config *)
1504                                        arg);
1505                 return 0;
1506         }
1507
1508         /*
1509          * Anything succeeds on channels with no physical allocation and
1510          * no queued transfers.
1511          */
1512         spin_lock_irqsave(&plchan->lock, flags);
1513         if (!plchan->phychan && !plchan->at) {
1514                 spin_unlock_irqrestore(&plchan->lock, flags);
1515                 return 0;
1516         }
1517
1518         switch (cmd) {
1519         case DMA_TERMINATE_ALL:
1520                 plchan->state = PL08X_CHAN_IDLE;
1521
1522                 if (plchan->phychan) {
1523                         pl08x_stop_phy_chan(plchan->phychan);
1524
1525                         /*
1526                          * Mark physical channel as free and free any slave
1527                          * signal
1528                          */
1529                         release_phy_channel(plchan);
1530                 }
1531                 /* Dequeue jobs and free LLIs */
1532                 if (plchan->at) {
1533                         pl08x_free_txd(pl08x, plchan->at);
1534                         plchan->at = NULL;
1535                 }
1536                 /* Dequeue jobs not yet fired as well */
1537                 pl08x_free_txd_list(pl08x, plchan);
1538                 break;
1539         case DMA_PAUSE:
1540                 pl08x_pause_phy_chan(plchan->phychan);
1541                 plchan->state = PL08X_CHAN_PAUSED;
1542                 break;
1543         case DMA_RESUME:
1544                 pl08x_resume_phy_chan(plchan->phychan);
1545                 plchan->state = PL08X_CHAN_RUNNING;
1546                 break;
1547         default:
1548                 /* Unknown command */
1549                 ret = -ENXIO;
1550                 break;
1551         }
1552
1553         spin_unlock_irqrestore(&plchan->lock, flags);
1554
1555         return ret;
1556 }
1557
1558 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1559 {
1560         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1561         char *name = chan_id;
1562
1563         /* Check that the channel is not taken! */
1564         if (!strcmp(plchan->name, name))
1565                 return true;
1566
1567         return false;
1568 }
1569
1570 /*
1571  * Just check that the device is there and active
1572  * TODO: turn this bit on/off depending on the number of
1573  * physical channels actually used, if it is zero... well
1574  * shut it off. That will save some power. Cut the clock
1575  * at the same time.
1576  */
1577 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1578 {
1579         u32 val;
1580
1581         val = readl(pl08x->base + PL080_CONFIG);
1582         val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1583         /* We implicitly clear bit 1 and that means little-endian mode */
1584         val |= PL080_CONFIG_ENABLE;
1585         writel(val, pl08x->base + PL080_CONFIG);
1586 }
1587
1588 static void pl08x_tasklet(unsigned long data)
1589 {
1590         struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1591         struct pl08x_driver_data *pl08x = plchan->host;
1592         unsigned long flags;
1593
1594         spin_lock_irqsave(&plchan->lock, flags);
1595
1596         if (plchan->at) {
1597                 dma_async_tx_callback callback =
1598                         plchan->at->tx.callback;
1599                 void *callback_param =
1600                         plchan->at->tx.callback_param;
1601
1602                 /*
1603                  * Update last completed
1604                  */
1605                 plchan->lc = plchan->at->tx.cookie;
1606
1607                 /*
1608                  * Callback to signal completion
1609                  */
1610                 if (callback)
1611                         callback(callback_param);
1612
1613                 /*
1614                  * Free the descriptor
1615                  */
1616                 pl08x_free_txd(pl08x, plchan->at);
1617                 plchan->at = NULL;
1618         }
1619         /*
1620          * If a new descriptor is queued, set it up
1621          * plchan->at is NULL here
1622          */
1623         if (!list_empty(&plchan->desc_list)) {
1624                 struct pl08x_txd *next;
1625
1626                 next = list_first_entry(&plchan->desc_list,
1627                                         struct pl08x_txd,
1628                                         node);
1629                 list_del(&next->node);
1630                 plchan->at = next;
1631                 /* Configure the physical channel for the next txd */
1632                 pl08x_config_phychan_for_txd(plchan);
1633                 pl08x_set_cregs(pl08x, plchan->phychan);
1634                 pl08x_enable_phy_chan(pl08x, plchan->phychan);
1635         } else {
1636                 struct pl08x_dma_chan *waiting = NULL;
1637
1638                 /*
1639                  * No more jobs, so free up the physical channel
1640                  * Free any allocated signal on slave transfers too
1641                  */
1642                 release_phy_channel(plchan);
1643                 plchan->state = PL08X_CHAN_IDLE;
1644
1645                 /*
1646                  * And NOW before anyone else can grab that free:d
1647                  * up physical channel, see if there is some memcpy
1648                  * pending that seriously needs to start because of
1649                  * being stacked up while we were choking the
1650                  * physical channels with data.
1651                  */
1652                 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1653                                     chan.device_node) {
1654                   if (waiting->state == PL08X_CHAN_WAITING &&
1655                             waiting->waiting != NULL) {
1656                                 int ret;
1657
1658                                 /* This should REALLY not fail now */
1659                                 ret = prep_phy_channel(waiting,
1660                                                        waiting->waiting);
1661                                 BUG_ON(ret);
1662                                 waiting->state = PL08X_CHAN_RUNNING;
1663                                 waiting->waiting = NULL;
1664                                 pl08x_issue_pending(&waiting->chan);
1665                                 break;
1666                         }
1667                 }
1668         }
1669
1670         spin_unlock_irqrestore(&plchan->lock, flags);
1671 }
1672
1673 static irqreturn_t pl08x_irq(int irq, void *dev)
1674 {
1675         struct pl08x_driver_data *pl08x = dev;
1676         u32 mask = 0;
1677         u32 val;
1678         int i;
1679
1680         val = readl(pl08x->base + PL080_ERR_STATUS);
1681         if (val) {
1682                 /*
1683                  * An error interrupt (on one or more channels)
1684                  */
1685                 dev_err(&pl08x->adev->dev,
1686                         "%s error interrupt, register value 0x%08x\n",
1687                                 __func__, val);
1688                 /*
1689                  * Simply clear ALL PL08X error interrupts,
1690                  * regardless of channel and cause
1691                  * FIXME: should be 0x00000003 on PL081 really.
1692                  */
1693                 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1694         }
1695         val = readl(pl08x->base + PL080_INT_STATUS);
1696         for (i = 0; i < pl08x->vd->channels; i++) {
1697                 if ((1 << i) & val) {
1698                         /* Locate physical channel */
1699                         struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1700                         struct pl08x_dma_chan *plchan = phychan->serving;
1701
1702                         /* Schedule tasklet on this channel */
1703                         tasklet_schedule(&plchan->tasklet);
1704
1705                         mask |= (1 << i);
1706                 }
1707         }
1708         /*
1709          * Clear only the terminal interrupts on channels we processed
1710          */
1711         writel(mask, pl08x->base + PL080_TC_CLEAR);
1712
1713         return mask ? IRQ_HANDLED : IRQ_NONE;
1714 }
1715
1716 /*
1717  * Initialise the DMAC memcpy/slave channels.
1718  * Make a local wrapper to hold required data
1719  */
1720 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1721                                            struct dma_device *dmadev,
1722                                            unsigned int channels,
1723                                            bool slave)
1724 {
1725         struct pl08x_dma_chan *chan;
1726         int i;
1727
1728         INIT_LIST_HEAD(&dmadev->channels);
1729         /*
1730          * Register as many many memcpy as we have physical channels,
1731          * we won't always be able to use all but the code will have
1732          * to cope with that situation.
1733          */
1734         for (i = 0; i < channels; i++) {
1735                 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1736                 if (!chan) {
1737                         dev_err(&pl08x->adev->dev,
1738                                 "%s no memory for channel\n", __func__);
1739                         return -ENOMEM;
1740                 }
1741
1742                 chan->host = pl08x;
1743                 chan->state = PL08X_CHAN_IDLE;
1744
1745                 if (slave) {
1746                         chan->slave = true;
1747                         chan->name = pl08x->pd->slave_channels[i].bus_id;
1748                         chan->cd = &pl08x->pd->slave_channels[i];
1749                 } else {
1750                         chan->cd = &pl08x->pd->memcpy_channel;
1751                         chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1752                         if (!chan->name) {
1753                                 kfree(chan);
1754                                 return -ENOMEM;
1755                         }
1756                 }
1757                 if (chan->cd->circular_buffer) {
1758                         dev_err(&pl08x->adev->dev,
1759                                 "channel %s: circular buffers not supported\n",
1760                                 chan->name);
1761                         kfree(chan);
1762                         continue;
1763                 }
1764                 dev_info(&pl08x->adev->dev,
1765                          "initialize virtual channel \"%s\"\n",
1766                          chan->name);
1767
1768                 chan->chan.device = dmadev;
1769                 chan->chan.cookie = 0;
1770                 chan->lc = 0;
1771
1772                 spin_lock_init(&chan->lock);
1773                 INIT_LIST_HEAD(&chan->desc_list);
1774                 tasklet_init(&chan->tasklet, pl08x_tasklet,
1775                              (unsigned long) chan);
1776
1777                 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1778         }
1779         dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1780                  i, slave ? "slave" : "memcpy");
1781         return i;
1782 }
1783
1784 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1785 {
1786         struct pl08x_dma_chan *chan = NULL;
1787         struct pl08x_dma_chan *next;
1788
1789         list_for_each_entry_safe(chan,
1790                                  next, &dmadev->channels, chan.device_node) {
1791                 list_del(&chan->chan.device_node);
1792                 kfree(chan);
1793         }
1794 }
1795
1796 #ifdef CONFIG_DEBUG_FS
1797 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1798 {
1799         switch (state) {
1800         case PL08X_CHAN_IDLE:
1801                 return "idle";
1802         case PL08X_CHAN_RUNNING:
1803                 return "running";
1804         case PL08X_CHAN_PAUSED:
1805                 return "paused";
1806         case PL08X_CHAN_WAITING:
1807                 return "waiting";
1808         default:
1809                 break;
1810         }
1811         return "UNKNOWN STATE";
1812 }
1813
1814 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1815 {
1816         struct pl08x_driver_data *pl08x = s->private;
1817         struct pl08x_dma_chan *chan;
1818         struct pl08x_phy_chan *ch;
1819         unsigned long flags;
1820         int i;
1821
1822         seq_printf(s, "PL08x physical channels:\n");
1823         seq_printf(s, "CHANNEL:\tUSER:\n");
1824         seq_printf(s, "--------\t-----\n");
1825         for (i = 0; i < pl08x->vd->channels; i++) {
1826                 struct pl08x_dma_chan *virt_chan;
1827
1828                 ch = &pl08x->phy_chans[i];
1829
1830                 spin_lock_irqsave(&ch->lock, flags);
1831                 virt_chan = ch->serving;
1832
1833                 seq_printf(s, "%d\t\t%s\n",
1834                            ch->id, virt_chan ? virt_chan->name : "(none)");
1835
1836                 spin_unlock_irqrestore(&ch->lock, flags);
1837         }
1838
1839         seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1840         seq_printf(s, "CHANNEL:\tSTATE:\n");
1841         seq_printf(s, "--------\t------\n");
1842         list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1843                 seq_printf(s, "%s\t\t%s\n", chan->name,
1844                            pl08x_state_str(chan->state));
1845         }
1846
1847         seq_printf(s, "\nPL08x virtual slave channels:\n");
1848         seq_printf(s, "CHANNEL:\tSTATE:\n");
1849         seq_printf(s, "--------\t------\n");
1850         list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1851                 seq_printf(s, "%s\t\t%s\n", chan->name,
1852                            pl08x_state_str(chan->state));
1853         }
1854
1855         return 0;
1856 }
1857
1858 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1859 {
1860         return single_open(file, pl08x_debugfs_show, inode->i_private);
1861 }
1862
1863 static const struct file_operations pl08x_debugfs_operations = {
1864         .open           = pl08x_debugfs_open,
1865         .read           = seq_read,
1866         .llseek         = seq_lseek,
1867         .release        = single_release,
1868 };
1869
1870 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1871 {
1872         /* Expose a simple debugfs interface to view all clocks */
1873         (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1874                                    NULL, pl08x,
1875                                    &pl08x_debugfs_operations);
1876 }
1877
1878 #else
1879 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1880 {
1881 }
1882 #endif
1883
1884 static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
1885 {
1886         struct pl08x_driver_data *pl08x;
1887         const struct vendor_data *vd = id->data;
1888         int ret = 0;
1889         int i;
1890
1891         ret = amba_request_regions(adev, NULL);
1892         if (ret)
1893                 return ret;
1894
1895         /* Create the driver state holder */
1896         pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1897         if (!pl08x) {
1898                 ret = -ENOMEM;
1899                 goto out_no_pl08x;
1900         }
1901
1902         /* Initialize memcpy engine */
1903         dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1904         pl08x->memcpy.dev = &adev->dev;
1905         pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1906         pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1907         pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1908         pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1909         pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1910         pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1911         pl08x->memcpy.device_control = pl08x_control;
1912
1913         /* Initialize slave engine */
1914         dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1915         pl08x->slave.dev = &adev->dev;
1916         pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1917         pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1918         pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1919         pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1920         pl08x->slave.device_issue_pending = pl08x_issue_pending;
1921         pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1922         pl08x->slave.device_control = pl08x_control;
1923
1924         /* Get the platform data */
1925         pl08x->pd = dev_get_platdata(&adev->dev);
1926         if (!pl08x->pd) {
1927                 dev_err(&adev->dev, "no platform data supplied\n");
1928                 goto out_no_platdata;
1929         }
1930
1931         /* Assign useful pointers to the driver state */
1932         pl08x->adev = adev;
1933         pl08x->vd = vd;
1934
1935         /* A DMA memory pool for LLIs, align on 1-byte boundary */
1936         pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1937                         PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1938         if (!pl08x->pool) {
1939                 ret = -ENOMEM;
1940                 goto out_no_lli_pool;
1941         }
1942
1943         spin_lock_init(&pl08x->lock);
1944
1945         pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1946         if (!pl08x->base) {
1947                 ret = -ENOMEM;
1948                 goto out_no_ioremap;
1949         }
1950
1951         /* Turn on the PL08x */
1952         pl08x_ensure_on(pl08x);
1953
1954         /*
1955          * Attach the interrupt handler
1956          */
1957         writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1958         writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1959
1960         ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1961                           DRIVER_NAME, pl08x);
1962         if (ret) {
1963                 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1964                         __func__, adev->irq[0]);
1965                 goto out_no_irq;
1966         }
1967
1968         /* Initialize physical channels */
1969         pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1970                         GFP_KERNEL);
1971         if (!pl08x->phy_chans) {
1972                 dev_err(&adev->dev, "%s failed to allocate "
1973                         "physical channel holders\n",
1974                         __func__);
1975                 goto out_no_phychans;
1976         }
1977
1978         for (i = 0; i < vd->channels; i++) {
1979                 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1980
1981                 ch->id = i;
1982                 ch->base = pl08x->base + PL080_Cx_BASE(i);
1983                 spin_lock_init(&ch->lock);
1984                 ch->serving = NULL;
1985                 ch->signal = -1;
1986                 dev_info(&adev->dev,
1987                          "physical channel %d is %s\n", i,
1988                          pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1989         }
1990
1991         /* Register as many memcpy channels as there are physical channels */
1992         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1993                                               pl08x->vd->channels, false);
1994         if (ret <= 0) {
1995                 dev_warn(&pl08x->adev->dev,
1996                          "%s failed to enumerate memcpy channels - %d\n",
1997                          __func__, ret);
1998                 goto out_no_memcpy;
1999         }
2000         pl08x->memcpy.chancnt = ret;
2001
2002         /* Register slave channels */
2003         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
2004                                               pl08x->pd->num_slave_channels,
2005                                               true);
2006         if (ret <= 0) {
2007                 dev_warn(&pl08x->adev->dev,
2008                         "%s failed to enumerate slave channels - %d\n",
2009                                 __func__, ret);
2010                 goto out_no_slave;
2011         }
2012         pl08x->slave.chancnt = ret;
2013
2014         ret = dma_async_device_register(&pl08x->memcpy);
2015         if (ret) {
2016                 dev_warn(&pl08x->adev->dev,
2017                         "%s failed to register memcpy as an async device - %d\n",
2018                         __func__, ret);
2019                 goto out_no_memcpy_reg;
2020         }
2021
2022         ret = dma_async_device_register(&pl08x->slave);
2023         if (ret) {
2024                 dev_warn(&pl08x->adev->dev,
2025                         "%s failed to register slave as an async device - %d\n",
2026                         __func__, ret);
2027                 goto out_no_slave_reg;
2028         }
2029
2030         amba_set_drvdata(adev, pl08x);
2031         init_pl08x_debugfs(pl08x);
2032         dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2033                  amba_part(adev), amba_rev(adev),
2034                  (unsigned long long)adev->res.start, adev->irq[0]);
2035         return 0;
2036
2037 out_no_slave_reg:
2038         dma_async_device_unregister(&pl08x->memcpy);
2039 out_no_memcpy_reg:
2040         pl08x_free_virtual_channels(&pl08x->slave);
2041 out_no_slave:
2042         pl08x_free_virtual_channels(&pl08x->memcpy);
2043 out_no_memcpy:
2044         kfree(pl08x->phy_chans);
2045 out_no_phychans:
2046         free_irq(adev->irq[0], pl08x);
2047 out_no_irq:
2048         iounmap(pl08x->base);
2049 out_no_ioremap:
2050         dma_pool_destroy(pl08x->pool);
2051 out_no_lli_pool:
2052 out_no_platdata:
2053         kfree(pl08x);
2054 out_no_pl08x:
2055         amba_release_regions(adev);
2056         return ret;
2057 }
2058
2059 /* PL080 has 8 channels and the PL080 have just 2 */
2060 static struct vendor_data vendor_pl080 = {
2061         .channels = 8,
2062         .dualmaster = true,
2063 };
2064
2065 static struct vendor_data vendor_pl081 = {
2066         .channels = 2,
2067         .dualmaster = false,
2068 };
2069
2070 static struct amba_id pl08x_ids[] = {
2071         /* PL080 */
2072         {
2073                 .id     = 0x00041080,
2074                 .mask   = 0x000fffff,
2075                 .data   = &vendor_pl080,
2076         },
2077         /* PL081 */
2078         {
2079                 .id     = 0x00041081,
2080                 .mask   = 0x000fffff,
2081                 .data   = &vendor_pl081,
2082         },
2083         /* Nomadik 8815 PL080 variant */
2084         {
2085                 .id     = 0x00280880,
2086                 .mask   = 0x00ffffff,
2087                 .data   = &vendor_pl080,
2088         },
2089         { 0, 0 },
2090 };
2091
2092 static struct amba_driver pl08x_amba_driver = {
2093         .drv.name       = DRIVER_NAME,
2094         .id_table       = pl08x_ids,
2095         .probe          = pl08x_probe,
2096 };
2097
2098 static int __init pl08x_init(void)
2099 {
2100         int retval;
2101         retval = amba_driver_register(&pl08x_amba_driver);
2102         if (retval)
2103                 printk(KERN_WARNING DRIVER_NAME
2104                        "failed to register as an AMBA device (%d)\n",
2105                        retval);
2106         return retval;
2107 }
2108 subsys_initcall(pl08x_init);