1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright(c) 2022 Intel Corporation. All rights reserved. */
3 #include <linux/debugfs.h>
4 #include <linux/device.h>
5 #include <linux/module.h>
14 * CXL memory endpoint devices and switches are CXL capable devices that are
15 * participating in CXL.mem protocol. Their functionality builds on top of the
16 * CXL.io protocol that allows enumerating and configuring components via
17 * standard PCI mechanisms.
19 * The cxl_mem driver owns kicking off the enumeration of this CXL.mem
20 * capability. With the detection of a CXL capable endpoint, the driver will
21 * walk up to find the platform specific port it is connected to, and determine
22 * if there are intervening switches in the path. If there are switches, a
23 * secondary action is to enumerate those (implemented in cxl_core). Finally the
24 * cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use
25 * in higher level operations.
28 static void enable_suspend(void *data)
33 static void remove_debugfs(void *dentry)
35 debugfs_remove_recursive(dentry);
38 static int cxl_mem_dpa_show(struct seq_file *file, void *data)
40 struct device *dev = file->private;
41 struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
43 cxl_dpa_debug(file, cxlmd->cxlds);
48 static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
49 struct cxl_dport *parent_dport)
51 struct cxl_port *parent_port = parent_dport->port;
52 struct cxl_dev_state *cxlds = cxlmd->cxlds;
53 struct cxl_port *endpoint, *iter, *down;
54 resource_size_t component_reg_phys;
58 * Now that the path to the root is established record all the
59 * intervening ports in the chain.
61 for (iter = parent_port, down = NULL; !is_cxl_root(iter);
62 down = iter, iter = to_cxl_port(iter->dev.parent)) {
65 ep = cxl_ep_load(iter, cxlmd);
70 * The component registers for an RCD might come from the
71 * host-bridge RCRB if they are not already mapped via the
72 * typical register locator mechanism.
74 if (parent_dport->rch && cxlds->component_reg_phys == CXL_RESOURCE_NONE)
75 component_reg_phys = cxl_rcrb_to_component(
76 &cxlmd->dev, parent_dport->rcrb, CXL_RCRB_UPSTREAM);
78 component_reg_phys = cxlds->component_reg_phys;
79 endpoint = devm_cxl_add_port(host, &cxlmd->dev, component_reg_phys,
82 return PTR_ERR(endpoint);
84 rc = cxl_endpoint_autoremove(cxlmd, endpoint);
88 if (!endpoint->dev.driver) {
89 dev_err(&cxlmd->dev, "%s failed probe\n",
90 dev_name(&endpoint->dev));
97 static int cxl_mem_probe(struct device *dev)
99 struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
100 struct cxl_dev_state *cxlds = cxlmd->cxlds;
101 struct device *endpoint_parent;
102 struct cxl_port *parent_port;
103 struct cxl_dport *dport;
104 struct dentry *dentry;
108 * Someone is trying to reattach this device after it lost its port
109 * connection (an endpoint port previously registered by this memdev was
110 * disabled). This racy check is ok because if the port is still gone,
111 * no harm done, and if the port hierarchy comes back it will re-trigger
112 * this probe. Port rescan and memdev detach work share the same
113 * single-threaded workqueue.
115 if (work_pending(&cxlmd->detach_work))
118 dentry = cxl_debugfs_create_dir(dev_name(dev));
119 debugfs_create_devm_seqfile(dev, "dpamem", dentry, cxl_mem_dpa_show);
120 rc = devm_add_action_or_reset(dev, remove_debugfs, dentry);
124 rc = devm_cxl_enumerate_ports(cxlmd);
128 parent_port = cxl_mem_find_port(cxlmd, &dport);
130 dev_err(dev, "CXL port topology not found\n");
135 endpoint_parent = parent_port->uport;
137 endpoint_parent = &parent_port->dev;
139 device_lock(endpoint_parent);
140 if (!endpoint_parent->driver) {
141 dev_err(dev, "CXL port topology %s not enabled\n",
142 dev_name(endpoint_parent));
147 rc = devm_cxl_add_endpoint(endpoint_parent, cxlmd, dport);
149 device_unlock(endpoint_parent);
150 put_device(&parent_port->dev);
154 if (resource_size(&cxlds->pmem_res) && IS_ENABLED(CONFIG_CXL_PMEM)) {
155 rc = devm_cxl_add_nvdimm(cxlmd);
157 dev_info(dev, "PMEM disabled by platform\n");
163 * The kernel may be operating out of CXL memory on this device,
164 * there is no spec defined way to determine whether this device
165 * preserves contents over suspend, and there is no simple way
166 * to arrange for the suspend image to avoid CXL memory which
167 * would setup a circular dependency between PCI resume and save
170 * TODO: support suspend when all the regions this device is
171 * hosting are locked and covered by the system address map,
172 * i.e. platform firmware owns restoring the HDM configuration
175 cxl_mem_active_inc();
176 return devm_add_action_or_reset(dev, enable_suspend, NULL);
179 static struct cxl_driver cxl_mem_driver = {
181 .probe = cxl_mem_probe,
182 .id = CXL_DEVICE_MEMORY_EXPANDER,
185 module_cxl_driver(cxl_mem_driver);
187 MODULE_LICENSE("GPL v2");
188 MODULE_IMPORT_NS(CXL);
189 MODULE_ALIAS_CXL(CXL_DEVICE_MEMORY_EXPANDER);
191 * create_endpoint() wants to validate port driver attach immediately after
192 * endpoint registration.
194 MODULE_SOFTDEP("pre: cxl_port");