drivers/cxl/acpi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright(c) 2021 Intel Corporation. All rights reserved. */
   3 #include <linux/platform_device.h>
   4 #include <linux/module.h>
   5 #include <linux/device.h>
   6 #include <linux/kernel.h>
   7 #include <linux/acpi.h>
   8 #include <linux/pci.h>
   9 #include <asm/div64.h>
  10 #include "cxlpci.h"
  11 #include "cxl.h"
  12
  13 #define CXL_RCRB_SIZE   SZ_8K
  14
  15 struct cxl_cxims_data {
  16         int nr_maps;
  17         u64 xormaps[] __counted_by(nr_maps);
  18 };
  19
  20 /*
  21  * Find a targets entry (n) in the host bridge interleave list.
  22  * CXL Specification 3.0 Table 9-22
  23  */
  24 static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw,
  25                           int ig)
  26 {
  27         int i = 0, n = 0;
  28         u8 eiw;
  29
  30         /* IW: 2,4,6,8,12,16 begin building 'n' using xormaps */
  31         if (iw != 3) {
  32                 for (i = 0; i < cximsd->nr_maps; i++)
  33                         n |= (hweight64(hpa & cximsd->xormaps[i]) & 1) << i;
  34         }
  35         /* IW: 3,6,12 add a modulo calculation to 'n' */
  36         if (!is_power_of_2(iw)) {
  37                 if (ways_to_eiw(iw, &eiw))
  38                         return -1;
  39                 hpa &= GENMASK_ULL(51, eiw + ig);
  40                 n |= do_div(hpa, 3) << i;
  41         }
  42         return n;
  43 }
  44
  45 static struct cxl_dport *cxl_hb_xor(struct cxl_root_decoder *cxlrd, int pos)
  46 {
  47         struct cxl_cxims_data *cximsd = cxlrd->platform_data;
  48         struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd;
  49         struct cxl_decoder *cxld = &cxlsd->cxld;
  50         int ig = cxld->interleave_granularity;
  51         int iw = cxld->interleave_ways;
  52         int n = 0;
  53         u64 hpa;
  54
  55         if (dev_WARN_ONCE(&cxld->dev,
  56                           cxld->interleave_ways != cxlsd->nr_targets,
  57                           "misconfigured root decoder\n"))
  58                 return NULL;
  59
  60         hpa = cxlrd->res->start + pos * ig;
  61
  62         /* Entry (n) is 0 for no interleave (iw == 1) */
  63         if (iw != 1)
  64                 n = cxl_xor_calc_n(hpa, cximsd, iw, ig);
  65
  66         if (n < 0)
  67                 return NULL;
  68
  69         return cxlrd->cxlsd.target[n];
  70 }
  71
  72 struct cxl_cxims_context {
  73         struct device *dev;
  74         struct cxl_root_decoder *cxlrd;
  75 };
  76
  77 static int cxl_parse_cxims(union acpi_subtable_headers *header, void *arg,
  78                            const unsigned long end)
  79 {
  80         struct acpi_cedt_cxims *cxims = (struct acpi_cedt_cxims *)header;
  81         struct cxl_cxims_context *ctx = arg;
  82         struct cxl_root_decoder *cxlrd = ctx->cxlrd;
  83         struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
  84         struct device *dev = ctx->dev;
  85         struct cxl_cxims_data *cximsd;
  86         unsigned int hbig, nr_maps;
  87         int rc;
  88
  89         rc = eig_to_granularity(cxims->hbig, &hbig);
  90         if (rc)
  91                 return rc;
  92
  93         /* Does this CXIMS entry apply to the given CXL Window? */
  94         if (hbig != cxld->interleave_granularity)
  95                 return 0;
  96
  97         /* IW 1,3 do not use xormaps and skip this parsing entirely */
  98         if (is_power_of_2(cxld->interleave_ways))
  99                 /* 2, 4, 8, 16 way */
 100                 nr_maps = ilog2(cxld->interleave_ways);
 101         else
 102                 /* 6, 12 way */
 103                 nr_maps = ilog2(cxld->interleave_ways / 3);
 104
 105         if (cxims->nr_xormaps < nr_maps) {
 106                 dev_dbg(dev, "CXIMS nr_xormaps[%d] expected[%d]\n",
 107                         cxims->nr_xormaps, nr_maps);
 108                 return -ENXIO;
 109         }
 110
 111         cximsd = devm_kzalloc(dev, struct_size(cximsd, xormaps, nr_maps),
 112                               GFP_KERNEL);
 113         if (!cximsd)
 114                 return -ENOMEM;
 115         cximsd->nr_maps = nr_maps;
 116         memcpy(cximsd->xormaps, cxims->xormap_list,
 117                nr_maps * sizeof(*cximsd->xormaps));
 118         cxlrd->platform_data = cximsd;
 119
 120         return 0;
 121 }
 122
 123 static unsigned long cfmws_to_decoder_flags(int restrictions)
 124 {
 125         unsigned long flags = CXL_DECODER_F_ENABLE;
 126
 127         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2)
 128                 flags |= CXL_DECODER_F_TYPE2;
 129         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3)
 130                 flags |= CXL_DECODER_F_TYPE3;
 131         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE)
 132                 flags |= CXL_DECODER_F_RAM;
 133         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM)
 134                 flags |= CXL_DECODER_F_PMEM;
 135         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED)
 136                 flags |= CXL_DECODER_F_LOCK;
 137
 138         return flags;
 139 }
 140
 141 static int cxl_acpi_cfmws_verify(struct device *dev,
 142                                  struct acpi_cedt_cfmws *cfmws)
 143 {
 144         int rc, expected_len;
 145         unsigned int ways;
 146
 147         if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO &&
 148             cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
 149                 dev_err(dev, "CFMWS Unknown Interleave Arithmetic: %d\n",
 150                         cfmws->interleave_arithmetic);
 151                 return -EINVAL;
 152         }
 153
 154         if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) {
 155                 dev_err(dev, "CFMWS Base HPA not 256MB aligned\n");
 156                 return -EINVAL;
 157         }
 158
 159         if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) {
 160                 dev_err(dev, "CFMWS Window Size not 256MB aligned\n");
 161                 return -EINVAL;
 162         }
 163
 164         rc = eiw_to_ways(cfmws->interleave_ways, &ways);
 165         if (rc) {
 166                 dev_err(dev, "CFMWS Interleave Ways (%d) invalid\n",
 167                         cfmws->interleave_ways);
 168                 return -EINVAL;
 169         }
 170
 171         expected_len = struct_size(cfmws, interleave_targets, ways);
 172
 173         if (cfmws->header.length < expected_len) {
 174                 dev_err(dev, "CFMWS length %d less than expected %d\n",
 175                         cfmws->header.length, expected_len);
 176                 return -EINVAL;
 177         }
 178
 179         if (cfmws->header.length > expected_len)
 180                 dev_dbg(dev, "CFMWS length %d greater than expected %d\n",
 181                         cfmws->header.length, expected_len);
 182
 183         return 0;
 184 }
 185
 186 /*
 187  * Note, @dev must be the first member, see 'struct cxl_chbs_context'
 188  * and mock_acpi_table_parse_cedt()
 189  */
 190 struct cxl_cfmws_context {
 191         struct device *dev;
 192         struct cxl_port *root_port;
 193         struct resource *cxl_res;
 194         int id;
 195 };
 196
 197 static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
 198                            const unsigned long end)
 199 {
 200         int target_map[CXL_DECODER_MAX_INTERLEAVE];
 201         struct cxl_cfmws_context *ctx = arg;
 202         struct cxl_port *root_port = ctx->root_port;
 203         struct resource *cxl_res = ctx->cxl_res;
 204         struct cxl_cxims_context cxims_ctx;
 205         struct cxl_root_decoder *cxlrd;
 206         struct device *dev = ctx->dev;
 207         struct acpi_cedt_cfmws *cfmws;
 208         cxl_calc_hb_fn cxl_calc_hb;
 209         struct cxl_decoder *cxld;
 210         unsigned int ways, i, ig;
 211         struct resource *res;
 212         int rc;
 213
 214         cfmws = (struct acpi_cedt_cfmws *) header;
 215
 216         rc = cxl_acpi_cfmws_verify(dev, cfmws);
 217         if (rc) {
 218                 dev_err(dev, "CFMWS range %#llx-%#llx not registered\n",
 219                         cfmws->base_hpa,
 220                         cfmws->base_hpa + cfmws->window_size - 1);
 221                 return 0;
 222         }
 223
 224         rc = eiw_to_ways(cfmws->interleave_ways, &ways);
 225         if (rc)
 226                 return rc;
 227         rc = eig_to_granularity(cfmws->granularity, &ig);
 228         if (rc)
 229                 return rc;
 230         for (i = 0; i < ways; i++)
 231                 target_map[i] = cfmws->interleave_targets[i];
 232
 233         res = kzalloc(sizeof(*res), GFP_KERNEL);
 234         if (!res)
 235                 return -ENOMEM;
 236
 237         res->name = kasprintf(GFP_KERNEL, "CXL Window %d", ctx->id++);
 238         if (!res->name)
 239                 goto err_name;
 240
 241         res->start = cfmws->base_hpa;
 242         res->end = cfmws->base_hpa + cfmws->window_size - 1;
 243         res->flags = IORESOURCE_MEM;
 244
 245         /* add to the local resource tracking to establish a sort order */
 246         rc = insert_resource(cxl_res, res);
 247         if (rc)
 248                 goto err_insert;
 249
 250         if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_MODULO)
 251                 cxl_calc_hb = cxl_hb_modulo;
 252         else
 253                 cxl_calc_hb = cxl_hb_xor;
 254
 255         cxlrd = cxl_root_decoder_alloc(root_port, ways, cxl_calc_hb);
 256         if (IS_ERR(cxlrd))
 257                 return 0;
 258
 259         cxld = &cxlrd->cxlsd.cxld;
 260         cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
 261         cxld->target_type = CXL_DECODER_HOSTONLYMEM;
 262         cxld->hpa_range = (struct range) {
 263                 .start = res->start,
 264                 .end = res->end,
 265         };
 266         cxld->interleave_ways = ways;
 267         /*
 268          * Minimize the x1 granularity to advertise support for any
 269          * valid region granularity
 270          */
 271         if (ways == 1)
 272                 ig = CXL_DECODER_MIN_GRANULARITY;
 273         cxld->interleave_granularity = ig;
 274
 275         if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
 276                 if (ways != 1 && ways != 3) {
 277                         cxims_ctx = (struct cxl_cxims_context) {
 278                                 .dev = dev,
 279                                 .cxlrd = cxlrd,
 280                         };
 281                         rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CXIMS,
 282                                                    cxl_parse_cxims, &cxims_ctx);
 283                         if (rc < 0)
 284                                 goto err_xormap;
 285                         if (!cxlrd->platform_data) {
 286                                 dev_err(dev, "No CXIMS for HBIG %u\n", ig);
 287                                 rc = -EINVAL;
 288                                 goto err_xormap;
 289                         }
 290                 }
 291         }
 292
 293         cxlrd->qos_class = cfmws->qtg_id;
 294
 295         rc = cxl_decoder_add(cxld, target_map);
 296 err_xormap:
 297         if (rc)
 298                 put_device(&cxld->dev);
 299         else
 300                 rc = cxl_decoder_autoremove(dev, cxld);
 301         if (rc) {
 302                 dev_err(dev, "Failed to add decode range: %pr", res);
 303                 return rc;
 304         }
 305         dev_dbg(dev, "add: %s node: %d range [%#llx - %#llx]\n",
 306                 dev_name(&cxld->dev),
 307                 phys_to_target_node(cxld->hpa_range.start),
 308                 cxld->hpa_range.start, cxld->hpa_range.end);
 309
 310         return 0;
 311
 312 err_insert:
 313         kfree(res->name);
 314 err_name:
 315         kfree(res);
 316         return -ENOMEM;
 317 }
 318
 319 __mock struct acpi_device *to_cxl_host_bridge(struct device *host,
 320                                               struct device *dev)
 321 {
 322         struct acpi_device *adev = to_acpi_device(dev);
 323
 324         if (!acpi_pci_find_root(adev->handle))
 325                 return NULL;
 326
 327         if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0)
 328                 return adev;
 329         return NULL;
 330 }
 331
 332 /* Note, @dev is used by mock_acpi_table_parse_cedt() */
 333 struct cxl_chbs_context {
 334         struct device *dev;
 335         unsigned long long uid;
 336         resource_size_t base;
 337         u32 cxl_version;
 338 };
 339
 340 static int cxl_get_chbs_iter(union acpi_subtable_headers *header, void *arg,
 341                              const unsigned long end)
 342 {
 343         struct cxl_chbs_context *ctx = arg;
 344         struct acpi_cedt_chbs *chbs;
 345
 346         if (ctx->base != CXL_RESOURCE_NONE)
 347                 return 0;
 348
 349         chbs = (struct acpi_cedt_chbs *) header;
 350
 351         if (ctx->uid != chbs->uid)
 352                 return 0;
 353
 354         ctx->cxl_version = chbs->cxl_version;
 355         if (!chbs->base)
 356                 return 0;
 357
 358         if (chbs->cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11 &&
 359             chbs->length != CXL_RCRB_SIZE)
 360                 return 0;
 361
 362         ctx->base = chbs->base;
 363
 364         return 0;
 365 }
 366
 367 static int cxl_get_chbs(struct device *dev, struct acpi_device *hb,
 368                         struct cxl_chbs_context *ctx)
 369 {
 370         unsigned long long uid;
 371         int rc;
 372
 373         rc = acpi_evaluate_integer(hb->handle, METHOD_NAME__UID, NULL, &uid);
 374         if (rc != AE_OK) {
 375                 dev_err(dev, "unable to retrieve _UID\n");
 376                 return -ENOENT;
 377         }
 378
 379         dev_dbg(dev, "UID found: %lld\n", uid);
 380         *ctx = (struct cxl_chbs_context) {
 381                 .dev = dev,
 382                 .uid = uid,
 383                 .base = CXL_RESOURCE_NONE,
 384                 .cxl_version = UINT_MAX,
 385         };
 386
 387         acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbs_iter, ctx);
 388
 389         return 0;
 390 }
 391
 392 static int add_host_bridge_dport(struct device *match, void *arg)
 393 {
 394         acpi_status rc;
 395         struct device *bridge;
 396         struct cxl_dport *dport;
 397         struct cxl_chbs_context ctx;
 398         struct acpi_pci_root *pci_root;
 399         struct cxl_port *root_port = arg;
 400         struct device *host = root_port->dev.parent;
 401         struct acpi_device *hb = to_cxl_host_bridge(host, match);
 402
 403         if (!hb)
 404                 return 0;
 405
 406         rc = cxl_get_chbs(match, hb, &ctx);
 407         if (rc)
 408                 return rc;
 409
 410         if (ctx.cxl_version == UINT_MAX) {
 411                 dev_warn(match, "No CHBS found for Host Bridge (UID %lld)\n",
 412                          ctx.uid);
 413                 return 0;
 414         }
 415
 416         if (ctx.base == CXL_RESOURCE_NONE) {
 417                 dev_warn(match, "CHBS invalid for Host Bridge (UID %lld)\n",
 418                          ctx.uid);
 419                 return 0;
 420         }
 421
 422         pci_root = acpi_pci_find_root(hb->handle);
 423         bridge = pci_root->bus->bridge;
 424
 425         /*
 426          * In RCH mode, bind the component regs base to the dport. In
 427          * VH mode it will be bound to the CXL host bridge's port
 428          * object later in add_host_bridge_uport().
 429          */
 430         if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
 431                 dev_dbg(match, "RCRB found for UID %lld: %pa\n", ctx.uid,
 432                         &ctx.base);
 433                 dport = devm_cxl_add_rch_dport(root_port, bridge, ctx.uid,
 434                                                ctx.base);
 435         } else {
 436                 dport = devm_cxl_add_dport(root_port, bridge, ctx.uid,
 437                                            CXL_RESOURCE_NONE);
 438         }
 439
 440         if (IS_ERR(dport))
 441                 return PTR_ERR(dport);
 442
 443         return 0;
 444 }
 445
 446 /*
 447  * A host bridge is a dport to a CFMWS decode and it is a uport to the
 448  * dport (PCIe Root Ports) in the host bridge.
 449  */
 450 static int add_host_bridge_uport(struct device *match, void *arg)
 451 {
 452         struct cxl_port *root_port = arg;
 453         struct device *host = root_port->dev.parent;
 454         struct acpi_device *hb = to_cxl_host_bridge(host, match);
 455         struct acpi_pci_root *pci_root;
 456         struct cxl_dport *dport;
 457         struct cxl_port *port;
 458         struct device *bridge;
 459         struct cxl_chbs_context ctx;
 460         resource_size_t component_reg_phys;
 461         int rc;
 462
 463         if (!hb)
 464                 return 0;
 465
 466         pci_root = acpi_pci_find_root(hb->handle);
 467         bridge = pci_root->bus->bridge;
 468         dport = cxl_find_dport_by_dev(root_port, bridge);
 469         if (!dport) {
 470                 dev_dbg(host, "host bridge expected and not found\n");
 471                 return 0;
 472         }
 473
 474         if (dport->rch) {
 475                 dev_info(bridge, "host supports CXL (restricted)\n");
 476                 return 0;
 477         }
 478
 479         rc = cxl_get_chbs(match, hb, &ctx);
 480         if (rc)
 481                 return rc;
 482
 483         if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
 484                 dev_warn(bridge,
 485                          "CXL CHBS version mismatch, skip port registration\n");
 486                 return 0;
 487         }
 488
 489         component_reg_phys = ctx.base;
 490         if (component_reg_phys != CXL_RESOURCE_NONE)
 491                 dev_dbg(match, "CHBCR found for UID %lld: %pa\n",
 492                         ctx.uid, &component_reg_phys);
 493
 494         rc = devm_cxl_register_pci_bus(host, bridge, pci_root->bus);
 495         if (rc)
 496                 return rc;
 497
 498         port = devm_cxl_add_port(host, bridge, component_reg_phys, dport);
 499         if (IS_ERR(port))
 500                 return PTR_ERR(port);
 501
 502         dev_info(bridge, "host supports CXL\n");
 503
 504         return 0;
 505 }
 506
 507 static int add_root_nvdimm_bridge(struct device *match, void *data)
 508 {
 509         struct cxl_decoder *cxld;
 510         struct cxl_port *root_port = data;
 511         struct cxl_nvdimm_bridge *cxl_nvb;
 512         struct device *host = root_port->dev.parent;
 513
 514         if (!is_root_decoder(match))
 515                 return 0;
 516
 517         cxld = to_cxl_decoder(match);
 518         if (!(cxld->flags & CXL_DECODER_F_PMEM))
 519                 return 0;
 520
 521         cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port);
 522         if (IS_ERR(cxl_nvb)) {
 523                 dev_dbg(host, "failed to register pmem\n");
 524                 return PTR_ERR(cxl_nvb);
 525         }
 526         dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev),
 527                 dev_name(&cxl_nvb->dev));
 528         return 1;
 529 }
 530
 531 static struct lock_class_key cxl_root_key;
 532
 533 static void cxl_acpi_lock_reset_class(void *dev)
 534 {
 535         device_lock_reset_class(dev);
 536 }
 537
 538 static void del_cxl_resource(struct resource *res)
 539 {
 540         kfree(res->name);
 541         kfree(res);
 542 }
 543
 544 static void cxl_set_public_resource(struct resource *priv, struct resource *pub)
 545 {
 546         priv->desc = (unsigned long) pub;
 547 }
 548
 549 static struct resource *cxl_get_public_resource(struct resource *priv)
 550 {
 551         return (struct resource *) priv->desc;
 552 }
 553
 554 static void remove_cxl_resources(void *data)
 555 {
 556         struct resource *res, *next, *cxl = data;
 557
 558         for (res = cxl->child; res; res = next) {
 559                 struct resource *victim = cxl_get_public_resource(res);
 560
 561                 next = res->sibling;
 562                 remove_resource(res);
 563
 564                 if (victim) {
 565                         remove_resource(victim);
 566                         kfree(victim);
 567                 }
 568
 569                 del_cxl_resource(res);
 570         }
 571 }
 572
 573 /**
 574  * add_cxl_resources() - reflect CXL fixed memory windows in iomem_resource
 575  * @cxl_res: A standalone resource tree where each CXL window is a sibling
 576  *
 577  * Walk each CXL window in @cxl_res and add it to iomem_resource potentially
 578  * expanding its boundaries to ensure that any conflicting resources become
 579  * children. If a window is expanded it may then conflict with a another window
 580  * entry and require the window to be truncated or trimmed. Consider this
 581  * situation:
 582  *
 583  * |-- "CXL Window 0" --||----- "CXL Window 1" -----|
 584  * |--------------- "System RAM" -------------|
 585  *
 586  * ...where platform firmware has established as System RAM resource across 2
 587  * windows, but has left some portion of window 1 for dynamic CXL region
 588  * provisioning. In this case "Window 0" will span the entirety of the "System
 589  * RAM" span, and "CXL Window 1" is truncated to the remaining tail past the end
 590  * of that "System RAM" resource.
 591  */
 592 static int add_cxl_resources(struct resource *cxl_res)
 593 {
 594         struct resource *res, *new, *next;
 595
 596         for (res = cxl_res->child; res; res = next) {
 597                 new = kzalloc(sizeof(*new), GFP_KERNEL);
 598                 if (!new)
 599                         return -ENOMEM;
 600                 new->name = res->name;
 601                 new->start = res->start;
 602                 new->end = res->end;
 603                 new->flags = IORESOURCE_MEM;
 604                 new->desc = IORES_DESC_CXL;
 605
 606                 /*
 607                  * Record the public resource in the private cxl_res tree for
 608                  * later removal.
 609                  */
 610                 cxl_set_public_resource(res, new);
 611
 612                 insert_resource_expand_to_fit(&iomem_resource, new);
 613
 614                 next = res->sibling;
 615                 while (next && resource_overlaps(new, next)) {
 616                         if (resource_contains(new, next)) {
 617                                 struct resource *_next = next->sibling;
 618
 619                                 remove_resource(next);
 620                                 del_cxl_resource(next);
 621                                 next = _next;
 622                         } else
 623                                 next->start = new->end + 1;
 624                 }
 625         }
 626         return 0;
 627 }
 628
 629 static int pair_cxl_resource(struct device *dev, void *data)
 630 {
 631         struct resource *cxl_res = data;
 632         struct resource *p;
 633
 634         if (!is_root_decoder(dev))
 635                 return 0;
 636
 637         for (p = cxl_res->child; p; p = p->sibling) {
 638                 struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev);
 639                 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
 640                 struct resource res = {
 641                         .start = cxld->hpa_range.start,
 642                         .end = cxld->hpa_range.end,
 643                         .flags = IORESOURCE_MEM,
 644                 };
 645
 646                 if (resource_contains(p, &res)) {
 647                         cxlrd->res = cxl_get_public_resource(p);
 648                         break;
 649                 }
 650         }
 651
 652         return 0;
 653 }
 654
 655 static int cxl_acpi_probe(struct platform_device *pdev)
 656 {
 657         int rc;
 658         struct resource *cxl_res;
 659         struct cxl_port *root_port;
 660         struct device *host = &pdev->dev;
 661         struct acpi_device *adev = ACPI_COMPANION(host);
 662         struct cxl_cfmws_context ctx;
 663
 664         device_lock_set_class(&pdev->dev, &cxl_root_key);
 665         rc = devm_add_action_or_reset(&pdev->dev, cxl_acpi_lock_reset_class,
 666                                       &pdev->dev);
 667         if (rc)
 668                 return rc;
 669
 670         cxl_res = devm_kzalloc(host, sizeof(*cxl_res), GFP_KERNEL);
 671         if (!cxl_res)
 672                 return -ENOMEM;
 673         cxl_res->name = "CXL mem";
 674         cxl_res->start = 0;
 675         cxl_res->end = -1;
 676         cxl_res->flags = IORESOURCE_MEM;
 677
 678         root_port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);
 679         if (IS_ERR(root_port))
 680                 return PTR_ERR(root_port);
 681
 682         rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
 683                               add_host_bridge_dport);
 684         if (rc < 0)
 685                 return rc;
 686
 687         rc = devm_add_action_or_reset(host, remove_cxl_resources, cxl_res);
 688         if (rc)
 689                 return rc;
 690
 691         ctx = (struct cxl_cfmws_context) {
 692                 .dev = host,
 693                 .root_port = root_port,
 694                 .cxl_res = cxl_res,
 695         };
 696         rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx);
 697         if (rc < 0)
 698                 return -ENXIO;
 699
 700         rc = add_cxl_resources(cxl_res);
 701         if (rc)
 702                 return rc;
 703
 704         /*
 705          * Populate the root decoders with their related iomem resource,
 706          * if present
 707          */
 708         device_for_each_child(&root_port->dev, cxl_res, pair_cxl_resource);
 709
 710         /*
 711          * Root level scanned with host-bridge as dports, now scan host-bridges
 712          * for their role as CXL uports to their CXL-capable PCIe Root Ports.
 713          */
 714         rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
 715                               add_host_bridge_uport);
 716         if (rc < 0)
 717                 return rc;
 718
 719         if (IS_ENABLED(CONFIG_CXL_PMEM))
 720                 rc = device_for_each_child(&root_port->dev, root_port,
 721                                            add_root_nvdimm_bridge);
 722         if (rc < 0)
 723                 return rc;
 724
 725         /* In case PCI is scanned before ACPI re-trigger memdev attach */
 726         cxl_bus_rescan();
 727         return 0;
 728 }
 729
 730 static const struct acpi_device_id cxl_acpi_ids[] = {
 731         { "ACPI0017" },
 732         { },
 733 };
 734 MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids);
 735
 736 static const struct platform_device_id cxl_test_ids[] = {
 737         { "cxl_acpi" },
 738         { },
 739 };
 740 MODULE_DEVICE_TABLE(platform, cxl_test_ids);
 741
 742 static struct platform_driver cxl_acpi_driver = {
 743         .probe = cxl_acpi_probe,
 744         .driver = {
 745                 .name = KBUILD_MODNAME,
 746                 .acpi_match_table = cxl_acpi_ids,
 747         },
 748         .id_table = cxl_test_ids,
 749 };
 750
 751 static int __init cxl_acpi_init(void)
 752 {
 753         return platform_driver_register(&cxl_acpi_driver);
 754 }
 755
 756 static void __exit cxl_acpi_exit(void)
 757 {
 758         platform_driver_unregister(&cxl_acpi_driver);
 759         cxl_bus_drain();
 760 }
 761
 762 /* load before dax_hmem sees 'Soft Reserved' CXL ranges */
 763 subsys_initcall(cxl_acpi_init);
 764 module_exit(cxl_acpi_exit);
 765 MODULE_LICENSE("GPL v2");
 766 MODULE_IMPORT_NS(CXL);
 767 MODULE_IMPORT_NS(ACPI);