1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright(c) 2021 Intel Corporation. All rights reserved. */
3 #include <linux/platform_device.h>
4 #include <linux/module.h>
5 #include <linux/device.h>
6 #include <linux/kernel.h>
7 #include <linux/acpi.h>
13 #define CXL_RCRB_SIZE SZ_8K
15 struct cxl_cxims_data {
17 u64 xormaps[] __counted_by(nr_maps);
21 * Find a targets entry (n) in the host bridge interleave list.
22 * CXL Specification 3.0 Table 9-22
24 static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw,
30 /* IW: 2,4,6,8,12,16 begin building 'n' using xormaps */
32 for (i = 0; i < cximsd->nr_maps; i++)
33 n |= (hweight64(hpa & cximsd->xormaps[i]) & 1) << i;
35 /* IW: 3,6,12 add a modulo calculation to 'n' */
36 if (!is_power_of_2(iw)) {
37 if (ways_to_eiw(iw, &eiw))
39 hpa &= GENMASK_ULL(51, eiw + ig);
40 n |= do_div(hpa, 3) << i;
45 static struct cxl_dport *cxl_hb_xor(struct cxl_root_decoder *cxlrd, int pos)
47 struct cxl_cxims_data *cximsd = cxlrd->platform_data;
48 struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd;
49 struct cxl_decoder *cxld = &cxlsd->cxld;
50 int ig = cxld->interleave_granularity;
51 int iw = cxld->interleave_ways;
55 if (dev_WARN_ONCE(&cxld->dev,
56 cxld->interleave_ways != cxlsd->nr_targets,
57 "misconfigured root decoder\n"))
60 hpa = cxlrd->res->start + pos * ig;
62 /* Entry (n) is 0 for no interleave (iw == 1) */
64 n = cxl_xor_calc_n(hpa, cximsd, iw, ig);
69 return cxlrd->cxlsd.target[n];
72 struct cxl_cxims_context {
74 struct cxl_root_decoder *cxlrd;
77 static int cxl_parse_cxims(union acpi_subtable_headers *header, void *arg,
78 const unsigned long end)
80 struct acpi_cedt_cxims *cxims = (struct acpi_cedt_cxims *)header;
81 struct cxl_cxims_context *ctx = arg;
82 struct cxl_root_decoder *cxlrd = ctx->cxlrd;
83 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
84 struct device *dev = ctx->dev;
85 struct cxl_cxims_data *cximsd;
86 unsigned int hbig, nr_maps;
89 rc = eig_to_granularity(cxims->hbig, &hbig);
93 /* Does this CXIMS entry apply to the given CXL Window? */
94 if (hbig != cxld->interleave_granularity)
97 /* IW 1,3 do not use xormaps and skip this parsing entirely */
98 if (is_power_of_2(cxld->interleave_ways))
100 nr_maps = ilog2(cxld->interleave_ways);
103 nr_maps = ilog2(cxld->interleave_ways / 3);
105 if (cxims->nr_xormaps < nr_maps) {
106 dev_dbg(dev, "CXIMS nr_xormaps[%d] expected[%d]\n",
107 cxims->nr_xormaps, nr_maps);
111 cximsd = devm_kzalloc(dev, struct_size(cximsd, xormaps, nr_maps),
115 cximsd->nr_maps = nr_maps;
116 memcpy(cximsd->xormaps, cxims->xormap_list,
117 nr_maps * sizeof(*cximsd->xormaps));
118 cxlrd->platform_data = cximsd;
123 static unsigned long cfmws_to_decoder_flags(int restrictions)
125 unsigned long flags = CXL_DECODER_F_ENABLE;
127 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2)
128 flags |= CXL_DECODER_F_TYPE2;
129 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3)
130 flags |= CXL_DECODER_F_TYPE3;
131 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE)
132 flags |= CXL_DECODER_F_RAM;
133 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM)
134 flags |= CXL_DECODER_F_PMEM;
135 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED)
136 flags |= CXL_DECODER_F_LOCK;
141 static int cxl_acpi_cfmws_verify(struct device *dev,
142 struct acpi_cedt_cfmws *cfmws)
144 int rc, expected_len;
147 if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO &&
148 cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
149 dev_err(dev, "CFMWS Unknown Interleave Arithmetic: %d\n",
150 cfmws->interleave_arithmetic);
154 if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) {
155 dev_err(dev, "CFMWS Base HPA not 256MB aligned\n");
159 if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) {
160 dev_err(dev, "CFMWS Window Size not 256MB aligned\n");
164 rc = eiw_to_ways(cfmws->interleave_ways, &ways);
166 dev_err(dev, "CFMWS Interleave Ways (%d) invalid\n",
167 cfmws->interleave_ways);
171 expected_len = struct_size(cfmws, interleave_targets, ways);
173 if (cfmws->header.length < expected_len) {
174 dev_err(dev, "CFMWS length %d less than expected %d\n",
175 cfmws->header.length, expected_len);
179 if (cfmws->header.length > expected_len)
180 dev_dbg(dev, "CFMWS length %d greater than expected %d\n",
181 cfmws->header.length, expected_len);
187 * Note, @dev must be the first member, see 'struct cxl_chbs_context'
188 * and mock_acpi_table_parse_cedt()
190 struct cxl_cfmws_context {
192 struct cxl_port *root_port;
193 struct resource *cxl_res;
197 static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
198 const unsigned long end)
200 int target_map[CXL_DECODER_MAX_INTERLEAVE];
201 struct cxl_cfmws_context *ctx = arg;
202 struct cxl_port *root_port = ctx->root_port;
203 struct resource *cxl_res = ctx->cxl_res;
204 struct cxl_cxims_context cxims_ctx;
205 struct cxl_root_decoder *cxlrd;
206 struct device *dev = ctx->dev;
207 struct acpi_cedt_cfmws *cfmws;
208 cxl_calc_hb_fn cxl_calc_hb;
209 struct cxl_decoder *cxld;
210 unsigned int ways, i, ig;
211 struct resource *res;
214 cfmws = (struct acpi_cedt_cfmws *) header;
216 rc = cxl_acpi_cfmws_verify(dev, cfmws);
218 dev_err(dev, "CFMWS range %#llx-%#llx not registered\n",
220 cfmws->base_hpa + cfmws->window_size - 1);
224 rc = eiw_to_ways(cfmws->interleave_ways, &ways);
227 rc = eig_to_granularity(cfmws->granularity, &ig);
230 for (i = 0; i < ways; i++)
231 target_map[i] = cfmws->interleave_targets[i];
233 res = kzalloc(sizeof(*res), GFP_KERNEL);
237 res->name = kasprintf(GFP_KERNEL, "CXL Window %d", ctx->id++);
241 res->start = cfmws->base_hpa;
242 res->end = cfmws->base_hpa + cfmws->window_size - 1;
243 res->flags = IORESOURCE_MEM;
245 /* add to the local resource tracking to establish a sort order */
246 rc = insert_resource(cxl_res, res);
250 if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_MODULO)
251 cxl_calc_hb = cxl_hb_modulo;
253 cxl_calc_hb = cxl_hb_xor;
255 cxlrd = cxl_root_decoder_alloc(root_port, ways, cxl_calc_hb);
259 cxld = &cxlrd->cxlsd.cxld;
260 cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
261 cxld->target_type = CXL_DECODER_HOSTONLYMEM;
262 cxld->hpa_range = (struct range) {
266 cxld->interleave_ways = ways;
268 * Minimize the x1 granularity to advertise support for any
269 * valid region granularity
272 ig = CXL_DECODER_MIN_GRANULARITY;
273 cxld->interleave_granularity = ig;
275 if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
276 if (ways != 1 && ways != 3) {
277 cxims_ctx = (struct cxl_cxims_context) {
281 rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CXIMS,
282 cxl_parse_cxims, &cxims_ctx);
285 if (!cxlrd->platform_data) {
286 dev_err(dev, "No CXIMS for HBIG %u\n", ig);
293 cxlrd->qos_class = cfmws->qtg_id;
295 rc = cxl_decoder_add(cxld, target_map);
298 put_device(&cxld->dev);
300 rc = cxl_decoder_autoremove(dev, cxld);
302 dev_err(dev, "Failed to add decode range: %pr", res);
305 dev_dbg(dev, "add: %s node: %d range [%#llx - %#llx]\n",
306 dev_name(&cxld->dev),
307 phys_to_target_node(cxld->hpa_range.start),
308 cxld->hpa_range.start, cxld->hpa_range.end);
319 __mock struct acpi_device *to_cxl_host_bridge(struct device *host,
322 struct acpi_device *adev = to_acpi_device(dev);
324 if (!acpi_pci_find_root(adev->handle))
327 if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0)
332 /* Note, @dev is used by mock_acpi_table_parse_cedt() */
333 struct cxl_chbs_context {
335 unsigned long long uid;
336 resource_size_t base;
340 static int cxl_get_chbs_iter(union acpi_subtable_headers *header, void *arg,
341 const unsigned long end)
343 struct cxl_chbs_context *ctx = arg;
344 struct acpi_cedt_chbs *chbs;
346 if (ctx->base != CXL_RESOURCE_NONE)
349 chbs = (struct acpi_cedt_chbs *) header;
351 if (ctx->uid != chbs->uid)
354 ctx->cxl_version = chbs->cxl_version;
358 if (chbs->cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11 &&
359 chbs->length != CXL_RCRB_SIZE)
362 ctx->base = chbs->base;
367 static int cxl_get_chbs(struct device *dev, struct acpi_device *hb,
368 struct cxl_chbs_context *ctx)
370 unsigned long long uid;
373 rc = acpi_evaluate_integer(hb->handle, METHOD_NAME__UID, NULL, &uid);
375 dev_err(dev, "unable to retrieve _UID\n");
379 dev_dbg(dev, "UID found: %lld\n", uid);
380 *ctx = (struct cxl_chbs_context) {
383 .base = CXL_RESOURCE_NONE,
384 .cxl_version = UINT_MAX,
387 acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbs_iter, ctx);
392 static int add_host_bridge_dport(struct device *match, void *arg)
395 struct device *bridge;
396 struct cxl_dport *dport;
397 struct cxl_chbs_context ctx;
398 struct acpi_pci_root *pci_root;
399 struct cxl_port *root_port = arg;
400 struct device *host = root_port->dev.parent;
401 struct acpi_device *hb = to_cxl_host_bridge(host, match);
406 rc = cxl_get_chbs(match, hb, &ctx);
410 if (ctx.cxl_version == UINT_MAX) {
411 dev_warn(match, "No CHBS found for Host Bridge (UID %lld)\n",
416 if (ctx.base == CXL_RESOURCE_NONE) {
417 dev_warn(match, "CHBS invalid for Host Bridge (UID %lld)\n",
422 pci_root = acpi_pci_find_root(hb->handle);
423 bridge = pci_root->bus->bridge;
426 * In RCH mode, bind the component regs base to the dport. In
427 * VH mode it will be bound to the CXL host bridge's port
428 * object later in add_host_bridge_uport().
430 if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
431 dev_dbg(match, "RCRB found for UID %lld: %pa\n", ctx.uid,
433 dport = devm_cxl_add_rch_dport(root_port, bridge, ctx.uid,
436 dport = devm_cxl_add_dport(root_port, bridge, ctx.uid,
441 return PTR_ERR(dport);
447 * A host bridge is a dport to a CFMWS decode and it is a uport to the
448 * dport (PCIe Root Ports) in the host bridge.
450 static int add_host_bridge_uport(struct device *match, void *arg)
452 struct cxl_port *root_port = arg;
453 struct device *host = root_port->dev.parent;
454 struct acpi_device *hb = to_cxl_host_bridge(host, match);
455 struct acpi_pci_root *pci_root;
456 struct cxl_dport *dport;
457 struct cxl_port *port;
458 struct device *bridge;
459 struct cxl_chbs_context ctx;
460 resource_size_t component_reg_phys;
466 pci_root = acpi_pci_find_root(hb->handle);
467 bridge = pci_root->bus->bridge;
468 dport = cxl_find_dport_by_dev(root_port, bridge);
470 dev_dbg(host, "host bridge expected and not found\n");
475 dev_info(bridge, "host supports CXL (restricted)\n");
479 rc = cxl_get_chbs(match, hb, &ctx);
483 if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
485 "CXL CHBS version mismatch, skip port registration\n");
489 component_reg_phys = ctx.base;
490 if (component_reg_phys != CXL_RESOURCE_NONE)
491 dev_dbg(match, "CHBCR found for UID %lld: %pa\n",
492 ctx.uid, &component_reg_phys);
494 rc = devm_cxl_register_pci_bus(host, bridge, pci_root->bus);
498 port = devm_cxl_add_port(host, bridge, component_reg_phys, dport);
500 return PTR_ERR(port);
502 dev_info(bridge, "host supports CXL\n");
507 static int add_root_nvdimm_bridge(struct device *match, void *data)
509 struct cxl_decoder *cxld;
510 struct cxl_port *root_port = data;
511 struct cxl_nvdimm_bridge *cxl_nvb;
512 struct device *host = root_port->dev.parent;
514 if (!is_root_decoder(match))
517 cxld = to_cxl_decoder(match);
518 if (!(cxld->flags & CXL_DECODER_F_PMEM))
521 cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port);
522 if (IS_ERR(cxl_nvb)) {
523 dev_dbg(host, "failed to register pmem\n");
524 return PTR_ERR(cxl_nvb);
526 dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev),
527 dev_name(&cxl_nvb->dev));
531 static struct lock_class_key cxl_root_key;
533 static void cxl_acpi_lock_reset_class(void *dev)
535 device_lock_reset_class(dev);
538 static void del_cxl_resource(struct resource *res)
544 static void cxl_set_public_resource(struct resource *priv, struct resource *pub)
546 priv->desc = (unsigned long) pub;
549 static struct resource *cxl_get_public_resource(struct resource *priv)
551 return (struct resource *) priv->desc;
554 static void remove_cxl_resources(void *data)
556 struct resource *res, *next, *cxl = data;
558 for (res = cxl->child; res; res = next) {
559 struct resource *victim = cxl_get_public_resource(res);
562 remove_resource(res);
565 remove_resource(victim);
569 del_cxl_resource(res);
574 * add_cxl_resources() - reflect CXL fixed memory windows in iomem_resource
575 * @cxl_res: A standalone resource tree where each CXL window is a sibling
577 * Walk each CXL window in @cxl_res and add it to iomem_resource potentially
578 * expanding its boundaries to ensure that any conflicting resources become
579 * children. If a window is expanded it may then conflict with a another window
580 * entry and require the window to be truncated or trimmed. Consider this
583 * |-- "CXL Window 0" --||----- "CXL Window 1" -----|
584 * |--------------- "System RAM" -------------|
586 * ...where platform firmware has established as System RAM resource across 2
587 * windows, but has left some portion of window 1 for dynamic CXL region
588 * provisioning. In this case "Window 0" will span the entirety of the "System
589 * RAM" span, and "CXL Window 1" is truncated to the remaining tail past the end
590 * of that "System RAM" resource.
592 static int add_cxl_resources(struct resource *cxl_res)
594 struct resource *res, *new, *next;
596 for (res = cxl_res->child; res; res = next) {
597 new = kzalloc(sizeof(*new), GFP_KERNEL);
600 new->name = res->name;
601 new->start = res->start;
603 new->flags = IORESOURCE_MEM;
604 new->desc = IORES_DESC_CXL;
607 * Record the public resource in the private cxl_res tree for
610 cxl_set_public_resource(res, new);
612 insert_resource_expand_to_fit(&iomem_resource, new);
615 while (next && resource_overlaps(new, next)) {
616 if (resource_contains(new, next)) {
617 struct resource *_next = next->sibling;
619 remove_resource(next);
620 del_cxl_resource(next);
623 next->start = new->end + 1;
629 static int pair_cxl_resource(struct device *dev, void *data)
631 struct resource *cxl_res = data;
634 if (!is_root_decoder(dev))
637 for (p = cxl_res->child; p; p = p->sibling) {
638 struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev);
639 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
640 struct resource res = {
641 .start = cxld->hpa_range.start,
642 .end = cxld->hpa_range.end,
643 .flags = IORESOURCE_MEM,
646 if (resource_contains(p, &res)) {
647 cxlrd->res = cxl_get_public_resource(p);
655 static int cxl_acpi_probe(struct platform_device *pdev)
658 struct resource *cxl_res;
659 struct cxl_port *root_port;
660 struct device *host = &pdev->dev;
661 struct acpi_device *adev = ACPI_COMPANION(host);
662 struct cxl_cfmws_context ctx;
664 device_lock_set_class(&pdev->dev, &cxl_root_key);
665 rc = devm_add_action_or_reset(&pdev->dev, cxl_acpi_lock_reset_class,
670 cxl_res = devm_kzalloc(host, sizeof(*cxl_res), GFP_KERNEL);
673 cxl_res->name = "CXL mem";
676 cxl_res->flags = IORESOURCE_MEM;
678 root_port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);
679 if (IS_ERR(root_port))
680 return PTR_ERR(root_port);
682 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
683 add_host_bridge_dport);
687 rc = devm_add_action_or_reset(host, remove_cxl_resources, cxl_res);
691 ctx = (struct cxl_cfmws_context) {
693 .root_port = root_port,
696 rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx);
700 rc = add_cxl_resources(cxl_res);
705 * Populate the root decoders with their related iomem resource,
708 device_for_each_child(&root_port->dev, cxl_res, pair_cxl_resource);
711 * Root level scanned with host-bridge as dports, now scan host-bridges
712 * for their role as CXL uports to their CXL-capable PCIe Root Ports.
714 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
715 add_host_bridge_uport);
719 if (IS_ENABLED(CONFIG_CXL_PMEM))
720 rc = device_for_each_child(&root_port->dev, root_port,
721 add_root_nvdimm_bridge);
725 /* In case PCI is scanned before ACPI re-trigger memdev attach */
730 static const struct acpi_device_id cxl_acpi_ids[] = {
734 MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids);
736 static const struct platform_device_id cxl_test_ids[] = {
740 MODULE_DEVICE_TABLE(platform, cxl_test_ids);
742 static struct platform_driver cxl_acpi_driver = {
743 .probe = cxl_acpi_probe,
745 .name = KBUILD_MODNAME,
746 .acpi_match_table = cxl_acpi_ids,
748 .id_table = cxl_test_ids,
751 static int __init cxl_acpi_init(void)
753 return platform_driver_register(&cxl_acpi_driver);
756 static void __exit cxl_acpi_exit(void)
758 platform_driver_unregister(&cxl_acpi_driver);
762 /* load before dax_hmem sees 'Soft Reserved' CXL ranges */
763 subsys_initcall(cxl_acpi_init);
764 module_exit(cxl_acpi_exit);
765 MODULE_LICENSE("GPL v2");
766 MODULE_IMPORT_NS(CXL);
767 MODULE_IMPORT_NS(ACPI);