1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright(c) 2021 Intel Corporation. All rights reserved. */
3 #include <linux/platform_device.h>
4 #include <linux/module.h>
5 #include <linux/device.h>
6 #include <linux/kernel.h>
7 #include <linux/acpi.h>
9 #include <linux/node.h>
10 #include <asm/div64.h>
14 #define CXL_RCRB_SIZE SZ_8K
16 struct cxl_cxims_data {
18 u64 xormaps[] __counted_by(nr_maps);
21 static const guid_t acpi_cxl_qtg_id_guid =
22 GUID_INIT(0xF365F9A6, 0xA7DE, 0x4071,
23 0xA6, 0x6A, 0xB4, 0x0C, 0x0B, 0x4F, 0x8E, 0x52);
26 * Find a targets entry (n) in the host bridge interleave list.
27 * CXL Specification 3.0 Table 9-22
29 static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw,
35 /* IW: 2,4,6,8,12,16 begin building 'n' using xormaps */
37 for (i = 0; i < cximsd->nr_maps; i++)
38 n |= (hweight64(hpa & cximsd->xormaps[i]) & 1) << i;
40 /* IW: 3,6,12 add a modulo calculation to 'n' */
41 if (!is_power_of_2(iw)) {
42 if (ways_to_eiw(iw, &eiw))
44 hpa &= GENMASK_ULL(51, eiw + ig);
45 n |= do_div(hpa, 3) << i;
50 static struct cxl_dport *cxl_hb_xor(struct cxl_root_decoder *cxlrd, int pos)
52 struct cxl_cxims_data *cximsd = cxlrd->platform_data;
53 struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd;
54 struct cxl_decoder *cxld = &cxlsd->cxld;
55 int ig = cxld->interleave_granularity;
56 int iw = cxld->interleave_ways;
60 if (dev_WARN_ONCE(&cxld->dev,
61 cxld->interleave_ways != cxlsd->nr_targets,
62 "misconfigured root decoder\n"))
65 hpa = cxlrd->res->start + pos * ig;
67 /* Entry (n) is 0 for no interleave (iw == 1) */
69 n = cxl_xor_calc_n(hpa, cximsd, iw, ig);
74 return cxlrd->cxlsd.target[n];
77 struct cxl_cxims_context {
79 struct cxl_root_decoder *cxlrd;
82 static int cxl_parse_cxims(union acpi_subtable_headers *header, void *arg,
83 const unsigned long end)
85 struct acpi_cedt_cxims *cxims = (struct acpi_cedt_cxims *)header;
86 struct cxl_cxims_context *ctx = arg;
87 struct cxl_root_decoder *cxlrd = ctx->cxlrd;
88 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
89 struct device *dev = ctx->dev;
90 struct cxl_cxims_data *cximsd;
91 unsigned int hbig, nr_maps;
94 rc = eig_to_granularity(cxims->hbig, &hbig);
98 /* Does this CXIMS entry apply to the given CXL Window? */
99 if (hbig != cxld->interleave_granularity)
102 /* IW 1,3 do not use xormaps and skip this parsing entirely */
103 if (is_power_of_2(cxld->interleave_ways))
104 /* 2, 4, 8, 16 way */
105 nr_maps = ilog2(cxld->interleave_ways);
108 nr_maps = ilog2(cxld->interleave_ways / 3);
110 if (cxims->nr_xormaps < nr_maps) {
111 dev_dbg(dev, "CXIMS nr_xormaps[%d] expected[%d]\n",
112 cxims->nr_xormaps, nr_maps);
116 cximsd = devm_kzalloc(dev, struct_size(cximsd, xormaps, nr_maps),
120 cximsd->nr_maps = nr_maps;
121 memcpy(cximsd->xormaps, cxims->xormap_list,
122 nr_maps * sizeof(*cximsd->xormaps));
123 cxlrd->platform_data = cximsd;
128 static unsigned long cfmws_to_decoder_flags(int restrictions)
130 unsigned long flags = CXL_DECODER_F_ENABLE;
132 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2)
133 flags |= CXL_DECODER_F_TYPE2;
134 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3)
135 flags |= CXL_DECODER_F_TYPE3;
136 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE)
137 flags |= CXL_DECODER_F_RAM;
138 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM)
139 flags |= CXL_DECODER_F_PMEM;
140 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED)
141 flags |= CXL_DECODER_F_LOCK;
146 static int cxl_acpi_cfmws_verify(struct device *dev,
147 struct acpi_cedt_cfmws *cfmws)
149 int rc, expected_len;
152 if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO &&
153 cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
154 dev_err(dev, "CFMWS Unknown Interleave Arithmetic: %d\n",
155 cfmws->interleave_arithmetic);
159 if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) {
160 dev_err(dev, "CFMWS Base HPA not 256MB aligned\n");
164 if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) {
165 dev_err(dev, "CFMWS Window Size not 256MB aligned\n");
169 rc = eiw_to_ways(cfmws->interleave_ways, &ways);
171 dev_err(dev, "CFMWS Interleave Ways (%d) invalid\n",
172 cfmws->interleave_ways);
176 expected_len = struct_size(cfmws, interleave_targets, ways);
178 if (cfmws->header.length < expected_len) {
179 dev_err(dev, "CFMWS length %d less than expected %d\n",
180 cfmws->header.length, expected_len);
184 if (cfmws->header.length > expected_len)
185 dev_dbg(dev, "CFMWS length %d greater than expected %d\n",
186 cfmws->header.length, expected_len);
192 * Note, @dev must be the first member, see 'struct cxl_chbs_context'
193 * and mock_acpi_table_parse_cedt()
195 struct cxl_cfmws_context {
197 struct cxl_port *root_port;
198 struct resource *cxl_res;
203 * cxl_acpi_evaluate_qtg_dsm - Retrieve QTG ids via ACPI _DSM
204 * @handle: ACPI handle
205 * @coord: performance access coordinates
206 * @entries: number of QTG IDs to return
207 * @qos_class: int array provided by caller to return QTG IDs
209 * Return: number of QTG IDs returned, or -errno for errors
211 * Issue QTG _DSM with accompanied bandwidth and latency data in order to get
212 * the QTG IDs that are suitable for the performance point in order of most
213 * suitable to least suitable. Write back array of QTG IDs and return the
214 * actual number of QTG IDs written back.
217 cxl_acpi_evaluate_qtg_dsm(acpi_handle handle, struct access_coordinate *coord,
218 int entries, int *qos_class)
220 union acpi_object *out_obj, *out_buf, *obj;
221 union acpi_object in_array[4] = {
222 [0].integer = { ACPI_TYPE_INTEGER, coord->read_latency },
223 [1].integer = { ACPI_TYPE_INTEGER, coord->write_latency },
224 [2].integer = { ACPI_TYPE_INTEGER, coord->read_bandwidth },
225 [3].integer = { ACPI_TYPE_INTEGER, coord->write_bandwidth },
227 union acpi_object in_obj = {
229 .type = ACPI_TYPE_PACKAGE,
231 .elements = in_array,
234 int count, pkg_entries, i;
241 out_obj = acpi_evaluate_dsm(handle, &acpi_cxl_qtg_id_guid, 1, 1, &in_obj);
245 if (out_obj->type != ACPI_TYPE_PACKAGE) {
250 /* Check Max QTG ID */
251 obj = &out_obj->package.elements[0];
252 if (obj->type != ACPI_TYPE_INTEGER) {
257 max_qtg = obj->integer.value;
259 /* It's legal to have 0 QTG entries */
260 pkg_entries = out_obj->package.count;
261 if (pkg_entries <= 1) {
266 /* Retrieve QTG IDs package */
267 obj = &out_obj->package.elements[1];
268 if (obj->type != ACPI_TYPE_PACKAGE) {
273 pkg_entries = obj->package.count;
274 count = min(entries, pkg_entries);
275 for (i = 0; i < count; i++) {
278 out_buf = &obj->package.elements[i];
279 if (out_buf->type != ACPI_TYPE_INTEGER) {
284 qtg_id = out_buf->integer.value;
285 if (qtg_id > max_qtg)
286 pr_warn("QTG ID %u greater than MAX %u\n",
289 qos_class[i] = qtg_id;
298 static int cxl_acpi_qos_class(struct cxl_root *cxl_root,
299 struct access_coordinate *coord, int entries,
302 struct device *dev = cxl_root->port.uport_dev;
305 if (!dev_is_platform(dev))
308 handle = ACPI_HANDLE(dev);
312 return cxl_acpi_evaluate_qtg_dsm(handle, coord, entries, qos_class);
315 static const struct cxl_root_ops acpi_root_ops = {
316 .qos_class = cxl_acpi_qos_class,
319 static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
320 const unsigned long end)
322 int target_map[CXL_DECODER_MAX_INTERLEAVE];
323 struct cxl_cfmws_context *ctx = arg;
324 struct cxl_port *root_port = ctx->root_port;
325 struct resource *cxl_res = ctx->cxl_res;
326 struct cxl_cxims_context cxims_ctx;
327 struct cxl_root_decoder *cxlrd;
328 struct device *dev = ctx->dev;
329 struct acpi_cedt_cfmws *cfmws;
330 cxl_calc_hb_fn cxl_calc_hb;
331 struct cxl_decoder *cxld;
332 unsigned int ways, i, ig;
333 struct resource *res;
336 cfmws = (struct acpi_cedt_cfmws *) header;
338 rc = cxl_acpi_cfmws_verify(dev, cfmws);
340 dev_err(dev, "CFMWS range %#llx-%#llx not registered\n",
342 cfmws->base_hpa + cfmws->window_size - 1);
346 rc = eiw_to_ways(cfmws->interleave_ways, &ways);
349 rc = eig_to_granularity(cfmws->granularity, &ig);
352 for (i = 0; i < ways; i++)
353 target_map[i] = cfmws->interleave_targets[i];
355 res = kzalloc(sizeof(*res), GFP_KERNEL);
359 res->name = kasprintf(GFP_KERNEL, "CXL Window %d", ctx->id++);
363 res->start = cfmws->base_hpa;
364 res->end = cfmws->base_hpa + cfmws->window_size - 1;
365 res->flags = IORESOURCE_MEM;
367 /* add to the local resource tracking to establish a sort order */
368 rc = insert_resource(cxl_res, res);
372 if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_MODULO)
373 cxl_calc_hb = cxl_hb_modulo;
375 cxl_calc_hb = cxl_hb_xor;
377 cxlrd = cxl_root_decoder_alloc(root_port, ways, cxl_calc_hb);
381 cxld = &cxlrd->cxlsd.cxld;
382 cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
383 cxld->target_type = CXL_DECODER_HOSTONLYMEM;
384 cxld->hpa_range = (struct range) {
388 cxld->interleave_ways = ways;
390 * Minimize the x1 granularity to advertise support for any
391 * valid region granularity
394 ig = CXL_DECODER_MIN_GRANULARITY;
395 cxld->interleave_granularity = ig;
397 if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
398 if (ways != 1 && ways != 3) {
399 cxims_ctx = (struct cxl_cxims_context) {
403 rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CXIMS,
404 cxl_parse_cxims, &cxims_ctx);
407 if (!cxlrd->platform_data) {
408 dev_err(dev, "No CXIMS for HBIG %u\n", ig);
415 cxlrd->qos_class = cfmws->qtg_id;
417 rc = cxl_decoder_add(cxld, target_map);
420 put_device(&cxld->dev);
422 rc = cxl_decoder_autoremove(dev, cxld);
424 dev_err(dev, "Failed to add decode range: %pr", res);
427 dev_dbg(dev, "add: %s node: %d range [%#llx - %#llx]\n",
428 dev_name(&cxld->dev),
429 phys_to_target_node(cxld->hpa_range.start),
430 cxld->hpa_range.start, cxld->hpa_range.end);
441 __mock struct acpi_device *to_cxl_host_bridge(struct device *host,
444 struct acpi_device *adev = to_acpi_device(dev);
446 if (!acpi_pci_find_root(adev->handle))
449 if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0)
454 /* Note, @dev is used by mock_acpi_table_parse_cedt() */
455 struct cxl_chbs_context {
457 unsigned long long uid;
458 resource_size_t base;
462 static int cxl_get_chbs_iter(union acpi_subtable_headers *header, void *arg,
463 const unsigned long end)
465 struct cxl_chbs_context *ctx = arg;
466 struct acpi_cedt_chbs *chbs;
468 if (ctx->base != CXL_RESOURCE_NONE)
471 chbs = (struct acpi_cedt_chbs *) header;
473 if (ctx->uid != chbs->uid)
476 ctx->cxl_version = chbs->cxl_version;
480 if (chbs->cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11 &&
481 chbs->length != CXL_RCRB_SIZE)
484 ctx->base = chbs->base;
489 static int cxl_get_chbs(struct device *dev, struct acpi_device *hb,
490 struct cxl_chbs_context *ctx)
492 unsigned long long uid;
495 rc = acpi_evaluate_integer(hb->handle, METHOD_NAME__UID, NULL, &uid);
497 dev_err(dev, "unable to retrieve _UID\n");
501 dev_dbg(dev, "UID found: %lld\n", uid);
502 *ctx = (struct cxl_chbs_context) {
505 .base = CXL_RESOURCE_NONE,
506 .cxl_version = UINT_MAX,
509 acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbs_iter, ctx);
514 static int get_genport_coordinates(struct device *dev, struct cxl_dport *dport)
516 struct acpi_device *hb = to_cxl_host_bridge(NULL, dev);
520 if (kstrtou32(acpi_device_uid(hb), 0, &uid))
523 rc = acpi_get_genport_coordinates(uid, &dport->hb_coord);
527 /* Adjust back to picoseconds from nanoseconds */
528 dport->hb_coord.read_latency *= 1000;
529 dport->hb_coord.write_latency *= 1000;
534 static int add_host_bridge_dport(struct device *match, void *arg)
538 struct device *bridge;
539 struct cxl_dport *dport;
540 struct cxl_chbs_context ctx;
541 struct acpi_pci_root *pci_root;
542 struct cxl_port *root_port = arg;
543 struct device *host = root_port->dev.parent;
544 struct acpi_device *hb = to_cxl_host_bridge(host, match);
549 rc = cxl_get_chbs(match, hb, &ctx);
553 if (ctx.cxl_version == UINT_MAX) {
554 dev_warn(match, "No CHBS found for Host Bridge (UID %lld)\n",
559 if (ctx.base == CXL_RESOURCE_NONE) {
560 dev_warn(match, "CHBS invalid for Host Bridge (UID %lld)\n",
565 pci_root = acpi_pci_find_root(hb->handle);
566 bridge = pci_root->bus->bridge;
569 * In RCH mode, bind the component regs base to the dport. In
570 * VH mode it will be bound to the CXL host bridge's port
571 * object later in add_host_bridge_uport().
573 if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
574 dev_dbg(match, "RCRB found for UID %lld: %pa\n", ctx.uid,
576 dport = devm_cxl_add_rch_dport(root_port, bridge, ctx.uid,
579 dport = devm_cxl_add_dport(root_port, bridge, ctx.uid,
584 return PTR_ERR(dport);
586 ret = get_genport_coordinates(match, dport);
588 dev_dbg(match, "Failed to get generic port perf coordinates.\n");
594 * A host bridge is a dport to a CFMWS decode and it is a uport to the
595 * dport (PCIe Root Ports) in the host bridge.
597 static int add_host_bridge_uport(struct device *match, void *arg)
599 struct cxl_port *root_port = arg;
600 struct device *host = root_port->dev.parent;
601 struct acpi_device *hb = to_cxl_host_bridge(host, match);
602 struct acpi_pci_root *pci_root;
603 struct cxl_dport *dport;
604 struct cxl_port *port;
605 struct device *bridge;
606 struct cxl_chbs_context ctx;
607 resource_size_t component_reg_phys;
613 pci_root = acpi_pci_find_root(hb->handle);
614 bridge = pci_root->bus->bridge;
615 dport = cxl_find_dport_by_dev(root_port, bridge);
617 dev_dbg(host, "host bridge expected and not found\n");
622 dev_info(bridge, "host supports CXL (restricted)\n");
626 rc = cxl_get_chbs(match, hb, &ctx);
630 if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
632 "CXL CHBS version mismatch, skip port registration\n");
636 component_reg_phys = ctx.base;
637 if (component_reg_phys != CXL_RESOURCE_NONE)
638 dev_dbg(match, "CHBCR found for UID %lld: %pa\n",
639 ctx.uid, &component_reg_phys);
641 rc = devm_cxl_register_pci_bus(host, bridge, pci_root->bus);
645 port = devm_cxl_add_port(host, bridge, component_reg_phys, dport);
647 return PTR_ERR(port);
649 dev_info(bridge, "host supports CXL\n");
654 static int add_root_nvdimm_bridge(struct device *match, void *data)
656 struct cxl_decoder *cxld;
657 struct cxl_port *root_port = data;
658 struct cxl_nvdimm_bridge *cxl_nvb;
659 struct device *host = root_port->dev.parent;
661 if (!is_root_decoder(match))
664 cxld = to_cxl_decoder(match);
665 if (!(cxld->flags & CXL_DECODER_F_PMEM))
668 cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port);
669 if (IS_ERR(cxl_nvb)) {
670 dev_dbg(host, "failed to register pmem\n");
671 return PTR_ERR(cxl_nvb);
673 dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev),
674 dev_name(&cxl_nvb->dev));
678 static struct lock_class_key cxl_root_key;
680 static void cxl_acpi_lock_reset_class(void *dev)
682 device_lock_reset_class(dev);
685 static void del_cxl_resource(struct resource *res)
691 static void cxl_set_public_resource(struct resource *priv, struct resource *pub)
693 priv->desc = (unsigned long) pub;
696 static struct resource *cxl_get_public_resource(struct resource *priv)
698 return (struct resource *) priv->desc;
701 static void remove_cxl_resources(void *data)
703 struct resource *res, *next, *cxl = data;
705 for (res = cxl->child; res; res = next) {
706 struct resource *victim = cxl_get_public_resource(res);
709 remove_resource(res);
712 remove_resource(victim);
716 del_cxl_resource(res);
721 * add_cxl_resources() - reflect CXL fixed memory windows in iomem_resource
722 * @cxl_res: A standalone resource tree where each CXL window is a sibling
724 * Walk each CXL window in @cxl_res and add it to iomem_resource potentially
725 * expanding its boundaries to ensure that any conflicting resources become
726 * children. If a window is expanded it may then conflict with a another window
727 * entry and require the window to be truncated or trimmed. Consider this
730 * |-- "CXL Window 0" --||----- "CXL Window 1" -----|
731 * |--------------- "System RAM" -------------|
733 * ...where platform firmware has established as System RAM resource across 2
734 * windows, but has left some portion of window 1 for dynamic CXL region
735 * provisioning. In this case "Window 0" will span the entirety of the "System
736 * RAM" span, and "CXL Window 1" is truncated to the remaining tail past the end
737 * of that "System RAM" resource.
739 static int add_cxl_resources(struct resource *cxl_res)
741 struct resource *res, *new, *next;
743 for (res = cxl_res->child; res; res = next) {
744 new = kzalloc(sizeof(*new), GFP_KERNEL);
747 new->name = res->name;
748 new->start = res->start;
750 new->flags = IORESOURCE_MEM;
751 new->desc = IORES_DESC_CXL;
754 * Record the public resource in the private cxl_res tree for
757 cxl_set_public_resource(res, new);
759 insert_resource_expand_to_fit(&iomem_resource, new);
762 while (next && resource_overlaps(new, next)) {
763 if (resource_contains(new, next)) {
764 struct resource *_next = next->sibling;
766 remove_resource(next);
767 del_cxl_resource(next);
770 next->start = new->end + 1;
776 static int pair_cxl_resource(struct device *dev, void *data)
778 struct resource *cxl_res = data;
781 if (!is_root_decoder(dev))
784 for (p = cxl_res->child; p; p = p->sibling) {
785 struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev);
786 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
787 struct resource res = {
788 .start = cxld->hpa_range.start,
789 .end = cxld->hpa_range.end,
790 .flags = IORESOURCE_MEM,
793 if (resource_contains(p, &res)) {
794 cxlrd->res = cxl_get_public_resource(p);
802 static int cxl_acpi_probe(struct platform_device *pdev)
805 struct resource *cxl_res;
806 struct cxl_root *cxl_root;
807 struct cxl_port *root_port;
808 struct device *host = &pdev->dev;
809 struct acpi_device *adev = ACPI_COMPANION(host);
810 struct cxl_cfmws_context ctx;
812 device_lock_set_class(&pdev->dev, &cxl_root_key);
813 rc = devm_add_action_or_reset(&pdev->dev, cxl_acpi_lock_reset_class,
818 cxl_res = devm_kzalloc(host, sizeof(*cxl_res), GFP_KERNEL);
821 cxl_res->name = "CXL mem";
824 cxl_res->flags = IORESOURCE_MEM;
826 cxl_root = devm_cxl_add_root(host, &acpi_root_ops);
827 if (IS_ERR(cxl_root))
828 return PTR_ERR(cxl_root);
829 root_port = &cxl_root->port;
831 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
832 add_host_bridge_dport);
836 rc = devm_add_action_or_reset(host, remove_cxl_resources, cxl_res);
840 ctx = (struct cxl_cfmws_context) {
842 .root_port = root_port,
845 rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx);
849 rc = add_cxl_resources(cxl_res);
854 * Populate the root decoders with their related iomem resource,
857 device_for_each_child(&root_port->dev, cxl_res, pair_cxl_resource);
860 * Root level scanned with host-bridge as dports, now scan host-bridges
861 * for their role as CXL uports to their CXL-capable PCIe Root Ports.
863 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
864 add_host_bridge_uport);
868 if (IS_ENABLED(CONFIG_CXL_PMEM))
869 rc = device_for_each_child(&root_port->dev, root_port,
870 add_root_nvdimm_bridge);
874 /* In case PCI is scanned before ACPI re-trigger memdev attach */
879 static const struct acpi_device_id cxl_acpi_ids[] = {
883 MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids);
885 static const struct platform_device_id cxl_test_ids[] = {
889 MODULE_DEVICE_TABLE(platform, cxl_test_ids);
891 static struct platform_driver cxl_acpi_driver = {
892 .probe = cxl_acpi_probe,
894 .name = KBUILD_MODNAME,
895 .acpi_match_table = cxl_acpi_ids,
897 .id_table = cxl_test_ids,
900 static int __init cxl_acpi_init(void)
902 return platform_driver_register(&cxl_acpi_driver);
905 static void __exit cxl_acpi_exit(void)
907 platform_driver_unregister(&cxl_acpi_driver);
911 /* load before dax_hmem sees 'Soft Reserved' CXL ranges */
912 subsys_initcall(cxl_acpi_init);
913 module_exit(cxl_acpi_exit);
914 MODULE_LICENSE("GPL v2");
915 MODULE_IMPORT_NS(CXL);
916 MODULE_IMPORT_NS(ACPI);