drivers/crypto/stm32/stm32_crc32.c

   1 /*
   2  * Copyright (C) STMicroelectronics SA 2017
   3  * Author: Fabien Dessenne <fabien.dessenne@st.com>
   4  * License terms:  GNU General Public License (GPL), version 2
   5  */
   6
   7 #include <linux/bitrev.h>
   8 #include <linux/clk.h>
   9 #include <linux/module.h>
  10 #include <linux/mod_devicetable.h>
  11 #include <linux/platform_device.h>
  12
  13 #include <crypto/internal/hash.h>
  14
  15 #include <asm/unaligned.h>
  16
  17 #define DRIVER_NAME             "stm32-crc32"
  18 #define CHKSUM_DIGEST_SIZE      4
  19 #define CHKSUM_BLOCK_SIZE       1
  20
  21 /* Registers */
  22 #define CRC_DR                  0x00000000
  23 #define CRC_CR                  0x00000008
  24 #define CRC_INIT                0x00000010
  25 #define CRC_POL                 0x00000014
  26
  27 /* Registers values */
  28 #define CRC_CR_RESET            BIT(0)
  29 #define CRC_CR_REVERSE          (BIT(7) | BIT(6) | BIT(5))
  30 #define CRC_INIT_DEFAULT        0xFFFFFFFF
  31
  32 /* Polynomial reversed */
  33 #define POLY_CRC32              0xEDB88320
  34 #define POLY_CRC32C             0x82F63B78
  35
  36 struct stm32_crc {
  37         struct list_head list;
  38         struct device    *dev;
  39         void __iomem     *regs;
  40         struct clk       *clk;
  41         u8               pending_data[sizeof(u32)];
  42         size_t           nb_pending_bytes;
  43 };
  44
  45 struct stm32_crc_list {
  46         struct list_head dev_list;
  47         spinlock_t       lock; /* protect dev_list */
  48 };
  49
  50 static struct stm32_crc_list crc_list = {
  51         .dev_list = LIST_HEAD_INIT(crc_list.dev_list),
  52         .lock     = __SPIN_LOCK_UNLOCKED(crc_list.lock),
  53 };
  54
  55 struct stm32_crc_ctx {
  56         u32 key;
  57         u32 poly;
  58 };
  59
  60 struct stm32_crc_desc_ctx {
  61         u32    partial; /* crc32c: partial in first 4 bytes of that struct */
  62         struct stm32_crc *crc;
  63 };
  64
  65 static int stm32_crc32_cra_init(struct crypto_tfm *tfm)
  66 {
  67         struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
  68
  69         mctx->key = CRC_INIT_DEFAULT;
  70         mctx->poly = POLY_CRC32;
  71         return 0;
  72 }
  73
  74 static int stm32_crc32c_cra_init(struct crypto_tfm *tfm)
  75 {
  76         struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
  77
  78         mctx->key = CRC_INIT_DEFAULT;
  79         mctx->poly = POLY_CRC32C;
  80         return 0;
  81 }
  82
  83 static int stm32_crc_setkey(struct crypto_shash *tfm, const u8 *key,
  84                             unsigned int keylen)
  85 {
  86         struct stm32_crc_ctx *mctx = crypto_shash_ctx(tfm);
  87
  88         if (keylen != sizeof(u32)) {
  89                 crypto_shash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
  90                 return -EINVAL;
  91         }
  92
  93         mctx->key = get_unaligned_le32(key);
  94         return 0;
  95 }
  96
  97 static int stm32_crc_init(struct shash_desc *desc)
  98 {
  99         struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
 100         struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
 101         struct stm32_crc *crc;
 102
 103         spin_lock_bh(&crc_list.lock);
 104         list_for_each_entry(crc, &crc_list.dev_list, list) {
 105                 ctx->crc = crc;
 106                 break;
 107         }
 108         spin_unlock_bh(&crc_list.lock);
 109
 110         /* Reset, set key, poly and configure in bit reverse mode */
 111         writel_relaxed(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
 112         writel_relaxed(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
 113         writel_relaxed(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
 114
 115         /* Store partial result */
 116         ctx->partial = readl_relaxed(ctx->crc->regs + CRC_DR);
 117         ctx->crc->nb_pending_bytes = 0;
 118
 119         return 0;
 120 }
 121
 122 static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
 123                             unsigned int length)
 124 {
 125         struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
 126         struct stm32_crc *crc = ctx->crc;
 127         u32 *d32;
 128         unsigned int i;
 129
 130         if (unlikely(crc->nb_pending_bytes)) {
 131                 while (crc->nb_pending_bytes != sizeof(u32) && length) {
 132                         /* Fill in pending data */
 133                         crc->pending_data[crc->nb_pending_bytes++] = *(d8++);
 134                         length--;
 135                 }
 136
 137                 if (crc->nb_pending_bytes == sizeof(u32)) {
 138                         /* Process completed pending data */
 139                         writel_relaxed(*(u32 *)crc->pending_data,
 140                                        crc->regs + CRC_DR);
 141                         crc->nb_pending_bytes = 0;
 142                 }
 143         }
 144
 145         d32 = (u32 *)d8;
 146         for (i = 0; i < length >> 2; i++)
 147                 /* Process 32 bits data */
 148                 writel_relaxed(*(d32++), crc->regs + CRC_DR);
 149
 150         /* Store partial result */
 151         ctx->partial = readl_relaxed(crc->regs + CRC_DR);
 152
 153         /* Check for pending data (non 32 bits) */
 154         length &= 3;
 155         if (likely(!length))
 156                 return 0;
 157
 158         if ((crc->nb_pending_bytes + length) >= sizeof(u32)) {
 159                 /* Shall not happen */
 160                 dev_err(crc->dev, "Pending data overflow\n");
 161                 return -EINVAL;
 162         }
 163
 164         d8 = (const u8 *)d32;
 165         for (i = 0; i < length; i++)
 166                 /* Store pending data */
 167                 crc->pending_data[crc->nb_pending_bytes++] = *(d8++);
 168
 169         return 0;
 170 }
 171
 172 static int stm32_crc_final(struct shash_desc *desc, u8 *out)
 173 {
 174         struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
 175         struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
 176
 177         /* Send computed CRC */
 178         put_unaligned_le32(mctx->poly == POLY_CRC32C ?
 179                            ~ctx->partial : ctx->partial, out);
 180
 181         return 0;
 182 }
 183
 184 static int stm32_crc_finup(struct shash_desc *desc, const u8 *data,
 185                            unsigned int length, u8 *out)
 186 {
 187         return stm32_crc_update(desc, data, length) ?:
 188                stm32_crc_final(desc, out);
 189 }
 190
 191 static int stm32_crc_digest(struct shash_desc *desc, const u8 *data,
 192                             unsigned int length, u8 *out)
 193 {
 194         return stm32_crc_init(desc) ?: stm32_crc_finup(desc, data, length, out);
 195 }
 196
 197 static struct shash_alg algs[] = {
 198         /* CRC-32 */
 199         {
 200                 .setkey         = stm32_crc_setkey,
 201                 .init           = stm32_crc_init,
 202                 .update         = stm32_crc_update,
 203                 .final          = stm32_crc_final,
 204                 .finup          = stm32_crc_finup,
 205                 .digest         = stm32_crc_digest,
 206                 .descsize       = sizeof(struct stm32_crc_desc_ctx),
 207                 .digestsize     = CHKSUM_DIGEST_SIZE,
 208                 .base           = {
 209                         .cra_name               = "crc32",
 210                         .cra_driver_name        = DRIVER_NAME,
 211                         .cra_priority           = 200,
 212                         .cra_flags              = CRYPTO_ALG_OPTIONAL_KEY,
 213                         .cra_blocksize          = CHKSUM_BLOCK_SIZE,
 214                         .cra_alignmask          = 3,
 215                         .cra_ctxsize            = sizeof(struct stm32_crc_ctx),
 216                         .cra_module             = THIS_MODULE,
 217                         .cra_init               = stm32_crc32_cra_init,
 218                 }
 219         },
 220         /* CRC-32Castagnoli */
 221         {
 222                 .setkey         = stm32_crc_setkey,
 223                 .init           = stm32_crc_init,
 224                 .update         = stm32_crc_update,
 225                 .final          = stm32_crc_final,
 226                 .finup          = stm32_crc_finup,
 227                 .digest         = stm32_crc_digest,
 228                 .descsize       = sizeof(struct stm32_crc_desc_ctx),
 229                 .digestsize     = CHKSUM_DIGEST_SIZE,
 230                 .base           = {
 231                         .cra_name               = "crc32c",
 232                         .cra_driver_name        = DRIVER_NAME,
 233                         .cra_priority           = 200,
 234                         .cra_flags              = CRYPTO_ALG_OPTIONAL_KEY,
 235                         .cra_blocksize          = CHKSUM_BLOCK_SIZE,
 236                         .cra_alignmask          = 3,
 237                         .cra_ctxsize            = sizeof(struct stm32_crc_ctx),
 238                         .cra_module             = THIS_MODULE,
 239                         .cra_init               = stm32_crc32c_cra_init,
 240                 }
 241         }
 242 };
 243
 244 static int stm32_crc_probe(struct platform_device *pdev)
 245 {
 246         struct device *dev = &pdev->dev;
 247         struct stm32_crc *crc;
 248         struct resource *res;
 249         int ret;
 250
 251         crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
 252         if (!crc)
 253                 return -ENOMEM;
 254
 255         crc->dev = dev;
 256
 257         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 258         crc->regs = devm_ioremap_resource(dev, res);
 259         if (IS_ERR(crc->regs)) {
 260                 dev_err(dev, "Cannot map CRC IO\n");
 261                 return PTR_ERR(crc->regs);
 262         }
 263
 264         crc->clk = devm_clk_get(dev, NULL);
 265         if (IS_ERR(crc->clk)) {
 266                 dev_err(dev, "Could not get clock\n");
 267                 return PTR_ERR(crc->clk);
 268         }
 269
 270         ret = clk_prepare_enable(crc->clk);
 271         if (ret) {
 272                 dev_err(crc->dev, "Failed to enable clock\n");
 273                 return ret;
 274         }
 275
 276         platform_set_drvdata(pdev, crc);
 277
 278         spin_lock(&crc_list.lock);
 279         list_add(&crc->list, &crc_list.dev_list);
 280         spin_unlock(&crc_list.lock);
 281
 282         ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
 283         if (ret) {
 284                 dev_err(dev, "Failed to register\n");
 285                 clk_disable_unprepare(crc->clk);
 286                 return ret;
 287         }
 288
 289         dev_info(dev, "Initialized\n");
 290
 291         return 0;
 292 }
 293
 294 static int stm32_crc_remove(struct platform_device *pdev)
 295 {
 296         struct stm32_crc *crc = platform_get_drvdata(pdev);
 297
 298         spin_lock(&crc_list.lock);
 299         list_del(&crc->list);
 300         spin_unlock(&crc_list.lock);
 301
 302         crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
 303
 304         clk_disable_unprepare(crc->clk);
 305
 306         return 0;
 307 }
 308
 309 static const struct of_device_id stm32_dt_ids[] = {
 310         { .compatible = "st,stm32f7-crc", },
 311         {},
 312 };
 313 MODULE_DEVICE_TABLE(of, stm32_dt_ids);
 314
 315 static struct platform_driver stm32_crc_driver = {
 316         .probe  = stm32_crc_probe,
 317         .remove = stm32_crc_remove,
 318         .driver = {
 319                 .name           = DRIVER_NAME,
 320                 .of_match_table = stm32_dt_ids,
 321         },
 322 };
 323
 324 module_platform_driver(stm32_crc_driver);
 325
 326 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
 327 MODULE_DESCRIPTION("STMicrolectronics STM32 CRC32 hardware driver");
 328 MODULE_LICENSE("GPL");