4 * Support for OMAP SHA1/MD5 HW acceleration.
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
8 * Copyright (c) 2011 Texas Instruments Incorporated
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
14 * Some ideas are from old omap-sha1-md5.c driver.
17 #define pr_fmt(fmt) "%s: " fmt, __func__
19 #include <linux/err.h>
20 #include <linux/device.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/irq.h>
28 #include <linux/platform_device.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/of_device.h>
35 #include <linux/of_address.h>
36 #include <linux/of_irq.h>
37 #include <linux/delay.h>
38 #include <linux/crypto.h>
39 #include <linux/cryptohash.h>
40 #include <crypto/scatterwalk.h>
41 #include <crypto/algapi.h>
42 #include <crypto/sha.h>
43 #include <crypto/hash.h>
44 #include <crypto/internal/hash.h>
46 #define MD5_DIGEST_SIZE 16
48 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04))
49 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04))
50 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs)
52 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04))
54 #define SHA_REG_CTRL 0x18
55 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5)
56 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4)
57 #define SHA_REG_CTRL_ALGO_CONST (1 << 3)
58 #define SHA_REG_CTRL_ALGO (1 << 2)
59 #define SHA_REG_CTRL_INPUT_READY (1 << 1)
60 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0)
62 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs)
64 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs)
65 #define SHA_REG_MASK_DMA_EN (1 << 3)
66 #define SHA_REG_MASK_IT_EN (1 << 2)
67 #define SHA_REG_MASK_SOFTRESET (1 << 1)
68 #define SHA_REG_AUTOIDLE (1 << 0)
70 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs)
71 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
73 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs)
74 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7)
75 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5)
76 #define SHA_REG_MODE_CLOSE_HASH (1 << 4)
77 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3)
79 #define SHA_REG_MODE_ALGO_MASK (7 << 0)
80 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1)
81 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1)
82 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1)
83 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1)
84 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0)
85 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0)
87 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs)
89 #define SHA_REG_IRQSTATUS 0x118
90 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3)
91 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
92 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1)
93 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0)
95 #define SHA_REG_IRQENA 0x11C
96 #define SHA_REG_IRQENA_CTX_RDY (1 << 3)
97 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2)
98 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1)
99 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0)
101 #define DEFAULT_TIMEOUT_INTERVAL HZ
103 #define DEFAULT_AUTOSUSPEND_DELAY 1000
105 /* mostly device flags */
107 #define FLAGS_FINAL 1
108 #define FLAGS_DMA_ACTIVE 2
109 #define FLAGS_OUTPUT_READY 3
112 #define FLAGS_DMA_READY 6
113 #define FLAGS_AUTO_XOR 7
114 #define FLAGS_BE32_SHA1 8
116 #define FLAGS_FINUP 16
119 #define FLAGS_MODE_SHIFT 18
120 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
121 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
122 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
123 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
124 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
125 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
126 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
128 #define FLAGS_HMAC 21
129 #define FLAGS_ERROR 22
134 #define OMAP_ALIGN_MASK (sizeof(u32)-1)
135 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32))))
137 #define BUFLEN PAGE_SIZE
139 struct omap_sham_dev;
141 struct omap_sham_reqctx {
142 struct omap_sham_dev *dd;
146 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
153 struct scatterlist *sg;
154 struct scatterlist sgl;
155 unsigned int offset; /* offset in current sg */
156 unsigned int total; /* total request */
158 u8 buffer[0] OMAP_ALIGNED;
161 struct omap_sham_hmac_ctx {
162 struct crypto_shash *shash;
163 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
164 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
167 struct omap_sham_ctx {
168 struct omap_sham_dev *dd;
173 struct crypto_shash *fallback;
175 struct omap_sham_hmac_ctx base[0];
178 #define OMAP_SHAM_QUEUE_LENGTH 10
180 struct omap_sham_algs_info {
181 struct ahash_alg *algs_list;
183 unsigned int registered;
186 struct omap_sham_pdata {
187 struct omap_sham_algs_info *algs_info;
188 unsigned int algs_info_size;
192 void (*copy_hash)(struct ahash_request *req, int out);
193 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
195 void (*trigger)(struct omap_sham_dev *dd, size_t length);
196 int (*poll_irq)(struct omap_sham_dev *dd);
197 irqreturn_t (*intr_hdlr)(int irq, void *dev_id);
215 struct omap_sham_dev {
216 struct list_head list;
217 unsigned long phys_base;
219 void __iomem *io_base;
223 struct dma_chan *dma_lch;
224 struct tasklet_struct done_task;
228 struct crypto_queue queue;
229 struct ahash_request *req;
231 const struct omap_sham_pdata *pdata;
234 struct omap_sham_drv {
235 struct list_head dev_list;
240 static struct omap_sham_drv sham = {
241 .dev_list = LIST_HEAD_INIT(sham.dev_list),
242 .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
245 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
247 return __raw_readl(dd->io_base + offset);
250 static inline void omap_sham_write(struct omap_sham_dev *dd,
251 u32 offset, u32 value)
253 __raw_writel(value, dd->io_base + offset);
256 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
261 val = omap_sham_read(dd, address);
264 omap_sham_write(dd, address, val);
267 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
269 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
271 while (!(omap_sham_read(dd, offset) & bit)) {
272 if (time_is_before_jiffies(timeout))
279 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
281 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
282 struct omap_sham_dev *dd = ctx->dd;
283 u32 *hash = (u32 *)ctx->digest;
286 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
288 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
290 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
294 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
296 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
297 struct omap_sham_dev *dd = ctx->dd;
300 if (ctx->flags & BIT(FLAGS_HMAC)) {
301 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
302 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
303 struct omap_sham_hmac_ctx *bctx = tctx->base;
304 u32 *opad = (u32 *)bctx->opad;
306 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
308 opad[i] = omap_sham_read(dd,
309 SHA_REG_ODIGEST(dd, i));
311 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
316 omap_sham_copy_hash_omap2(req, out);
319 static void omap_sham_copy_ready_hash(struct ahash_request *req)
321 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
322 u32 *in = (u32 *)ctx->digest;
323 u32 *hash = (u32 *)req->result;
324 int i, d, big_endian = 0;
329 switch (ctx->flags & FLAGS_MODE_MASK) {
331 d = MD5_DIGEST_SIZE / sizeof(u32);
333 case FLAGS_MODE_SHA1:
334 /* OMAP2 SHA1 is big endian */
335 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
337 d = SHA1_DIGEST_SIZE / sizeof(u32);
339 case FLAGS_MODE_SHA224:
340 d = SHA224_DIGEST_SIZE / sizeof(u32);
342 case FLAGS_MODE_SHA256:
343 d = SHA256_DIGEST_SIZE / sizeof(u32);
345 case FLAGS_MODE_SHA384:
346 d = SHA384_DIGEST_SIZE / sizeof(u32);
348 case FLAGS_MODE_SHA512:
349 d = SHA512_DIGEST_SIZE / sizeof(u32);
356 for (i = 0; i < d; i++)
357 hash[i] = be32_to_cpu(in[i]);
359 for (i = 0; i < d; i++)
360 hash[i] = le32_to_cpu(in[i]);
363 static int omap_sham_hw_init(struct omap_sham_dev *dd)
367 err = pm_runtime_get_sync(dd->dev);
369 dev_err(dd->dev, "failed to get sync: %d\n", err);
373 if (!test_bit(FLAGS_INIT, &dd->flags)) {
374 set_bit(FLAGS_INIT, &dd->flags);
381 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
384 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
385 u32 val = length << 5, mask;
387 if (likely(ctx->digcnt))
388 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
390 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
391 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
392 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
394 * Setting ALGO_CONST only for the first iteration
395 * and CLOSE_HASH only for the last one.
397 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
398 val |= SHA_REG_CTRL_ALGO;
400 val |= SHA_REG_CTRL_ALGO_CONST;
402 val |= SHA_REG_CTRL_CLOSE_HASH;
404 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
405 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
407 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
410 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
414 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
416 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
419 static int get_block_size(struct omap_sham_reqctx *ctx)
423 switch (ctx->flags & FLAGS_MODE_MASK) {
425 case FLAGS_MODE_SHA1:
428 case FLAGS_MODE_SHA224:
429 case FLAGS_MODE_SHA256:
430 d = SHA256_BLOCK_SIZE;
432 case FLAGS_MODE_SHA384:
433 case FLAGS_MODE_SHA512:
434 d = SHA512_BLOCK_SIZE;
443 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
444 u32 *value, int count)
446 for (; count--; value++, offset += 4)
447 omap_sham_write(dd, offset, *value);
450 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
453 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
457 * Setting ALGO_CONST only for the first iteration and
458 * CLOSE_HASH only for the last one. Note that flags mode bits
459 * correspond to algorithm encoding in mode register.
461 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
463 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
464 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
465 struct omap_sham_hmac_ctx *bctx = tctx->base;
468 val |= SHA_REG_MODE_ALGO_CONSTANT;
470 if (ctx->flags & BIT(FLAGS_HMAC)) {
471 bs = get_block_size(ctx);
472 nr_dr = bs / (2 * sizeof(u32));
473 val |= SHA_REG_MODE_HMAC_KEY_PROC;
474 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
475 (u32 *)bctx->ipad, nr_dr);
476 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
477 (u32 *)bctx->ipad + nr_dr, nr_dr);
483 val |= SHA_REG_MODE_CLOSE_HASH;
485 if (ctx->flags & BIT(FLAGS_HMAC))
486 val |= SHA_REG_MODE_HMAC_OUTER_HASH;
489 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
490 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
491 SHA_REG_MODE_HMAC_KEY_PROC;
493 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
494 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
495 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
496 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
498 (dma ? SHA_REG_MASK_DMA_EN : 0),
499 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
502 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
504 omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
507 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
509 return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
510 SHA_REG_IRQSTATUS_INPUT_RDY);
513 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
514 size_t length, int final)
516 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
517 int count, len32, bs32, offset = 0;
518 const u32 *buffer = (const u32 *)buf;
520 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
521 ctx->digcnt, length, final);
523 dd->pdata->write_ctrl(dd, length, final, 0);
524 dd->pdata->trigger(dd, length);
526 /* should be non-zero before next lines to disable clocks later */
527 ctx->digcnt += length;
530 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
532 set_bit(FLAGS_CPU, &dd->flags);
534 len32 = DIV_ROUND_UP(length, sizeof(u32));
535 bs32 = get_block_size(ctx) / sizeof(u32);
538 if (dd->pdata->poll_irq(dd))
541 for (count = 0; count < min(len32, bs32); count++, offset++)
542 omap_sham_write(dd, SHA_REG_DIN(dd, count),
544 len32 -= min(len32, bs32);
550 static void omap_sham_dma_callback(void *param)
552 struct omap_sham_dev *dd = param;
554 set_bit(FLAGS_DMA_READY, &dd->flags);
555 tasklet_schedule(&dd->done_task);
558 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
559 size_t length, int final, int is_sg)
561 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
562 struct dma_async_tx_descriptor *tx;
563 struct dma_slave_config cfg;
564 int len32, ret, dma_min = get_block_size(ctx);
566 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
567 ctx->digcnt, length, final);
569 memset(&cfg, 0, sizeof(cfg));
571 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
572 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
573 cfg.dst_maxburst = dma_min / DMA_SLAVE_BUSWIDTH_4_BYTES;
575 ret = dmaengine_slave_config(dd->dma_lch, &cfg);
577 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
581 len32 = DIV_ROUND_UP(length, dma_min) * dma_min;
585 * The SG entry passed in may not have the 'length' member
586 * set correctly so use a local SG entry (sgl) with the
587 * proper value for 'length' instead. If this is not done,
588 * the dmaengine may try to DMA the incorrect amount of data.
590 sg_init_table(&ctx->sgl, 1);
591 sg_assign_page(&ctx->sgl, sg_page(ctx->sg));
592 ctx->sgl.offset = ctx->sg->offset;
593 sg_dma_len(&ctx->sgl) = len32;
594 sg_dma_address(&ctx->sgl) = sg_dma_address(ctx->sg);
596 tx = dmaengine_prep_slave_sg(dd->dma_lch, &ctx->sgl, 1,
597 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
599 tx = dmaengine_prep_slave_single(dd->dma_lch, dma_addr, len32,
600 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
604 dev_err(dd->dev, "prep_slave_sg/single() failed\n");
608 tx->callback = omap_sham_dma_callback;
609 tx->callback_param = dd;
611 dd->pdata->write_ctrl(dd, length, final, 1);
613 ctx->digcnt += length;
616 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
618 set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
620 dmaengine_submit(tx);
621 dma_async_issue_pending(dd->dma_lch);
623 dd->pdata->trigger(dd, length);
628 static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx,
629 const u8 *data, size_t length)
631 size_t count = min(length, ctx->buflen - ctx->bufcnt);
633 count = min(count, ctx->total);
636 memcpy(ctx->buffer + ctx->bufcnt, data, count);
637 ctx->bufcnt += count;
642 static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
648 vaddr = kmap_atomic(sg_page(ctx->sg));
649 vaddr += ctx->sg->offset;
651 count = omap_sham_append_buffer(ctx,
653 ctx->sg->length - ctx->offset);
655 kunmap_atomic((void *)vaddr);
659 ctx->offset += count;
661 if (ctx->offset == ctx->sg->length) {
662 ctx->sg = sg_next(ctx->sg);
673 static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
674 struct omap_sham_reqctx *ctx,
675 size_t length, int final)
679 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
681 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
682 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
686 ctx->flags &= ~BIT(FLAGS_SG);
688 ret = omap_sham_xmit_dma(dd, ctx->dma_addr, length, final, 0);
689 if (ret != -EINPROGRESS)
690 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
696 static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
698 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
702 omap_sham_append_sg(ctx);
704 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
706 dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
707 ctx->bufcnt, ctx->digcnt, final);
709 if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
712 return omap_sham_xmit_dma_map(dd, ctx, count, final);
718 /* Start address alignment */
719 #define SG_AA(sg) (IS_ALIGNED(sg->offset, sizeof(u32)))
720 /* SHA1 block size alignment */
721 #define SG_SA(sg, bs) (IS_ALIGNED(sg->length, bs))
723 static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
725 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
726 unsigned int length, final, tail;
727 struct scatterlist *sg;
733 if (ctx->bufcnt || ctx->offset)
734 return omap_sham_update_dma_slow(dd);
737 * Don't use the sg interface when the transfer size is less
738 * than the number of elements in a DMA frame. Otherwise,
739 * the dmaengine infrastructure will calculate that it needs
740 * to transfer 0 frames which ultimately fails.
742 if (ctx->total < get_block_size(ctx))
743 return omap_sham_update_dma_slow(dd);
745 dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
746 ctx->digcnt, ctx->bufcnt, ctx->total);
749 bs = get_block_size(ctx);
752 return omap_sham_update_dma_slow(dd);
754 if (!sg_is_last(sg) && !SG_SA(sg, bs))
755 /* size is not BLOCK_SIZE aligned */
756 return omap_sham_update_dma_slow(dd);
758 length = min(ctx->total, sg->length);
760 if (sg_is_last(sg)) {
761 if (!(ctx->flags & BIT(FLAGS_FINUP))) {
762 /* not last sg must be BLOCK_SIZE aligned */
763 tail = length & (bs - 1);
764 /* without finup() we need one block to close hash */
771 if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
772 dev_err(dd->dev, "dma_map_sg error\n");
776 ctx->flags |= BIT(FLAGS_SG);
778 ctx->total -= length;
779 ctx->offset = length; /* offset where to start slow */
781 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
783 ret = omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final, 1);
784 if (ret != -EINPROGRESS)
785 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
790 static int omap_sham_update_cpu(struct omap_sham_dev *dd)
792 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
798 omap_sham_append_sg(ctx);
800 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
802 dev_dbg(dd->dev, "cpu: bufcnt: %u, digcnt: %d, final: %d\n",
803 ctx->bufcnt, ctx->digcnt, final);
805 if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
806 bufcnt = ctx->bufcnt;
808 return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, final);
814 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
816 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
819 if (ctx->flags & BIT(FLAGS_SG)) {
820 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
821 if (ctx->sg->length == ctx->offset) {
822 ctx->sg = sg_next(ctx->sg);
827 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
834 static int omap_sham_init(struct ahash_request *req)
836 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
837 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
838 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
839 struct omap_sham_dev *dd = NULL, *tmp;
842 spin_lock_bh(&sham.lock);
844 list_for_each_entry(tmp, &sham.dev_list, list) {
852 spin_unlock_bh(&sham.lock);
858 dev_dbg(dd->dev, "init: digest size: %d\n",
859 crypto_ahash_digestsize(tfm));
861 switch (crypto_ahash_digestsize(tfm)) {
862 case MD5_DIGEST_SIZE:
863 ctx->flags |= FLAGS_MODE_MD5;
864 bs = SHA1_BLOCK_SIZE;
866 case SHA1_DIGEST_SIZE:
867 ctx->flags |= FLAGS_MODE_SHA1;
868 bs = SHA1_BLOCK_SIZE;
870 case SHA224_DIGEST_SIZE:
871 ctx->flags |= FLAGS_MODE_SHA224;
872 bs = SHA224_BLOCK_SIZE;
874 case SHA256_DIGEST_SIZE:
875 ctx->flags |= FLAGS_MODE_SHA256;
876 bs = SHA256_BLOCK_SIZE;
878 case SHA384_DIGEST_SIZE:
879 ctx->flags |= FLAGS_MODE_SHA384;
880 bs = SHA384_BLOCK_SIZE;
882 case SHA512_DIGEST_SIZE:
883 ctx->flags |= FLAGS_MODE_SHA512;
884 bs = SHA512_BLOCK_SIZE;
890 ctx->buflen = BUFLEN;
892 if (tctx->flags & BIT(FLAGS_HMAC)) {
893 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
894 struct omap_sham_hmac_ctx *bctx = tctx->base;
896 memcpy(ctx->buffer, bctx->ipad, bs);
900 ctx->flags |= BIT(FLAGS_HMAC);
907 static int omap_sham_update_req(struct omap_sham_dev *dd)
909 struct ahash_request *req = dd->req;
910 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
913 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
914 ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
916 if (ctx->flags & BIT(FLAGS_CPU))
917 err = omap_sham_update_cpu(dd);
919 err = omap_sham_update_dma_start(dd);
921 /* wait for dma completion before can take more data */
922 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
927 static int omap_sham_final_req(struct omap_sham_dev *dd)
929 struct ahash_request *req = dd->req;
930 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
931 int err = 0, use_dma = 1;
933 if ((ctx->bufcnt <= get_block_size(ctx)) || dd->polling_mode)
935 * faster to handle last block with cpu or
936 * use cpu when dma is not present.
941 err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1);
943 err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
947 dev_dbg(dd->dev, "final_req: err: %d\n", err);
952 static int omap_sham_finish_hmac(struct ahash_request *req)
954 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
955 struct omap_sham_hmac_ctx *bctx = tctx->base;
956 int bs = crypto_shash_blocksize(bctx->shash);
957 int ds = crypto_shash_digestsize(bctx->shash);
958 SHASH_DESC_ON_STACK(shash, bctx->shash);
960 shash->tfm = bctx->shash;
961 shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
963 return crypto_shash_init(shash) ?:
964 crypto_shash_update(shash, bctx->opad, bs) ?:
965 crypto_shash_finup(shash, req->result, ds, req->result);
968 static int omap_sham_finish(struct ahash_request *req)
970 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
971 struct omap_sham_dev *dd = ctx->dd;
975 omap_sham_copy_ready_hash(req);
976 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
977 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
978 err = omap_sham_finish_hmac(req);
981 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
986 static void omap_sham_finish_req(struct ahash_request *req, int err)
988 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
989 struct omap_sham_dev *dd = ctx->dd;
992 dd->pdata->copy_hash(req, 1);
993 if (test_bit(FLAGS_FINAL, &dd->flags))
994 err = omap_sham_finish(req);
996 ctx->flags |= BIT(FLAGS_ERROR);
999 /* atomic operation is not needed here */
1000 dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1001 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1003 pm_runtime_mark_last_busy(dd->dev);
1004 pm_runtime_put_autosuspend(dd->dev);
1006 if (req->base.complete)
1007 req->base.complete(&req->base, err);
1010 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1011 struct ahash_request *req)
1013 struct crypto_async_request *async_req, *backlog;
1014 struct omap_sham_reqctx *ctx;
1015 unsigned long flags;
1016 int err = 0, ret = 0;
1019 spin_lock_irqsave(&dd->lock, flags);
1021 ret = ahash_enqueue_request(&dd->queue, req);
1022 if (test_bit(FLAGS_BUSY, &dd->flags)) {
1023 spin_unlock_irqrestore(&dd->lock, flags);
1026 backlog = crypto_get_backlog(&dd->queue);
1027 async_req = crypto_dequeue_request(&dd->queue);
1029 set_bit(FLAGS_BUSY, &dd->flags);
1030 spin_unlock_irqrestore(&dd->lock, flags);
1036 backlog->complete(backlog, -EINPROGRESS);
1038 req = ahash_request_cast(async_req);
1040 ctx = ahash_request_ctx(req);
1042 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1043 ctx->op, req->nbytes);
1045 err = omap_sham_hw_init(dd);
1050 /* request has changed - restore hash */
1051 dd->pdata->copy_hash(req, 0);
1053 if (ctx->op == OP_UPDATE) {
1054 err = omap_sham_update_req(dd);
1055 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1056 /* no final() after finup() */
1057 err = omap_sham_final_req(dd);
1058 } else if (ctx->op == OP_FINAL) {
1059 err = omap_sham_final_req(dd);
1062 dev_dbg(dd->dev, "exit, err: %d\n", err);
1064 if (err != -EINPROGRESS) {
1065 /* done_task will not finish it, so do it here */
1066 omap_sham_finish_req(req, err);
1070 * Execute next request immediately if there is anything
1079 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1081 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1082 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1083 struct omap_sham_dev *dd = tctx->dd;
1087 return omap_sham_handle_queue(dd, req);
1090 static int omap_sham_update(struct ahash_request *req)
1092 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1093 struct omap_sham_dev *dd = ctx->dd;
1094 int bs = get_block_size(ctx);
1099 ctx->total = req->nbytes;
1103 if (ctx->flags & BIT(FLAGS_FINUP)) {
1104 if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 240) {
1106 * OMAP HW accel works only with buffers >= 9
1107 * will switch to bypass in final()
1108 * final has the same request and data
1110 omap_sham_append_sg(ctx);
1112 } else if ((ctx->bufcnt + ctx->total <= bs) ||
1115 * faster to use CPU for short transfers or
1116 * use cpu when dma is not present.
1118 ctx->flags |= BIT(FLAGS_CPU);
1120 } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
1121 omap_sham_append_sg(ctx);
1125 if (dd->polling_mode)
1126 ctx->flags |= BIT(FLAGS_CPU);
1128 return omap_sham_enqueue(req, OP_UPDATE);
1131 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1132 const u8 *data, unsigned int len, u8 *out)
1134 SHASH_DESC_ON_STACK(shash, tfm);
1137 shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1139 return crypto_shash_digest(shash, data, len, out);
1142 static int omap_sham_final_shash(struct ahash_request *req)
1144 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1145 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1147 return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1148 ctx->buffer, ctx->bufcnt, req->result);
1151 static int omap_sham_final(struct ahash_request *req)
1153 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1155 ctx->flags |= BIT(FLAGS_FINUP);
1157 if (ctx->flags & BIT(FLAGS_ERROR))
1158 return 0; /* uncompleted hash is not needed */
1161 * OMAP HW accel works only with buffers >= 9.
1162 * HMAC is always >= 9 because ipad == block size.
1163 * If buffersize is less than 240, we use fallback SW encoding,
1164 * as using DMA + HW in this case doesn't provide any benefit.
1166 if ((ctx->digcnt + ctx->bufcnt) < 240)
1167 return omap_sham_final_shash(req);
1168 else if (ctx->bufcnt)
1169 return omap_sham_enqueue(req, OP_FINAL);
1171 /* copy ready hash (+ finalize hmac) */
1172 return omap_sham_finish(req);
1175 static int omap_sham_finup(struct ahash_request *req)
1177 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1180 ctx->flags |= BIT(FLAGS_FINUP);
1182 err1 = omap_sham_update(req);
1183 if (err1 == -EINPROGRESS || err1 == -EBUSY)
1186 * final() has to be always called to cleanup resources
1187 * even if udpate() failed, except EINPROGRESS
1189 err2 = omap_sham_final(req);
1191 return err1 ?: err2;
1194 static int omap_sham_digest(struct ahash_request *req)
1196 return omap_sham_init(req) ?: omap_sham_finup(req);
1199 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1200 unsigned int keylen)
1202 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1203 struct omap_sham_hmac_ctx *bctx = tctx->base;
1204 int bs = crypto_shash_blocksize(bctx->shash);
1205 int ds = crypto_shash_digestsize(bctx->shash);
1206 struct omap_sham_dev *dd = NULL, *tmp;
1209 spin_lock_bh(&sham.lock);
1211 list_for_each_entry(tmp, &sham.dev_list, list) {
1219 spin_unlock_bh(&sham.lock);
1221 err = crypto_shash_setkey(tctx->fallback, key, keylen);
1226 err = omap_sham_shash_digest(bctx->shash,
1227 crypto_shash_get_flags(bctx->shash),
1228 key, keylen, bctx->ipad);
1233 memcpy(bctx->ipad, key, keylen);
1236 memset(bctx->ipad + keylen, 0, bs - keylen);
1238 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1239 memcpy(bctx->opad, bctx->ipad, bs);
1241 for (i = 0; i < bs; i++) {
1242 bctx->ipad[i] ^= 0x36;
1243 bctx->opad[i] ^= 0x5c;
1250 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1252 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1253 const char *alg_name = crypto_tfm_alg_name(tfm);
1255 /* Allocate a fallback and abort if it failed. */
1256 tctx->fallback = crypto_alloc_shash(alg_name, 0,
1257 CRYPTO_ALG_NEED_FALLBACK);
1258 if (IS_ERR(tctx->fallback)) {
1259 pr_err("omap-sham: fallback driver '%s' "
1260 "could not be loaded.\n", alg_name);
1261 return PTR_ERR(tctx->fallback);
1264 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1265 sizeof(struct omap_sham_reqctx) + BUFLEN);
1268 struct omap_sham_hmac_ctx *bctx = tctx->base;
1269 tctx->flags |= BIT(FLAGS_HMAC);
1270 bctx->shash = crypto_alloc_shash(alg_base, 0,
1271 CRYPTO_ALG_NEED_FALLBACK);
1272 if (IS_ERR(bctx->shash)) {
1273 pr_err("omap-sham: base driver '%s' "
1274 "could not be loaded.\n", alg_base);
1275 crypto_free_shash(tctx->fallback);
1276 return PTR_ERR(bctx->shash);
1284 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1286 return omap_sham_cra_init_alg(tfm, NULL);
1289 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1291 return omap_sham_cra_init_alg(tfm, "sha1");
1294 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1296 return omap_sham_cra_init_alg(tfm, "sha224");
1299 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1301 return omap_sham_cra_init_alg(tfm, "sha256");
1304 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1306 return omap_sham_cra_init_alg(tfm, "md5");
1309 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1311 return omap_sham_cra_init_alg(tfm, "sha384");
1314 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1316 return omap_sham_cra_init_alg(tfm, "sha512");
1319 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1321 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1323 crypto_free_shash(tctx->fallback);
1324 tctx->fallback = NULL;
1326 if (tctx->flags & BIT(FLAGS_HMAC)) {
1327 struct omap_sham_hmac_ctx *bctx = tctx->base;
1328 crypto_free_shash(bctx->shash);
1332 static struct ahash_alg algs_sha1_md5[] = {
1334 .init = omap_sham_init,
1335 .update = omap_sham_update,
1336 .final = omap_sham_final,
1337 .finup = omap_sham_finup,
1338 .digest = omap_sham_digest,
1339 .halg.digestsize = SHA1_DIGEST_SIZE,
1342 .cra_driver_name = "omap-sha1",
1343 .cra_priority = 400,
1344 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1345 CRYPTO_ALG_KERN_DRIVER_ONLY |
1347 CRYPTO_ALG_NEED_FALLBACK,
1348 .cra_blocksize = SHA1_BLOCK_SIZE,
1349 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1351 .cra_module = THIS_MODULE,
1352 .cra_init = omap_sham_cra_init,
1353 .cra_exit = omap_sham_cra_exit,
1357 .init = omap_sham_init,
1358 .update = omap_sham_update,
1359 .final = omap_sham_final,
1360 .finup = omap_sham_finup,
1361 .digest = omap_sham_digest,
1362 .halg.digestsize = MD5_DIGEST_SIZE,
1365 .cra_driver_name = "omap-md5",
1366 .cra_priority = 400,
1367 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1368 CRYPTO_ALG_KERN_DRIVER_ONLY |
1370 CRYPTO_ALG_NEED_FALLBACK,
1371 .cra_blocksize = SHA1_BLOCK_SIZE,
1372 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1373 .cra_alignmask = OMAP_ALIGN_MASK,
1374 .cra_module = THIS_MODULE,
1375 .cra_init = omap_sham_cra_init,
1376 .cra_exit = omap_sham_cra_exit,
1380 .init = omap_sham_init,
1381 .update = omap_sham_update,
1382 .final = omap_sham_final,
1383 .finup = omap_sham_finup,
1384 .digest = omap_sham_digest,
1385 .setkey = omap_sham_setkey,
1386 .halg.digestsize = SHA1_DIGEST_SIZE,
1388 .cra_name = "hmac(sha1)",
1389 .cra_driver_name = "omap-hmac-sha1",
1390 .cra_priority = 400,
1391 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1392 CRYPTO_ALG_KERN_DRIVER_ONLY |
1394 CRYPTO_ALG_NEED_FALLBACK,
1395 .cra_blocksize = SHA1_BLOCK_SIZE,
1396 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1397 sizeof(struct omap_sham_hmac_ctx),
1398 .cra_alignmask = OMAP_ALIGN_MASK,
1399 .cra_module = THIS_MODULE,
1400 .cra_init = omap_sham_cra_sha1_init,
1401 .cra_exit = omap_sham_cra_exit,
1405 .init = omap_sham_init,
1406 .update = omap_sham_update,
1407 .final = omap_sham_final,
1408 .finup = omap_sham_finup,
1409 .digest = omap_sham_digest,
1410 .setkey = omap_sham_setkey,
1411 .halg.digestsize = MD5_DIGEST_SIZE,
1413 .cra_name = "hmac(md5)",
1414 .cra_driver_name = "omap-hmac-md5",
1415 .cra_priority = 400,
1416 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1417 CRYPTO_ALG_KERN_DRIVER_ONLY |
1419 CRYPTO_ALG_NEED_FALLBACK,
1420 .cra_blocksize = SHA1_BLOCK_SIZE,
1421 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1422 sizeof(struct omap_sham_hmac_ctx),
1423 .cra_alignmask = OMAP_ALIGN_MASK,
1424 .cra_module = THIS_MODULE,
1425 .cra_init = omap_sham_cra_md5_init,
1426 .cra_exit = omap_sham_cra_exit,
1431 /* OMAP4 has some algs in addition to what OMAP2 has */
1432 static struct ahash_alg algs_sha224_sha256[] = {
1434 .init = omap_sham_init,
1435 .update = omap_sham_update,
1436 .final = omap_sham_final,
1437 .finup = omap_sham_finup,
1438 .digest = omap_sham_digest,
1439 .halg.digestsize = SHA224_DIGEST_SIZE,
1441 .cra_name = "sha224",
1442 .cra_driver_name = "omap-sha224",
1443 .cra_priority = 400,
1444 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1446 CRYPTO_ALG_NEED_FALLBACK,
1447 .cra_blocksize = SHA224_BLOCK_SIZE,
1448 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1450 .cra_module = THIS_MODULE,
1451 .cra_init = omap_sham_cra_init,
1452 .cra_exit = omap_sham_cra_exit,
1456 .init = omap_sham_init,
1457 .update = omap_sham_update,
1458 .final = omap_sham_final,
1459 .finup = omap_sham_finup,
1460 .digest = omap_sham_digest,
1461 .halg.digestsize = SHA256_DIGEST_SIZE,
1463 .cra_name = "sha256",
1464 .cra_driver_name = "omap-sha256",
1465 .cra_priority = 400,
1466 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1468 CRYPTO_ALG_NEED_FALLBACK,
1469 .cra_blocksize = SHA256_BLOCK_SIZE,
1470 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1472 .cra_module = THIS_MODULE,
1473 .cra_init = omap_sham_cra_init,
1474 .cra_exit = omap_sham_cra_exit,
1478 .init = omap_sham_init,
1479 .update = omap_sham_update,
1480 .final = omap_sham_final,
1481 .finup = omap_sham_finup,
1482 .digest = omap_sham_digest,
1483 .setkey = omap_sham_setkey,
1484 .halg.digestsize = SHA224_DIGEST_SIZE,
1486 .cra_name = "hmac(sha224)",
1487 .cra_driver_name = "omap-hmac-sha224",
1488 .cra_priority = 400,
1489 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1491 CRYPTO_ALG_NEED_FALLBACK,
1492 .cra_blocksize = SHA224_BLOCK_SIZE,
1493 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1494 sizeof(struct omap_sham_hmac_ctx),
1495 .cra_alignmask = OMAP_ALIGN_MASK,
1496 .cra_module = THIS_MODULE,
1497 .cra_init = omap_sham_cra_sha224_init,
1498 .cra_exit = omap_sham_cra_exit,
1502 .init = omap_sham_init,
1503 .update = omap_sham_update,
1504 .final = omap_sham_final,
1505 .finup = omap_sham_finup,
1506 .digest = omap_sham_digest,
1507 .setkey = omap_sham_setkey,
1508 .halg.digestsize = SHA256_DIGEST_SIZE,
1510 .cra_name = "hmac(sha256)",
1511 .cra_driver_name = "omap-hmac-sha256",
1512 .cra_priority = 400,
1513 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1515 CRYPTO_ALG_NEED_FALLBACK,
1516 .cra_blocksize = SHA256_BLOCK_SIZE,
1517 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1518 sizeof(struct omap_sham_hmac_ctx),
1519 .cra_alignmask = OMAP_ALIGN_MASK,
1520 .cra_module = THIS_MODULE,
1521 .cra_init = omap_sham_cra_sha256_init,
1522 .cra_exit = omap_sham_cra_exit,
1527 static struct ahash_alg algs_sha384_sha512[] = {
1529 .init = omap_sham_init,
1530 .update = omap_sham_update,
1531 .final = omap_sham_final,
1532 .finup = omap_sham_finup,
1533 .digest = omap_sham_digest,
1534 .halg.digestsize = SHA384_DIGEST_SIZE,
1536 .cra_name = "sha384",
1537 .cra_driver_name = "omap-sha384",
1538 .cra_priority = 400,
1539 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1541 CRYPTO_ALG_NEED_FALLBACK,
1542 .cra_blocksize = SHA384_BLOCK_SIZE,
1543 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1545 .cra_module = THIS_MODULE,
1546 .cra_init = omap_sham_cra_init,
1547 .cra_exit = omap_sham_cra_exit,
1551 .init = omap_sham_init,
1552 .update = omap_sham_update,
1553 .final = omap_sham_final,
1554 .finup = omap_sham_finup,
1555 .digest = omap_sham_digest,
1556 .halg.digestsize = SHA512_DIGEST_SIZE,
1558 .cra_name = "sha512",
1559 .cra_driver_name = "omap-sha512",
1560 .cra_priority = 400,
1561 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1563 CRYPTO_ALG_NEED_FALLBACK,
1564 .cra_blocksize = SHA512_BLOCK_SIZE,
1565 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1567 .cra_module = THIS_MODULE,
1568 .cra_init = omap_sham_cra_init,
1569 .cra_exit = omap_sham_cra_exit,
1573 .init = omap_sham_init,
1574 .update = omap_sham_update,
1575 .final = omap_sham_final,
1576 .finup = omap_sham_finup,
1577 .digest = omap_sham_digest,
1578 .setkey = omap_sham_setkey,
1579 .halg.digestsize = SHA384_DIGEST_SIZE,
1581 .cra_name = "hmac(sha384)",
1582 .cra_driver_name = "omap-hmac-sha384",
1583 .cra_priority = 400,
1584 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1586 CRYPTO_ALG_NEED_FALLBACK,
1587 .cra_blocksize = SHA384_BLOCK_SIZE,
1588 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1589 sizeof(struct omap_sham_hmac_ctx),
1590 .cra_alignmask = OMAP_ALIGN_MASK,
1591 .cra_module = THIS_MODULE,
1592 .cra_init = omap_sham_cra_sha384_init,
1593 .cra_exit = omap_sham_cra_exit,
1597 .init = omap_sham_init,
1598 .update = omap_sham_update,
1599 .final = omap_sham_final,
1600 .finup = omap_sham_finup,
1601 .digest = omap_sham_digest,
1602 .setkey = omap_sham_setkey,
1603 .halg.digestsize = SHA512_DIGEST_SIZE,
1605 .cra_name = "hmac(sha512)",
1606 .cra_driver_name = "omap-hmac-sha512",
1607 .cra_priority = 400,
1608 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1610 CRYPTO_ALG_NEED_FALLBACK,
1611 .cra_blocksize = SHA512_BLOCK_SIZE,
1612 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1613 sizeof(struct omap_sham_hmac_ctx),
1614 .cra_alignmask = OMAP_ALIGN_MASK,
1615 .cra_module = THIS_MODULE,
1616 .cra_init = omap_sham_cra_sha512_init,
1617 .cra_exit = omap_sham_cra_exit,
1622 static void omap_sham_done_task(unsigned long data)
1624 struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1627 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1628 omap_sham_handle_queue(dd, NULL);
1632 if (test_bit(FLAGS_CPU, &dd->flags)) {
1633 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1634 /* hash or semi-hash ready */
1635 err = omap_sham_update_cpu(dd);
1636 if (err != -EINPROGRESS)
1639 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1640 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1641 omap_sham_update_dma_stop(dd);
1647 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1648 /* hash or semi-hash ready */
1649 clear_bit(FLAGS_DMA_READY, &dd->flags);
1650 err = omap_sham_update_dma_start(dd);
1651 if (err != -EINPROGRESS)
1659 dev_dbg(dd->dev, "update done: err: %d\n", err);
1660 /* finish curent request */
1661 omap_sham_finish_req(dd->req, err);
1663 /* If we are not busy, process next req */
1664 if (!test_bit(FLAGS_BUSY, &dd->flags))
1665 omap_sham_handle_queue(dd, NULL);
1668 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1670 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1671 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1673 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1674 tasklet_schedule(&dd->done_task);
1680 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1682 struct omap_sham_dev *dd = dev_id;
1684 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1685 /* final -> allow device to go to power-saving mode */
1686 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1688 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1689 SHA_REG_CTRL_OUTPUT_READY);
1690 omap_sham_read(dd, SHA_REG_CTRL);
1692 return omap_sham_irq_common(dd);
1695 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1697 struct omap_sham_dev *dd = dev_id;
1699 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1701 return omap_sham_irq_common(dd);
1704 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1706 .algs_list = algs_sha1_md5,
1707 .size = ARRAY_SIZE(algs_sha1_md5),
1711 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1712 .algs_info = omap_sham_algs_info_omap2,
1713 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1714 .flags = BIT(FLAGS_BE32_SHA1),
1715 .digest_size = SHA1_DIGEST_SIZE,
1716 .copy_hash = omap_sham_copy_hash_omap2,
1717 .write_ctrl = omap_sham_write_ctrl_omap2,
1718 .trigger = omap_sham_trigger_omap2,
1719 .poll_irq = omap_sham_poll_irq_omap2,
1720 .intr_hdlr = omap_sham_irq_omap2,
1721 .idigest_ofs = 0x00,
1726 .sysstatus_ofs = 0x64,
1734 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1736 .algs_list = algs_sha1_md5,
1737 .size = ARRAY_SIZE(algs_sha1_md5),
1740 .algs_list = algs_sha224_sha256,
1741 .size = ARRAY_SIZE(algs_sha224_sha256),
1745 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1746 .algs_info = omap_sham_algs_info_omap4,
1747 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1748 .flags = BIT(FLAGS_AUTO_XOR),
1749 .digest_size = SHA256_DIGEST_SIZE,
1750 .copy_hash = omap_sham_copy_hash_omap4,
1751 .write_ctrl = omap_sham_write_ctrl_omap4,
1752 .trigger = omap_sham_trigger_omap4,
1753 .poll_irq = omap_sham_poll_irq_omap4,
1754 .intr_hdlr = omap_sham_irq_omap4,
1755 .idigest_ofs = 0x020,
1758 .digcnt_ofs = 0x040,
1761 .sysstatus_ofs = 0x114,
1764 .major_mask = 0x0700,
1766 .minor_mask = 0x003f,
1770 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1772 .algs_list = algs_sha1_md5,
1773 .size = ARRAY_SIZE(algs_sha1_md5),
1776 .algs_list = algs_sha224_sha256,
1777 .size = ARRAY_SIZE(algs_sha224_sha256),
1780 .algs_list = algs_sha384_sha512,
1781 .size = ARRAY_SIZE(algs_sha384_sha512),
1785 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1786 .algs_info = omap_sham_algs_info_omap5,
1787 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1788 .flags = BIT(FLAGS_AUTO_XOR),
1789 .digest_size = SHA512_DIGEST_SIZE,
1790 .copy_hash = omap_sham_copy_hash_omap4,
1791 .write_ctrl = omap_sham_write_ctrl_omap4,
1792 .trigger = omap_sham_trigger_omap4,
1793 .poll_irq = omap_sham_poll_irq_omap4,
1794 .intr_hdlr = omap_sham_irq_omap4,
1795 .idigest_ofs = 0x240,
1796 .odigest_ofs = 0x200,
1798 .digcnt_ofs = 0x280,
1801 .sysstatus_ofs = 0x114,
1803 .length_ofs = 0x288,
1804 .major_mask = 0x0700,
1806 .minor_mask = 0x003f,
1810 static const struct of_device_id omap_sham_of_match[] = {
1812 .compatible = "ti,omap2-sham",
1813 .data = &omap_sham_pdata_omap2,
1816 .compatible = "ti,omap3-sham",
1817 .data = &omap_sham_pdata_omap2,
1820 .compatible = "ti,omap4-sham",
1821 .data = &omap_sham_pdata_omap4,
1824 .compatible = "ti,omap5-sham",
1825 .data = &omap_sham_pdata_omap5,
1829 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1831 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1832 struct device *dev, struct resource *res)
1834 struct device_node *node = dev->of_node;
1835 const struct of_device_id *match;
1838 match = of_match_device(of_match_ptr(omap_sham_of_match), dev);
1840 dev_err(dev, "no compatible OF match\n");
1845 err = of_address_to_resource(node, 0, res);
1847 dev_err(dev, "can't translate OF node address\n");
1852 dd->irq = irq_of_parse_and_map(node, 0);
1854 dev_err(dev, "can't translate OF irq value\n");
1859 dd->pdata = match->data;
1865 static const struct of_device_id omap_sham_of_match[] = {
1869 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1870 struct device *dev, struct resource *res)
1876 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1877 struct platform_device *pdev, struct resource *res)
1879 struct device *dev = &pdev->dev;
1883 /* Get the base address */
1884 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1886 dev_err(dev, "no MEM resource info\n");
1890 memcpy(res, r, sizeof(*res));
1893 dd->irq = platform_get_irq(pdev, 0);
1895 dev_err(dev, "no IRQ resource info\n");
1900 /* Only OMAP2/3 can be non-DT */
1901 dd->pdata = &omap_sham_pdata_omap2;
1907 static int omap_sham_probe(struct platform_device *pdev)
1909 struct omap_sham_dev *dd;
1910 struct device *dev = &pdev->dev;
1911 struct resource res;
1912 dma_cap_mask_t mask;
1916 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
1918 dev_err(dev, "unable to alloc data struct.\n");
1923 platform_set_drvdata(pdev, dd);
1925 INIT_LIST_HEAD(&dd->list);
1926 spin_lock_init(&dd->lock);
1927 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
1928 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
1930 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
1931 omap_sham_get_res_pdev(dd, pdev, &res);
1935 dd->io_base = devm_ioremap_resource(dev, &res);
1936 if (IS_ERR(dd->io_base)) {
1937 err = PTR_ERR(dd->io_base);
1940 dd->phys_base = res.start;
1942 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
1943 IRQF_TRIGGER_NONE, dev_name(dev), dd);
1945 dev_err(dev, "unable to request irq %d, err = %d\n",
1951 dma_cap_set(DMA_SLAVE, mask);
1953 dd->dma_lch = dma_request_chan(dev, "rx");
1954 if (IS_ERR(dd->dma_lch)) {
1955 err = PTR_ERR(dd->dma_lch);
1956 if (err == -EPROBE_DEFER)
1959 dd->polling_mode = 1;
1960 dev_dbg(dev, "using polling mode instead of dma\n");
1963 dd->flags |= dd->pdata->flags;
1965 pm_runtime_use_autosuspend(dev);
1966 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1968 pm_runtime_enable(dev);
1969 pm_runtime_irq_safe(dev);
1971 err = pm_runtime_get_sync(dev);
1973 dev_err(dev, "failed to get sync: %d\n", err);
1977 rev = omap_sham_read(dd, SHA_REG_REV(dd));
1978 pm_runtime_put_sync(&pdev->dev);
1980 dev_info(dev, "hw accel on OMAP rev %u.%u\n",
1981 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
1982 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1984 spin_lock(&sham.lock);
1985 list_add_tail(&dd->list, &sham.dev_list);
1986 spin_unlock(&sham.lock);
1988 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1989 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1990 err = crypto_register_ahash(
1991 &dd->pdata->algs_info[i].algs_list[j]);
1995 dd->pdata->algs_info[i].registered++;
2002 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2003 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2004 crypto_unregister_ahash(
2005 &dd->pdata->algs_info[i].algs_list[j]);
2007 pm_runtime_disable(dev);
2008 if (!dd->polling_mode)
2009 dma_release_channel(dd->dma_lch);
2011 dev_err(dev, "initialization failed.\n");
2016 static int omap_sham_remove(struct platform_device *pdev)
2018 static struct omap_sham_dev *dd;
2021 dd = platform_get_drvdata(pdev);
2024 spin_lock(&sham.lock);
2025 list_del(&dd->list);
2026 spin_unlock(&sham.lock);
2027 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2028 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2029 crypto_unregister_ahash(
2030 &dd->pdata->algs_info[i].algs_list[j]);
2031 tasklet_kill(&dd->done_task);
2032 pm_runtime_disable(&pdev->dev);
2034 if (!dd->polling_mode)
2035 dma_release_channel(dd->dma_lch);
2040 #ifdef CONFIG_PM_SLEEP
2041 static int omap_sham_suspend(struct device *dev)
2043 pm_runtime_put_sync(dev);
2047 static int omap_sham_resume(struct device *dev)
2049 int err = pm_runtime_get_sync(dev);
2051 dev_err(dev, "failed to get sync: %d\n", err);
2058 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2060 static struct platform_driver omap_sham_driver = {
2061 .probe = omap_sham_probe,
2062 .remove = omap_sham_remove,
2064 .name = "omap-sham",
2065 .pm = &omap_sham_pm_ops,
2066 .of_match_table = omap_sham_of_match,
2070 module_platform_driver(omap_sham_driver);
2072 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2073 MODULE_LICENSE("GPL v2");
2074 MODULE_AUTHOR("Dmitry Kasatkin");
2075 MODULE_ALIAS("platform:omap-sham");