drivers/crypto/omap-sham.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Cryptographic API.
   4  *
   5  * Support for OMAP SHA1/MD5 HW acceleration.
   6  *
   7  * Copyright (c) 2010 Nokia Corporation
   8  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   9  * Copyright (c) 2011 Texas Instruments Incorporated
  10  *
  11  * Some ideas are from old omap-sha1-md5.c driver.
  12  */
  13
  14 #define pr_fmt(fmt) "%s: " fmt, __func__
  15
  16 #include <linux/err.h>
  17 #include <linux/device.h>
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/errno.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/kernel.h>
  23 #include <linux/irq.h>
  24 #include <linux/io.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/scatterlist.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/dmaengine.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of_address.h>
  33 #include <linux/of_irq.h>
  34 #include <linux/delay.h>
  35 #include <linux/crypto.h>
  36 #include <linux/cryptohash.h>
  37 #include <crypto/scatterwalk.h>
  38 #include <crypto/algapi.h>
  39 #include <crypto/sha.h>
  40 #include <crypto/hash.h>
  41 #include <crypto/hmac.h>
  42 #include <crypto/internal/hash.h>
  43
  44 #define MD5_DIGEST_SIZE                 16
  45
  46 #define SHA_REG_IDIGEST(dd, x)          ((dd)->pdata->idigest_ofs + ((x)*0x04))
  47 #define SHA_REG_DIN(dd, x)              ((dd)->pdata->din_ofs + ((x) * 0x04))
  48 #define SHA_REG_DIGCNT(dd)              ((dd)->pdata->digcnt_ofs)
  49
  50 #define SHA_REG_ODIGEST(dd, x)          ((dd)->pdata->odigest_ofs + (x * 0x04))
  51
  52 #define SHA_REG_CTRL                    0x18
  53 #define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  54 #define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  55 #define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  56 #define SHA_REG_CTRL_ALGO               (1 << 2)
  57 #define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  58 #define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  59
  60 #define SHA_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  61
  62 #define SHA_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  63 #define SHA_REG_MASK_DMA_EN             (1 << 3)
  64 #define SHA_REG_MASK_IT_EN              (1 << 2)
  65 #define SHA_REG_MASK_SOFTRESET          (1 << 1)
  66 #define SHA_REG_AUTOIDLE                (1 << 0)
  67
  68 #define SHA_REG_SYSSTATUS(dd)           ((dd)->pdata->sysstatus_ofs)
  69 #define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  70
  71 #define SHA_REG_MODE(dd)                ((dd)->pdata->mode_ofs)
  72 #define SHA_REG_MODE_HMAC_OUTER_HASH    (1 << 7)
  73 #define SHA_REG_MODE_HMAC_KEY_PROC      (1 << 5)
  74 #define SHA_REG_MODE_CLOSE_HASH         (1 << 4)
  75 #define SHA_REG_MODE_ALGO_CONSTANT      (1 << 3)
  76
  77 #define SHA_REG_MODE_ALGO_MASK          (7 << 0)
  78 #define SHA_REG_MODE_ALGO_MD5_128       (0 << 1)
  79 #define SHA_REG_MODE_ALGO_SHA1_160      (1 << 1)
  80 #define SHA_REG_MODE_ALGO_SHA2_224      (2 << 1)
  81 #define SHA_REG_MODE_ALGO_SHA2_256      (3 << 1)
  82 #define SHA_REG_MODE_ALGO_SHA2_384      (1 << 0)
  83 #define SHA_REG_MODE_ALGO_SHA2_512      (3 << 0)
  84
  85 #define SHA_REG_LENGTH(dd)              ((dd)->pdata->length_ofs)
  86
  87 #define SHA_REG_IRQSTATUS               0x118
  88 #define SHA_REG_IRQSTATUS_CTX_RDY       (1 << 3)
  89 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
  90 #define SHA_REG_IRQSTATUS_INPUT_RDY     (1 << 1)
  91 #define SHA_REG_IRQSTATUS_OUTPUT_RDY    (1 << 0)
  92
  93 #define SHA_REG_IRQENA                  0x11C
  94 #define SHA_REG_IRQENA_CTX_RDY          (1 << 3)
  95 #define SHA_REG_IRQENA_PARTHASH_RDY     (1 << 2)
  96 #define SHA_REG_IRQENA_INPUT_RDY        (1 << 1)
  97 #define SHA_REG_IRQENA_OUTPUT_RDY       (1 << 0)
  98
  99 #define DEFAULT_TIMEOUT_INTERVAL        HZ
 100
 101 #define DEFAULT_AUTOSUSPEND_DELAY       1000
 102
 103 /* mostly device flags */
 104 #define FLAGS_BUSY              0
 105 #define FLAGS_FINAL             1
 106 #define FLAGS_DMA_ACTIVE        2
 107 #define FLAGS_OUTPUT_READY      3
 108 #define FLAGS_INIT              4
 109 #define FLAGS_CPU               5
 110 #define FLAGS_DMA_READY         6
 111 #define FLAGS_AUTO_XOR          7
 112 #define FLAGS_BE32_SHA1         8
 113 #define FLAGS_SGS_COPIED        9
 114 #define FLAGS_SGS_ALLOCED       10
 115 #define FLAGS_HUGE              11
 116
 117 /* context flags */
 118 #define FLAGS_FINUP             16
 119
 120 #define FLAGS_MODE_SHIFT        18
 121 #define FLAGS_MODE_MASK         (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
 122 #define FLAGS_MODE_MD5          (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
 123 #define FLAGS_MODE_SHA1         (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
 124 #define FLAGS_MODE_SHA224       (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
 125 #define FLAGS_MODE_SHA256       (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
 126 #define FLAGS_MODE_SHA384       (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
 127 #define FLAGS_MODE_SHA512       (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
 128
 129 #define FLAGS_HMAC              21
 130 #define FLAGS_ERROR             22
 131
 132 #define OP_UPDATE               1
 133 #define OP_FINAL                2
 134
 135 #define OMAP_ALIGN_MASK         (sizeof(u32)-1)
 136 #define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
 137
 138 #define BUFLEN                  SHA512_BLOCK_SIZE
 139 #define OMAP_SHA_DMA_THRESHOLD  256
 140
 141 #define OMAP_SHA_MAX_DMA_LEN    (1024 * 2048)
 142
 143 struct omap_sham_dev;
 144
 145 struct omap_sham_reqctx {
 146         struct omap_sham_dev    *dd;
 147         unsigned long           flags;
 148         unsigned long           op;
 149
 150         u8                      digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
 151         size_t                  digcnt;
 152         size_t                  bufcnt;
 153         size_t                  buflen;
 154
 155         /* walk state */
 156         struct scatterlist      *sg;
 157         struct scatterlist      sgl[2];
 158         int                     offset; /* offset in current sg */
 159         int                     sg_len;
 160         unsigned int            total;  /* total request */
 161
 162         u8                      buffer[0] OMAP_ALIGNED;
 163 };
 164
 165 struct omap_sham_hmac_ctx {
 166         struct crypto_shash     *shash;
 167         u8                      ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 168         u8                      opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 169 };
 170
 171 struct omap_sham_ctx {
 172         struct omap_sham_dev    *dd;
 173
 174         unsigned long           flags;
 175
 176         /* fallback stuff */
 177         struct crypto_shash     *fallback;
 178
 179         struct omap_sham_hmac_ctx base[0];
 180 };
 181
 182 #define OMAP_SHAM_QUEUE_LENGTH  10
 183
 184 struct omap_sham_algs_info {
 185         struct ahash_alg        *algs_list;
 186         unsigned int            size;
 187         unsigned int            registered;
 188 };
 189
 190 struct omap_sham_pdata {
 191         struct omap_sham_algs_info      *algs_info;
 192         unsigned int    algs_info_size;
 193         unsigned long   flags;
 194         int             digest_size;
 195
 196         void            (*copy_hash)(struct ahash_request *req, int out);
 197         void            (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
 198                                       int final, int dma);
 199         void            (*trigger)(struct omap_sham_dev *dd, size_t length);
 200         int             (*poll_irq)(struct omap_sham_dev *dd);
 201         irqreturn_t     (*intr_hdlr)(int irq, void *dev_id);
 202
 203         u32             odigest_ofs;
 204         u32             idigest_ofs;
 205         u32             din_ofs;
 206         u32             digcnt_ofs;
 207         u32             rev_ofs;
 208         u32             mask_ofs;
 209         u32             sysstatus_ofs;
 210         u32             mode_ofs;
 211         u32             length_ofs;
 212
 213         u32             major_mask;
 214         u32             major_shift;
 215         u32             minor_mask;
 216         u32             minor_shift;
 217 };
 218
 219 struct omap_sham_dev {
 220         struct list_head        list;
 221         unsigned long           phys_base;
 222         struct device           *dev;
 223         void __iomem            *io_base;
 224         int                     irq;
 225         spinlock_t              lock;
 226         int                     err;
 227         struct dma_chan         *dma_lch;
 228         struct tasklet_struct   done_task;
 229         u8                      polling_mode;
 230         u8                      xmit_buf[BUFLEN] OMAP_ALIGNED;
 231
 232         unsigned long           flags;
 233         int                     fallback_sz;
 234         struct crypto_queue     queue;
 235         struct ahash_request    *req;
 236
 237         const struct omap_sham_pdata    *pdata;
 238 };
 239
 240 struct omap_sham_drv {
 241         struct list_head        dev_list;
 242         spinlock_t              lock;
 243         unsigned long           flags;
 244 };
 245
 246 static struct omap_sham_drv sham = {
 247         .dev_list = LIST_HEAD_INIT(sham.dev_list),
 248         .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 249 };
 250
 251 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 252 {
 253         return __raw_readl(dd->io_base + offset);
 254 }
 255
 256 static inline void omap_sham_write(struct omap_sham_dev *dd,
 257                                         u32 offset, u32 value)
 258 {
 259         __raw_writel(value, dd->io_base + offset);
 260 }
 261
 262 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 263                                         u32 value, u32 mask)
 264 {
 265         u32 val;
 266
 267         val = omap_sham_read(dd, address);
 268         val &= ~mask;
 269         val |= value;
 270         omap_sham_write(dd, address, val);
 271 }
 272
 273 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 274 {
 275         unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 276
 277         while (!(omap_sham_read(dd, offset) & bit)) {
 278                 if (time_is_before_jiffies(timeout))
 279                         return -ETIMEDOUT;
 280         }
 281
 282         return 0;
 283 }
 284
 285 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
 286 {
 287         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 288         struct omap_sham_dev *dd = ctx->dd;
 289         u32 *hash = (u32 *)ctx->digest;
 290         int i;
 291
 292         for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 293                 if (out)
 294                         hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
 295                 else
 296                         omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
 297         }
 298 }
 299
 300 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
 301 {
 302         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 303         struct omap_sham_dev *dd = ctx->dd;
 304         int i;
 305
 306         if (ctx->flags & BIT(FLAGS_HMAC)) {
 307                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 308                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 309                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 310                 u32 *opad = (u32 *)bctx->opad;
 311
 312                 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 313                         if (out)
 314                                 opad[i] = omap_sham_read(dd,
 315                                                 SHA_REG_ODIGEST(dd, i));
 316                         else
 317                                 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
 318                                                 opad[i]);
 319                 }
 320         }
 321
 322         omap_sham_copy_hash_omap2(req, out);
 323 }
 324
 325 static void omap_sham_copy_ready_hash(struct ahash_request *req)
 326 {
 327         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 328         u32 *in = (u32 *)ctx->digest;
 329         u32 *hash = (u32 *)req->result;
 330         int i, d, big_endian = 0;
 331
 332         if (!hash)
 333                 return;
 334
 335         switch (ctx->flags & FLAGS_MODE_MASK) {
 336         case FLAGS_MODE_MD5:
 337                 d = MD5_DIGEST_SIZE / sizeof(u32);
 338                 break;
 339         case FLAGS_MODE_SHA1:
 340                 /* OMAP2 SHA1 is big endian */
 341                 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
 342                         big_endian = 1;
 343                 d = SHA1_DIGEST_SIZE / sizeof(u32);
 344                 break;
 345         case FLAGS_MODE_SHA224:
 346                 d = SHA224_DIGEST_SIZE / sizeof(u32);
 347                 break;
 348         case FLAGS_MODE_SHA256:
 349                 d = SHA256_DIGEST_SIZE / sizeof(u32);
 350                 break;
 351         case FLAGS_MODE_SHA384:
 352                 d = SHA384_DIGEST_SIZE / sizeof(u32);
 353                 break;
 354         case FLAGS_MODE_SHA512:
 355                 d = SHA512_DIGEST_SIZE / sizeof(u32);
 356                 break;
 357         default:
 358                 d = 0;
 359         }
 360
 361         if (big_endian)
 362                 for (i = 0; i < d; i++)
 363                         hash[i] = be32_to_cpu(in[i]);
 364         else
 365                 for (i = 0; i < d; i++)
 366                         hash[i] = le32_to_cpu(in[i]);
 367 }
 368
 369 static int omap_sham_hw_init(struct omap_sham_dev *dd)
 370 {
 371         int err;
 372
 373         err = pm_runtime_get_sync(dd->dev);
 374         if (err < 0) {
 375                 dev_err(dd->dev, "failed to get sync: %d\n", err);
 376                 return err;
 377         }
 378
 379         if (!test_bit(FLAGS_INIT, &dd->flags)) {
 380                 set_bit(FLAGS_INIT, &dd->flags);
 381                 dd->err = 0;
 382         }
 383
 384         return 0;
 385 }
 386
 387 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
 388                                  int final, int dma)
 389 {
 390         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 391         u32 val = length << 5, mask;
 392
 393         if (likely(ctx->digcnt))
 394                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 395
 396         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 397                 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 398                 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 399         /*
 400          * Setting ALGO_CONST only for the first iteration
 401          * and CLOSE_HASH only for the last one.
 402          */
 403         if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
 404                 val |= SHA_REG_CTRL_ALGO;
 405         if (!ctx->digcnt)
 406                 val |= SHA_REG_CTRL_ALGO_CONST;
 407         if (final)
 408                 val |= SHA_REG_CTRL_CLOSE_HASH;
 409
 410         mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 411                         SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 412
 413         omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 414 }
 415
 416 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
 417 {
 418 }
 419
 420 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
 421 {
 422         return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
 423 }
 424
 425 static int get_block_size(struct omap_sham_reqctx *ctx)
 426 {
 427         int d;
 428
 429         switch (ctx->flags & FLAGS_MODE_MASK) {
 430         case FLAGS_MODE_MD5:
 431         case FLAGS_MODE_SHA1:
 432                 d = SHA1_BLOCK_SIZE;
 433                 break;
 434         case FLAGS_MODE_SHA224:
 435         case FLAGS_MODE_SHA256:
 436                 d = SHA256_BLOCK_SIZE;
 437                 break;
 438         case FLAGS_MODE_SHA384:
 439         case FLAGS_MODE_SHA512:
 440                 d = SHA512_BLOCK_SIZE;
 441                 break;
 442         default:
 443                 d = 0;
 444         }
 445
 446         return d;
 447 }
 448
 449 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
 450                                     u32 *value, int count)
 451 {
 452         for (; count--; value++, offset += 4)
 453                 omap_sham_write(dd, offset, *value);
 454 }
 455
 456 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
 457                                  int final, int dma)
 458 {
 459         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 460         u32 val, mask;
 461
 462         /*
 463          * Setting ALGO_CONST only for the first iteration and
 464          * CLOSE_HASH only for the last one. Note that flags mode bits
 465          * correspond to algorithm encoding in mode register.
 466          */
 467         val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
 468         if (!ctx->digcnt) {
 469                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 470                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 471                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 472                 int bs, nr_dr;
 473
 474                 val |= SHA_REG_MODE_ALGO_CONSTANT;
 475
 476                 if (ctx->flags & BIT(FLAGS_HMAC)) {
 477                         bs = get_block_size(ctx);
 478                         nr_dr = bs / (2 * sizeof(u32));
 479                         val |= SHA_REG_MODE_HMAC_KEY_PROC;
 480                         omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
 481                                           (u32 *)bctx->ipad, nr_dr);
 482                         omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
 483                                           (u32 *)bctx->ipad + nr_dr, nr_dr);
 484                         ctx->digcnt += bs;
 485                 }
 486         }
 487
 488         if (final) {
 489                 val |= SHA_REG_MODE_CLOSE_HASH;
 490
 491                 if (ctx->flags & BIT(FLAGS_HMAC))
 492                         val |= SHA_REG_MODE_HMAC_OUTER_HASH;
 493         }
 494
 495         mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
 496                SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
 497                SHA_REG_MODE_HMAC_KEY_PROC;
 498
 499         dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
 500         omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
 501         omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
 502         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 503                              SHA_REG_MASK_IT_EN |
 504                                      (dma ? SHA_REG_MASK_DMA_EN : 0),
 505                              SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 506 }
 507
 508 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
 509 {
 510         omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
 511 }
 512
 513 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
 514 {
 515         return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
 516                               SHA_REG_IRQSTATUS_INPUT_RDY);
 517 }
 518
 519 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
 520                               int final)
 521 {
 522         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 523         int count, len32, bs32, offset = 0;
 524         const u32 *buffer;
 525         int mlen;
 526         struct sg_mapping_iter mi;
 527
 528         dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 529                                                 ctx->digcnt, length, final);
 530
 531         dd->pdata->write_ctrl(dd, length, final, 0);
 532         dd->pdata->trigger(dd, length);
 533
 534         /* should be non-zero before next lines to disable clocks later */
 535         ctx->digcnt += length;
 536         ctx->total -= length;
 537
 538         if (final)
 539                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 540
 541         set_bit(FLAGS_CPU, &dd->flags);
 542
 543         len32 = DIV_ROUND_UP(length, sizeof(u32));
 544         bs32 = get_block_size(ctx) / sizeof(u32);
 545
 546         sg_miter_start(&mi, ctx->sg, ctx->sg_len,
 547                        SG_MITER_FROM_SG | SG_MITER_ATOMIC);
 548
 549         mlen = 0;
 550
 551         while (len32) {
 552                 if (dd->pdata->poll_irq(dd))
 553                         return -ETIMEDOUT;
 554
 555                 for (count = 0; count < min(len32, bs32); count++, offset++) {
 556                         if (!mlen) {
 557                                 sg_miter_next(&mi);
 558                                 mlen = mi.length;
 559                                 if (!mlen) {
 560                                         pr_err("sg miter failure.\n");
 561                                         return -EINVAL;
 562                                 }
 563                                 offset = 0;
 564                                 buffer = mi.addr;
 565                         }
 566                         omap_sham_write(dd, SHA_REG_DIN(dd, count),
 567                                         buffer[offset]);
 568                         mlen -= 4;
 569                 }
 570                 len32 -= min(len32, bs32);
 571         }
 572
 573         sg_miter_stop(&mi);
 574
 575         return -EINPROGRESS;
 576 }
 577
 578 static void omap_sham_dma_callback(void *param)
 579 {
 580         struct omap_sham_dev *dd = param;
 581
 582         set_bit(FLAGS_DMA_READY, &dd->flags);
 583         tasklet_schedule(&dd->done_task);
 584 }
 585
 586 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
 587                               int final)
 588 {
 589         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 590         struct dma_async_tx_descriptor *tx;
 591         struct dma_slave_config cfg;
 592         int ret;
 593
 594         dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 595                                                 ctx->digcnt, length, final);
 596
 597         if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
 598                 dev_err(dd->dev, "dma_map_sg error\n");
 599                 return -EINVAL;
 600         }
 601
 602         memset(&cfg, 0, sizeof(cfg));
 603
 604         cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
 605         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 606         cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
 607
 608         ret = dmaengine_slave_config(dd->dma_lch, &cfg);
 609         if (ret) {
 610                 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
 611                 return ret;
 612         }
 613
 614         tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
 615                                      DMA_MEM_TO_DEV,
 616                                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 617
 618         if (!tx) {
 619                 dev_err(dd->dev, "prep_slave_sg failed\n");
 620                 return -EINVAL;
 621         }
 622
 623         tx->callback = omap_sham_dma_callback;
 624         tx->callback_param = dd;
 625
 626         dd->pdata->write_ctrl(dd, length, final, 1);
 627
 628         ctx->digcnt += length;
 629         ctx->total -= length;
 630
 631         if (final)
 632                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 633
 634         set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 635
 636         dmaengine_submit(tx);
 637         dma_async_issue_pending(dd->dma_lch);
 638
 639         dd->pdata->trigger(dd, length);
 640
 641         return -EINPROGRESS;
 642 }
 643
 644 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
 645                                    struct scatterlist *sg, int bs, int new_len)
 646 {
 647         int n = sg_nents(sg);
 648         struct scatterlist *tmp;
 649         int offset = ctx->offset;
 650
 651         if (ctx->bufcnt)
 652                 n++;
 653
 654         ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
 655         if (!ctx->sg)
 656                 return -ENOMEM;
 657
 658         sg_init_table(ctx->sg, n);
 659
 660         tmp = ctx->sg;
 661
 662         ctx->sg_len = 0;
 663
 664         if (ctx->bufcnt) {
 665                 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
 666                 tmp = sg_next(tmp);
 667                 ctx->sg_len++;
 668         }
 669
 670         while (sg && new_len) {
 671                 int len = sg->length - offset;
 672
 673                 if (offset) {
 674                         offset -= sg->length;
 675                         if (offset < 0)
 676                                 offset = 0;
 677                 }
 678
 679                 if (new_len < len)
 680                         len = new_len;
 681
 682                 if (len > 0) {
 683                         new_len -= len;
 684                         sg_set_page(tmp, sg_page(sg), len, sg->offset);
 685                         if (new_len <= 0)
 686                                 sg_mark_end(tmp);
 687                         tmp = sg_next(tmp);
 688                         ctx->sg_len++;
 689                 }
 690
 691                 sg = sg_next(sg);
 692         }
 693
 694         set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
 695
 696         ctx->offset += new_len - ctx->bufcnt;
 697         ctx->bufcnt = 0;
 698
 699         return 0;
 700 }
 701
 702 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
 703                               struct scatterlist *sg, int bs,
 704                               unsigned int new_len)
 705 {
 706         int pages;
 707         void *buf;
 708
 709         pages = get_order(new_len);
 710
 711         buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
 712         if (!buf) {
 713                 pr_err("Couldn't allocate pages for unaligned cases.\n");
 714                 return -ENOMEM;
 715         }
 716
 717         if (ctx->bufcnt)
 718                 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
 719
 720         scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
 721                                  min(new_len, ctx->total) - ctx->bufcnt, 0);
 722         sg_init_table(ctx->sgl, 1);
 723         sg_set_buf(ctx->sgl, buf, new_len);
 724         ctx->sg = ctx->sgl;
 725         set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
 726         ctx->sg_len = 1;
 727         ctx->offset += new_len - ctx->bufcnt;
 728         ctx->bufcnt = 0;
 729
 730         return 0;
 731 }
 732
 733 static int omap_sham_align_sgs(struct scatterlist *sg,
 734                                int nbytes, int bs, bool final,
 735                                struct omap_sham_reqctx *rctx)
 736 {
 737         int n = 0;
 738         bool aligned = true;
 739         bool list_ok = true;
 740         struct scatterlist *sg_tmp = sg;
 741         int new_len;
 742         int offset = rctx->offset;
 743         int bufcnt = rctx->bufcnt;
 744
 745         if (!sg || !sg->length || !nbytes)
 746                 return 0;
 747
 748         new_len = nbytes;
 749
 750         if (offset)
 751                 list_ok = false;
 752
 753         if (final)
 754                 new_len = DIV_ROUND_UP(new_len, bs) * bs;
 755         else
 756                 new_len = (new_len - 1) / bs * bs;
 757
 758         if (!new_len)
 759                 return 0;
 760
 761         if (nbytes != new_len)
 762                 list_ok = false;
 763
 764         while (nbytes > 0 && sg_tmp) {
 765                 n++;
 766
 767                 if (bufcnt) {
 768                         if (!IS_ALIGNED(bufcnt, bs)) {
 769                                 aligned = false;
 770                                 break;
 771                         }
 772                         nbytes -= bufcnt;
 773                         bufcnt = 0;
 774                         continue;
 775                 }
 776
 777 #ifdef CONFIG_ZONE_DMA
 778                 if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) {
 779                         aligned = false;
 780                         break;
 781                 }
 782 #endif
 783
 784                 if (offset < sg_tmp->length) {
 785                         if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
 786                                 aligned = false;
 787                                 break;
 788                         }
 789
 790                         if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
 791                                 aligned = false;
 792                                 break;
 793                         }
 794                 }
 795
 796                 if (offset) {
 797                         offset -= sg_tmp->length;
 798                         if (offset < 0) {
 799                                 nbytes += offset;
 800                                 offset = 0;
 801                         }
 802                 } else {
 803                         nbytes -= sg_tmp->length;
 804                 }
 805
 806                 sg_tmp = sg_next(sg_tmp);
 807
 808                 if (nbytes < 0) {
 809                         list_ok = false;
 810                         break;
 811                 }
 812         }
 813
 814         if (new_len > OMAP_SHA_MAX_DMA_LEN) {
 815                 new_len = OMAP_SHA_MAX_DMA_LEN;
 816                 aligned = false;
 817         }
 818
 819         if (!aligned)
 820                 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
 821         else if (!list_ok)
 822                 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
 823         else
 824                 rctx->offset += new_len;
 825
 826         rctx->sg_len = n;
 827         rctx->sg = sg;
 828
 829         return 0;
 830 }
 831
 832 static int omap_sham_prepare_request(struct ahash_request *req, bool update)
 833 {
 834         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
 835         int bs;
 836         int ret;
 837         int nbytes;
 838         bool final = rctx->flags & BIT(FLAGS_FINUP);
 839         int xmit_len, hash_later;
 840
 841         bs = get_block_size(rctx);
 842
 843         if (update)
 844                 nbytes = req->nbytes;
 845         else
 846                 nbytes = 0;
 847
 848         rctx->total = nbytes + rctx->bufcnt - rctx->offset;
 849
 850         dev_dbg(rctx->dd->dev,
 851                 "%s: nbytes=%d, bs=%d, total=%d, offset=%d, bufcnt=%d\n",
 852                 __func__, nbytes, bs, rctx->total, rctx->offset,
 853                 rctx->bufcnt);
 854
 855         if (!rctx->total)
 856                 return 0;
 857
 858         if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
 859                 int len = bs - rctx->bufcnt % bs;
 860
 861                 if (len > nbytes)
 862                         len = nbytes;
 863                 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
 864                                          0, len, 0);
 865                 rctx->bufcnt += len;
 866                 nbytes -= len;
 867                 rctx->offset = len;
 868         }
 869
 870         if (rctx->bufcnt)
 871                 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
 872
 873         ret = omap_sham_align_sgs(req->src, rctx->total, bs, final, rctx);
 874         if (ret)
 875                 return ret;
 876
 877         xmit_len = rctx->total;
 878
 879         if (xmit_len > OMAP_SHA_MAX_DMA_LEN)
 880                 xmit_len = OMAP_SHA_MAX_DMA_LEN;
 881
 882         if (!IS_ALIGNED(xmit_len, bs)) {
 883                 if (final)
 884                         xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs;
 885                 else
 886                         xmit_len = xmit_len / bs * bs;
 887         } else if (!final && rctx->total == xmit_len) {
 888                 xmit_len -= bs;
 889         }
 890
 891         hash_later = rctx->total - xmit_len;
 892         if (hash_later < 0)
 893                 hash_later = 0;
 894
 895         if (rctx->bufcnt && nbytes) {
 896                 /* have data from previous operation and current */
 897                 sg_init_table(rctx->sgl, 2);
 898                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
 899
 900                 sg_chain(rctx->sgl, 2, req->src);
 901
 902                 rctx->sg = rctx->sgl;
 903
 904                 rctx->sg_len++;
 905         } else if (rctx->bufcnt) {
 906                 /* have buffered data only */
 907                 sg_init_table(rctx->sgl, 1);
 908                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len);
 909
 910                 rctx->sg = rctx->sgl;
 911
 912                 rctx->sg_len = 1;
 913         }
 914
 915         if (hash_later && hash_later <= rctx->buflen) {
 916                 int offset = 0;
 917
 918                 if (hash_later > req->nbytes) {
 919                         memcpy(rctx->buffer, rctx->buffer + xmit_len,
 920                                hash_later - req->nbytes);
 921                         offset = hash_later - req->nbytes;
 922                 }
 923
 924                 if (req->nbytes) {
 925                         scatterwalk_map_and_copy(rctx->buffer + offset,
 926                                                  req->src,
 927                                                  offset + req->nbytes -
 928                                                  hash_later, hash_later, 0);
 929                 }
 930
 931                 rctx->bufcnt = hash_later;
 932         } else {
 933                 rctx->bufcnt = 0;
 934         }
 935
 936         if (hash_later > rctx->buflen)
 937                 set_bit(FLAGS_HUGE, &rctx->dd->flags);
 938
 939         if (!final)
 940                 rctx->total = xmit_len;
 941
 942         return 0;
 943 }
 944
 945 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 946 {
 947         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 948
 949         dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
 950
 951         clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 952
 953         return 0;
 954 }
 955
 956 static int omap_sham_init(struct ahash_request *req)
 957 {
 958         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 959         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 960         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 961         struct omap_sham_dev *dd = NULL, *tmp;
 962         int bs = 0;
 963
 964         spin_lock_bh(&sham.lock);
 965         if (!tctx->dd) {
 966                 list_for_each_entry(tmp, &sham.dev_list, list) {
 967                         dd = tmp;
 968                         break;
 969                 }
 970                 tctx->dd = dd;
 971         } else {
 972                 dd = tctx->dd;
 973         }
 974         spin_unlock_bh(&sham.lock);
 975
 976         ctx->dd = dd;
 977
 978         ctx->flags = 0;
 979
 980         dev_dbg(dd->dev, "init: digest size: %d\n",
 981                 crypto_ahash_digestsize(tfm));
 982
 983         switch (crypto_ahash_digestsize(tfm)) {
 984         case MD5_DIGEST_SIZE:
 985                 ctx->flags |= FLAGS_MODE_MD5;
 986                 bs = SHA1_BLOCK_SIZE;
 987                 break;
 988         case SHA1_DIGEST_SIZE:
 989                 ctx->flags |= FLAGS_MODE_SHA1;
 990                 bs = SHA1_BLOCK_SIZE;
 991                 break;
 992         case SHA224_DIGEST_SIZE:
 993                 ctx->flags |= FLAGS_MODE_SHA224;
 994                 bs = SHA224_BLOCK_SIZE;
 995                 break;
 996         case SHA256_DIGEST_SIZE:
 997                 ctx->flags |= FLAGS_MODE_SHA256;
 998                 bs = SHA256_BLOCK_SIZE;
 999                 break;
1000         case SHA384_DIGEST_SIZE:
1001                 ctx->flags |= FLAGS_MODE_SHA384;
1002                 bs = SHA384_BLOCK_SIZE;
1003                 break;
1004         case SHA512_DIGEST_SIZE:
1005                 ctx->flags |= FLAGS_MODE_SHA512;
1006                 bs = SHA512_BLOCK_SIZE;
1007                 break;
1008         }
1009
1010         ctx->bufcnt = 0;
1011         ctx->digcnt = 0;
1012         ctx->total = 0;
1013         ctx->offset = 0;
1014         ctx->buflen = BUFLEN;
1015
1016         if (tctx->flags & BIT(FLAGS_HMAC)) {
1017                 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1018                         struct omap_sham_hmac_ctx *bctx = tctx->base;
1019
1020                         memcpy(ctx->buffer, bctx->ipad, bs);
1021                         ctx->bufcnt = bs;
1022                 }
1023
1024                 ctx->flags |= BIT(FLAGS_HMAC);
1025         }
1026
1027         return 0;
1028
1029 }
1030
1031 static int omap_sham_update_req(struct omap_sham_dev *dd)
1032 {
1033         struct ahash_request *req = dd->req;
1034         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1035         int err;
1036         bool final = (ctx->flags & BIT(FLAGS_FINUP)) &&
1037                         !(dd->flags & BIT(FLAGS_HUGE));
1038
1039         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, final: %d",
1040                 ctx->total, ctx->digcnt, final);
1041
1042         if (ctx->total < get_block_size(ctx) ||
1043             ctx->total < dd->fallback_sz)
1044                 ctx->flags |= BIT(FLAGS_CPU);
1045
1046         if (ctx->flags & BIT(FLAGS_CPU))
1047                 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1048         else
1049                 err = omap_sham_xmit_dma(dd, ctx->total, final);
1050
1051         /* wait for dma completion before can take more data */
1052         dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
1053
1054         return err;
1055 }
1056
1057 static int omap_sham_final_req(struct omap_sham_dev *dd)
1058 {
1059         struct ahash_request *req = dd->req;
1060         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1061         int err = 0, use_dma = 1;
1062
1063         if (dd->flags & BIT(FLAGS_HUGE))
1064                 return 0;
1065
1066         if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1067                 /*
1068                  * faster to handle last block with cpu or
1069                  * use cpu when dma is not present.
1070                  */
1071                 use_dma = 0;
1072
1073         if (use_dma)
1074                 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1075         else
1076                 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1077
1078         ctx->bufcnt = 0;
1079
1080         dev_dbg(dd->dev, "final_req: err: %d\n", err);
1081
1082         return err;
1083 }
1084
1085 static int omap_sham_finish_hmac(struct ahash_request *req)
1086 {
1087         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1088         struct omap_sham_hmac_ctx *bctx = tctx->base;
1089         int bs = crypto_shash_blocksize(bctx->shash);
1090         int ds = crypto_shash_digestsize(bctx->shash);
1091         SHASH_DESC_ON_STACK(shash, bctx->shash);
1092
1093         shash->tfm = bctx->shash;
1094
1095         return crypto_shash_init(shash) ?:
1096                crypto_shash_update(shash, bctx->opad, bs) ?:
1097                crypto_shash_finup(shash, req->result, ds, req->result);
1098 }
1099
1100 static int omap_sham_finish(struct ahash_request *req)
1101 {
1102         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1103         struct omap_sham_dev *dd = ctx->dd;
1104         int err = 0;
1105
1106         if (ctx->digcnt) {
1107                 omap_sham_copy_ready_hash(req);
1108                 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1109                                 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1110                         err = omap_sham_finish_hmac(req);
1111         }
1112
1113         dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
1114
1115         return err;
1116 }
1117
1118 static void omap_sham_finish_req(struct ahash_request *req, int err)
1119 {
1120         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1121         struct omap_sham_dev *dd = ctx->dd;
1122
1123         if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1124                 free_pages((unsigned long)sg_virt(ctx->sg),
1125                            get_order(ctx->sg->length));
1126
1127         if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1128                 kfree(ctx->sg);
1129
1130         ctx->sg = NULL;
1131
1132         dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED));
1133
1134         if (dd->flags & BIT(FLAGS_HUGE)) {
1135                 dd->flags &= ~(BIT(FLAGS_CPU) | BIT(FLAGS_DMA_READY) |
1136                                 BIT(FLAGS_OUTPUT_READY) | BIT(FLAGS_HUGE));
1137                 omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1138                 if (ctx->op == OP_UPDATE || (dd->flags & BIT(FLAGS_HUGE))) {
1139                         err = omap_sham_update_req(dd);
1140                         if (err != -EINPROGRESS &&
1141                             (ctx->flags & BIT(FLAGS_FINUP)))
1142                                 err = omap_sham_final_req(dd);
1143                 } else if (ctx->op == OP_FINAL) {
1144                         omap_sham_final_req(dd);
1145                 }
1146                 return;
1147         }
1148
1149         if (!err) {
1150                 dd->pdata->copy_hash(req, 1);
1151                 if (test_bit(FLAGS_FINAL, &dd->flags))
1152                         err = omap_sham_finish(req);
1153         } else {
1154                 ctx->flags |= BIT(FLAGS_ERROR);
1155         }
1156
1157         /* atomic operation is not needed here */
1158         dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1159                         BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1160
1161         pm_runtime_mark_last_busy(dd->dev);
1162         pm_runtime_put_autosuspend(dd->dev);
1163
1164         ctx->offset = 0;
1165
1166         if (req->base.complete)
1167                 req->base.complete(&req->base, err);
1168 }
1169
1170 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1171                                   struct ahash_request *req)
1172 {
1173         struct crypto_async_request *async_req, *backlog;
1174         struct omap_sham_reqctx *ctx;
1175         unsigned long flags;
1176         int err = 0, ret = 0;
1177
1178 retry:
1179         spin_lock_irqsave(&dd->lock, flags);
1180         if (req)
1181                 ret = ahash_enqueue_request(&dd->queue, req);
1182         if (test_bit(FLAGS_BUSY, &dd->flags)) {
1183                 spin_unlock_irqrestore(&dd->lock, flags);
1184                 return ret;
1185         }
1186         backlog = crypto_get_backlog(&dd->queue);
1187         async_req = crypto_dequeue_request(&dd->queue);
1188         if (async_req)
1189                 set_bit(FLAGS_BUSY, &dd->flags);
1190         spin_unlock_irqrestore(&dd->lock, flags);
1191
1192         if (!async_req)
1193                 return ret;
1194
1195         if (backlog)
1196                 backlog->complete(backlog, -EINPROGRESS);
1197
1198         req = ahash_request_cast(async_req);
1199         dd->req = req;
1200         ctx = ahash_request_ctx(req);
1201
1202         err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1203         if (err || !ctx->total)
1204                 goto err1;
1205
1206         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1207                                                 ctx->op, req->nbytes);
1208
1209         err = omap_sham_hw_init(dd);
1210         if (err)
1211                 goto err1;
1212
1213         if (ctx->digcnt)
1214                 /* request has changed - restore hash */
1215                 dd->pdata->copy_hash(req, 0);
1216
1217         if (ctx->op == OP_UPDATE || (dd->flags & BIT(FLAGS_HUGE))) {
1218                 err = omap_sham_update_req(dd);
1219                 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1220                         /* no final() after finup() */
1221                         err = omap_sham_final_req(dd);
1222         } else if (ctx->op == OP_FINAL) {
1223                 err = omap_sham_final_req(dd);
1224         }
1225 err1:
1226         dev_dbg(dd->dev, "exit, err: %d\n", err);
1227
1228         if (err != -EINPROGRESS) {
1229                 /* done_task will not finish it, so do it here */
1230                 omap_sham_finish_req(req, err);
1231                 req = NULL;
1232
1233                 /*
1234                  * Execute next request immediately if there is anything
1235                  * in queue.
1236                  */
1237                 goto retry;
1238         }
1239
1240         return ret;
1241 }
1242
1243 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1244 {
1245         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1246         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1247         struct omap_sham_dev *dd = tctx->dd;
1248
1249         ctx->op = op;
1250
1251         return omap_sham_handle_queue(dd, req);
1252 }
1253
1254 static int omap_sham_update(struct ahash_request *req)
1255 {
1256         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1257         struct omap_sham_dev *dd = ctx->dd;
1258
1259         if (!req->nbytes)
1260                 return 0;
1261
1262         if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1263                 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1264                                          0, req->nbytes, 0);
1265                 ctx->bufcnt += req->nbytes;
1266                 return 0;
1267         }
1268
1269         if (dd->polling_mode)
1270                 ctx->flags |= BIT(FLAGS_CPU);
1271
1272         return omap_sham_enqueue(req, OP_UPDATE);
1273 }
1274
1275 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1276                                   const u8 *data, unsigned int len, u8 *out)
1277 {
1278         SHASH_DESC_ON_STACK(shash, tfm);
1279
1280         shash->tfm = tfm;
1281
1282         return crypto_shash_digest(shash, data, len, out);
1283 }
1284
1285 static int omap_sham_final_shash(struct ahash_request *req)
1286 {
1287         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1288         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1289         int offset = 0;
1290
1291         /*
1292          * If we are running HMAC on limited hardware support, skip
1293          * the ipad in the beginning of the buffer if we are going for
1294          * software fallback algorithm.
1295          */
1296         if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1297             !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1298                 offset = get_block_size(ctx);
1299
1300         return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1301                                       ctx->buffer + offset,
1302                                       ctx->bufcnt - offset, req->result);
1303 }
1304
1305 static int omap_sham_final(struct ahash_request *req)
1306 {
1307         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1308
1309         ctx->flags |= BIT(FLAGS_FINUP);
1310
1311         if (ctx->flags & BIT(FLAGS_ERROR))
1312                 return 0; /* uncompleted hash is not needed */
1313
1314         /*
1315          * OMAP HW accel works only with buffers >= 9.
1316          * HMAC is always >= 9 because ipad == block size.
1317          * If buffersize is less than fallback_sz, we use fallback
1318          * SW encoding, as using DMA + HW in this case doesn't provide
1319          * any benefit.
1320          */
1321         if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz)
1322                 return omap_sham_final_shash(req);
1323         else if (ctx->bufcnt)
1324                 return omap_sham_enqueue(req, OP_FINAL);
1325
1326         /* copy ready hash (+ finalize hmac) */
1327         return omap_sham_finish(req);
1328 }
1329
1330 static int omap_sham_finup(struct ahash_request *req)
1331 {
1332         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1333         int err1, err2;
1334
1335         ctx->flags |= BIT(FLAGS_FINUP);
1336
1337         err1 = omap_sham_update(req);
1338         if (err1 == -EINPROGRESS || err1 == -EBUSY)
1339                 return err1;
1340         /*
1341          * final() has to be always called to cleanup resources
1342          * even if udpate() failed, except EINPROGRESS
1343          */
1344         err2 = omap_sham_final(req);
1345
1346         return err1 ?: err2;
1347 }
1348
1349 static int omap_sham_digest(struct ahash_request *req)
1350 {
1351         return omap_sham_init(req) ?: omap_sham_finup(req);
1352 }
1353
1354 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1355                       unsigned int keylen)
1356 {
1357         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1358         struct omap_sham_hmac_ctx *bctx = tctx->base;
1359         int bs = crypto_shash_blocksize(bctx->shash);
1360         int ds = crypto_shash_digestsize(bctx->shash);
1361         struct omap_sham_dev *dd = NULL, *tmp;
1362         int err, i;
1363
1364         spin_lock_bh(&sham.lock);
1365         if (!tctx->dd) {
1366                 list_for_each_entry(tmp, &sham.dev_list, list) {
1367                         dd = tmp;
1368                         break;
1369                 }
1370                 tctx->dd = dd;
1371         } else {
1372                 dd = tctx->dd;
1373         }
1374         spin_unlock_bh(&sham.lock);
1375
1376         err = crypto_shash_setkey(tctx->fallback, key, keylen);
1377         if (err)
1378                 return err;
1379
1380         if (keylen > bs) {
1381                 err = omap_sham_shash_digest(bctx->shash,
1382                                 crypto_shash_get_flags(bctx->shash),
1383                                 key, keylen, bctx->ipad);
1384                 if (err)
1385                         return err;
1386                 keylen = ds;
1387         } else {
1388                 memcpy(bctx->ipad, key, keylen);
1389         }
1390
1391         memset(bctx->ipad + keylen, 0, bs - keylen);
1392
1393         if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1394                 memcpy(bctx->opad, bctx->ipad, bs);
1395
1396                 for (i = 0; i < bs; i++) {
1397                         bctx->ipad[i] ^= HMAC_IPAD_VALUE;
1398                         bctx->opad[i] ^= HMAC_OPAD_VALUE;
1399                 }
1400         }
1401
1402         return err;
1403 }
1404
1405 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1406 {
1407         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1408         const char *alg_name = crypto_tfm_alg_name(tfm);
1409
1410         /* Allocate a fallback and abort if it failed. */
1411         tctx->fallback = crypto_alloc_shash(alg_name, 0,
1412                                             CRYPTO_ALG_NEED_FALLBACK);
1413         if (IS_ERR(tctx->fallback)) {
1414                 pr_err("omap-sham: fallback driver '%s' "
1415                                 "could not be loaded.\n", alg_name);
1416                 return PTR_ERR(tctx->fallback);
1417         }
1418
1419         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1420                                  sizeof(struct omap_sham_reqctx) + BUFLEN);
1421
1422         if (alg_base) {
1423                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1424                 tctx->flags |= BIT(FLAGS_HMAC);
1425                 bctx->shash = crypto_alloc_shash(alg_base, 0,
1426                                                 CRYPTO_ALG_NEED_FALLBACK);
1427                 if (IS_ERR(bctx->shash)) {
1428                         pr_err("omap-sham: base driver '%s' "
1429                                         "could not be loaded.\n", alg_base);
1430                         crypto_free_shash(tctx->fallback);
1431                         return PTR_ERR(bctx->shash);
1432                 }
1433
1434         }
1435
1436         return 0;
1437 }
1438
1439 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1440 {
1441         return omap_sham_cra_init_alg(tfm, NULL);
1442 }
1443
1444 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1445 {
1446         return omap_sham_cra_init_alg(tfm, "sha1");
1447 }
1448
1449 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1450 {
1451         return omap_sham_cra_init_alg(tfm, "sha224");
1452 }
1453
1454 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1455 {
1456         return omap_sham_cra_init_alg(tfm, "sha256");
1457 }
1458
1459 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1460 {
1461         return omap_sham_cra_init_alg(tfm, "md5");
1462 }
1463
1464 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1465 {
1466         return omap_sham_cra_init_alg(tfm, "sha384");
1467 }
1468
1469 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1470 {
1471         return omap_sham_cra_init_alg(tfm, "sha512");
1472 }
1473
1474 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1475 {
1476         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1477
1478         crypto_free_shash(tctx->fallback);
1479         tctx->fallback = NULL;
1480
1481         if (tctx->flags & BIT(FLAGS_HMAC)) {
1482                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1483                 crypto_free_shash(bctx->shash);
1484         }
1485 }
1486
1487 static int omap_sham_export(struct ahash_request *req, void *out)
1488 {
1489         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1490
1491         memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1492
1493         return 0;
1494 }
1495
1496 static int omap_sham_import(struct ahash_request *req, const void *in)
1497 {
1498         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1499         const struct omap_sham_reqctx *ctx_in = in;
1500
1501         memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1502
1503         return 0;
1504 }
1505
1506 static struct ahash_alg algs_sha1_md5[] = {
1507 {
1508         .init           = omap_sham_init,
1509         .update         = omap_sham_update,
1510         .final          = omap_sham_final,
1511         .finup          = omap_sham_finup,
1512         .digest         = omap_sham_digest,
1513         .halg.digestsize        = SHA1_DIGEST_SIZE,
1514         .halg.base      = {
1515                 .cra_name               = "sha1",
1516                 .cra_driver_name        = "omap-sha1",
1517                 .cra_priority           = 400,
1518                 .cra_flags              = CRYPTO_ALG_KERN_DRIVER_ONLY |
1519                                                 CRYPTO_ALG_ASYNC |
1520                                                 CRYPTO_ALG_NEED_FALLBACK,
1521                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1522                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1523                 .cra_alignmask          = OMAP_ALIGN_MASK,
1524                 .cra_module             = THIS_MODULE,
1525                 .cra_init               = omap_sham_cra_init,
1526                 .cra_exit               = omap_sham_cra_exit,
1527         }
1528 },
1529 {
1530         .init           = omap_sham_init,
1531         .update         = omap_sham_update,
1532         .final          = omap_sham_final,
1533         .finup          = omap_sham_finup,
1534         .digest         = omap_sham_digest,
1535         .halg.digestsize        = MD5_DIGEST_SIZE,
1536         .halg.base      = {
1537                 .cra_name               = "md5",
1538                 .cra_driver_name        = "omap-md5",
1539                 .cra_priority           = 400,
1540                 .cra_flags              = CRYPTO_ALG_KERN_DRIVER_ONLY |
1541                                                 CRYPTO_ALG_ASYNC |
1542                                                 CRYPTO_ALG_NEED_FALLBACK,
1543                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1544                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1545                 .cra_alignmask          = OMAP_ALIGN_MASK,
1546                 .cra_module             = THIS_MODULE,
1547                 .cra_init               = omap_sham_cra_init,
1548                 .cra_exit               = omap_sham_cra_exit,
1549         }
1550 },
1551 {
1552         .init           = omap_sham_init,
1553         .update         = omap_sham_update,
1554         .final          = omap_sham_final,
1555         .finup          = omap_sham_finup,
1556         .digest         = omap_sham_digest,
1557         .setkey         = omap_sham_setkey,
1558         .halg.digestsize        = SHA1_DIGEST_SIZE,
1559         .halg.base      = {
1560                 .cra_name               = "hmac(sha1)",
1561                 .cra_driver_name        = "omap-hmac-sha1",
1562                 .cra_priority           = 400,
1563                 .cra_flags              = CRYPTO_ALG_KERN_DRIVER_ONLY |
1564                                                 CRYPTO_ALG_ASYNC |
1565                                                 CRYPTO_ALG_NEED_FALLBACK,
1566                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1567                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1568                                         sizeof(struct omap_sham_hmac_ctx),
1569                 .cra_alignmask          = OMAP_ALIGN_MASK,
1570                 .cra_module             = THIS_MODULE,
1571                 .cra_init               = omap_sham_cra_sha1_init,
1572                 .cra_exit               = omap_sham_cra_exit,
1573         }
1574 },
1575 {
1576         .init           = omap_sham_init,
1577         .update         = omap_sham_update,
1578         .final          = omap_sham_final,
1579         .finup          = omap_sham_finup,
1580         .digest         = omap_sham_digest,
1581         .setkey         = omap_sham_setkey,
1582         .halg.digestsize        = MD5_DIGEST_SIZE,
1583         .halg.base      = {
1584                 .cra_name               = "hmac(md5)",
1585                 .cra_driver_name        = "omap-hmac-md5",
1586                 .cra_priority           = 400,
1587                 .cra_flags              = CRYPTO_ALG_KERN_DRIVER_ONLY |
1588                                                 CRYPTO_ALG_ASYNC |
1589                                                 CRYPTO_ALG_NEED_FALLBACK,
1590                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1591                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1592                                         sizeof(struct omap_sham_hmac_ctx),
1593                 .cra_alignmask          = OMAP_ALIGN_MASK,
1594                 .cra_module             = THIS_MODULE,
1595                 .cra_init               = omap_sham_cra_md5_init,
1596                 .cra_exit               = omap_sham_cra_exit,
1597         }
1598 }
1599 };
1600
1601 /* OMAP4 has some algs in addition to what OMAP2 has */
1602 static struct ahash_alg algs_sha224_sha256[] = {
1603 {
1604         .init           = omap_sham_init,
1605         .update         = omap_sham_update,
1606         .final          = omap_sham_final,
1607         .finup          = omap_sham_finup,
1608         .digest         = omap_sham_digest,
1609         .halg.digestsize        = SHA224_DIGEST_SIZE,
1610         .halg.base      = {
1611                 .cra_name               = "sha224",
1612                 .cra_driver_name        = "omap-sha224",
1613                 .cra_priority           = 400,
1614                 .cra_flags              = CRYPTO_ALG_ASYNC |
1615                                                 CRYPTO_ALG_NEED_FALLBACK,
1616                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1617                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1618                 .cra_alignmask          = OMAP_ALIGN_MASK,
1619                 .cra_module             = THIS_MODULE,
1620                 .cra_init               = omap_sham_cra_init,
1621                 .cra_exit               = omap_sham_cra_exit,
1622         }
1623 },
1624 {
1625         .init           = omap_sham_init,
1626         .update         = omap_sham_update,
1627         .final          = omap_sham_final,
1628         .finup          = omap_sham_finup,
1629         .digest         = omap_sham_digest,
1630         .halg.digestsize        = SHA256_DIGEST_SIZE,
1631         .halg.base      = {
1632                 .cra_name               = "sha256",
1633                 .cra_driver_name        = "omap-sha256",
1634                 .cra_priority           = 400,
1635                 .cra_flags              = CRYPTO_ALG_ASYNC |
1636                                                 CRYPTO_ALG_NEED_FALLBACK,
1637                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1638                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1639                 .cra_alignmask          = OMAP_ALIGN_MASK,
1640                 .cra_module             = THIS_MODULE,
1641                 .cra_init               = omap_sham_cra_init,
1642                 .cra_exit               = omap_sham_cra_exit,
1643         }
1644 },
1645 {
1646         .init           = omap_sham_init,
1647         .update         = omap_sham_update,
1648         .final          = omap_sham_final,
1649         .finup          = omap_sham_finup,
1650         .digest         = omap_sham_digest,
1651         .setkey         = omap_sham_setkey,
1652         .halg.digestsize        = SHA224_DIGEST_SIZE,
1653         .halg.base      = {
1654                 .cra_name               = "hmac(sha224)",
1655                 .cra_driver_name        = "omap-hmac-sha224",
1656                 .cra_priority           = 400,
1657                 .cra_flags              = CRYPTO_ALG_ASYNC |
1658                                                 CRYPTO_ALG_NEED_FALLBACK,
1659                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1660                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1661                                         sizeof(struct omap_sham_hmac_ctx),
1662                 .cra_alignmask          = OMAP_ALIGN_MASK,
1663                 .cra_module             = THIS_MODULE,
1664                 .cra_init               = omap_sham_cra_sha224_init,
1665                 .cra_exit               = omap_sham_cra_exit,
1666         }
1667 },
1668 {
1669         .init           = omap_sham_init,
1670         .update         = omap_sham_update,
1671         .final          = omap_sham_final,
1672         .finup          = omap_sham_finup,
1673         .digest         = omap_sham_digest,
1674         .setkey         = omap_sham_setkey,
1675         .halg.digestsize        = SHA256_DIGEST_SIZE,
1676         .halg.base      = {
1677                 .cra_name               = "hmac(sha256)",
1678                 .cra_driver_name        = "omap-hmac-sha256",
1679                 .cra_priority           = 400,
1680                 .cra_flags              = CRYPTO_ALG_ASYNC |
1681                                                 CRYPTO_ALG_NEED_FALLBACK,
1682                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1683                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1684                                         sizeof(struct omap_sham_hmac_ctx),
1685                 .cra_alignmask          = OMAP_ALIGN_MASK,
1686                 .cra_module             = THIS_MODULE,
1687                 .cra_init               = omap_sham_cra_sha256_init,
1688                 .cra_exit               = omap_sham_cra_exit,
1689         }
1690 },
1691 };
1692
1693 static struct ahash_alg algs_sha384_sha512[] = {
1694 {
1695         .init           = omap_sham_init,
1696         .update         = omap_sham_update,
1697         .final          = omap_sham_final,
1698         .finup          = omap_sham_finup,
1699         .digest         = omap_sham_digest,
1700         .halg.digestsize        = SHA384_DIGEST_SIZE,
1701         .halg.base      = {
1702                 .cra_name               = "sha384",
1703                 .cra_driver_name        = "omap-sha384",
1704                 .cra_priority           = 400,
1705                 .cra_flags              = CRYPTO_ALG_ASYNC |
1706                                                 CRYPTO_ALG_NEED_FALLBACK,
1707                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1708                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1709                 .cra_alignmask          = OMAP_ALIGN_MASK,
1710                 .cra_module             = THIS_MODULE,
1711                 .cra_init               = omap_sham_cra_init,
1712                 .cra_exit               = omap_sham_cra_exit,
1713         }
1714 },
1715 {
1716         .init           = omap_sham_init,
1717         .update         = omap_sham_update,
1718         .final          = omap_sham_final,
1719         .finup          = omap_sham_finup,
1720         .digest         = omap_sham_digest,
1721         .halg.digestsize        = SHA512_DIGEST_SIZE,
1722         .halg.base      = {
1723                 .cra_name               = "sha512",
1724                 .cra_driver_name        = "omap-sha512",
1725                 .cra_priority           = 400,
1726                 .cra_flags              = CRYPTO_ALG_ASYNC |
1727                                                 CRYPTO_ALG_NEED_FALLBACK,
1728                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1729                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1730                 .cra_alignmask          = OMAP_ALIGN_MASK,
1731                 .cra_module             = THIS_MODULE,
1732                 .cra_init               = omap_sham_cra_init,
1733                 .cra_exit               = omap_sham_cra_exit,
1734         }
1735 },
1736 {
1737         .init           = omap_sham_init,
1738         .update         = omap_sham_update,
1739         .final          = omap_sham_final,
1740         .finup          = omap_sham_finup,
1741         .digest         = omap_sham_digest,
1742         .setkey         = omap_sham_setkey,
1743         .halg.digestsize        = SHA384_DIGEST_SIZE,
1744         .halg.base      = {
1745                 .cra_name               = "hmac(sha384)",
1746                 .cra_driver_name        = "omap-hmac-sha384",
1747                 .cra_priority           = 400,
1748                 .cra_flags              = CRYPTO_ALG_ASYNC |
1749                                                 CRYPTO_ALG_NEED_FALLBACK,
1750                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1751                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1752                                         sizeof(struct omap_sham_hmac_ctx),
1753                 .cra_alignmask          = OMAP_ALIGN_MASK,
1754                 .cra_module             = THIS_MODULE,
1755                 .cra_init               = omap_sham_cra_sha384_init,
1756                 .cra_exit               = omap_sham_cra_exit,
1757         }
1758 },
1759 {
1760         .init           = omap_sham_init,
1761         .update         = omap_sham_update,
1762         .final          = omap_sham_final,
1763         .finup          = omap_sham_finup,
1764         .digest         = omap_sham_digest,
1765         .setkey         = omap_sham_setkey,
1766         .halg.digestsize        = SHA512_DIGEST_SIZE,
1767         .halg.base      = {
1768                 .cra_name               = "hmac(sha512)",
1769                 .cra_driver_name        = "omap-hmac-sha512",
1770                 .cra_priority           = 400,
1771                 .cra_flags              = CRYPTO_ALG_ASYNC |
1772                                                 CRYPTO_ALG_NEED_FALLBACK,
1773                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1774                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1775                                         sizeof(struct omap_sham_hmac_ctx),
1776                 .cra_alignmask          = OMAP_ALIGN_MASK,
1777                 .cra_module             = THIS_MODULE,
1778                 .cra_init               = omap_sham_cra_sha512_init,
1779                 .cra_exit               = omap_sham_cra_exit,
1780         }
1781 },
1782 };
1783
1784 static void omap_sham_done_task(unsigned long data)
1785 {
1786         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1787         int err = 0;
1788
1789         dev_dbg(dd->dev, "%s: flags=%lx\n", __func__, dd->flags);
1790
1791         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1792                 omap_sham_handle_queue(dd, NULL);
1793                 return;
1794         }
1795
1796         if (test_bit(FLAGS_CPU, &dd->flags)) {
1797                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1798                         goto finish;
1799         } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1800                 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1801                         omap_sham_update_dma_stop(dd);
1802                         if (dd->err) {
1803                                 err = dd->err;
1804                                 goto finish;
1805                         }
1806                 }
1807                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1808                         /* hash or semi-hash ready */
1809                         clear_bit(FLAGS_DMA_READY, &dd->flags);
1810                         goto finish;
1811                 }
1812         }
1813
1814         return;
1815
1816 finish:
1817         dev_dbg(dd->dev, "update done: err: %d\n", err);
1818         /* finish curent request */
1819         omap_sham_finish_req(dd->req, err);
1820
1821         /* If we are not busy, process next req */
1822         if (!test_bit(FLAGS_BUSY, &dd->flags))
1823                 omap_sham_handle_queue(dd, NULL);
1824 }
1825
1826 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1827 {
1828         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1829                 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1830         } else {
1831                 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1832                 tasklet_schedule(&dd->done_task);
1833         }
1834
1835         return IRQ_HANDLED;
1836 }
1837
1838 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1839 {
1840         struct omap_sham_dev *dd = dev_id;
1841
1842         if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1843                 /* final -> allow device to go to power-saving mode */
1844                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1845
1846         omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1847                                  SHA_REG_CTRL_OUTPUT_READY);
1848         omap_sham_read(dd, SHA_REG_CTRL);
1849
1850         return omap_sham_irq_common(dd);
1851 }
1852
1853 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1854 {
1855         struct omap_sham_dev *dd = dev_id;
1856
1857         omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1858
1859         return omap_sham_irq_common(dd);
1860 }
1861
1862 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1863         {
1864                 .algs_list      = algs_sha1_md5,
1865                 .size           = ARRAY_SIZE(algs_sha1_md5),
1866         },
1867 };
1868
1869 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1870         .algs_info      = omap_sham_algs_info_omap2,
1871         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1872         .flags          = BIT(FLAGS_BE32_SHA1),
1873         .digest_size    = SHA1_DIGEST_SIZE,
1874         .copy_hash      = omap_sham_copy_hash_omap2,
1875         .write_ctrl     = omap_sham_write_ctrl_omap2,
1876         .trigger        = omap_sham_trigger_omap2,
1877         .poll_irq       = omap_sham_poll_irq_omap2,
1878         .intr_hdlr      = omap_sham_irq_omap2,
1879         .idigest_ofs    = 0x00,
1880         .din_ofs        = 0x1c,
1881         .digcnt_ofs     = 0x14,
1882         .rev_ofs        = 0x5c,
1883         .mask_ofs       = 0x60,
1884         .sysstatus_ofs  = 0x64,
1885         .major_mask     = 0xf0,
1886         .major_shift    = 4,
1887         .minor_mask     = 0x0f,
1888         .minor_shift    = 0,
1889 };
1890
1891 #ifdef CONFIG_OF
1892 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1893         {
1894                 .algs_list      = algs_sha1_md5,
1895                 .size           = ARRAY_SIZE(algs_sha1_md5),
1896         },
1897         {
1898                 .algs_list      = algs_sha224_sha256,
1899                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1900         },
1901 };
1902
1903 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1904         .algs_info      = omap_sham_algs_info_omap4,
1905         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1906         .flags          = BIT(FLAGS_AUTO_XOR),
1907         .digest_size    = SHA256_DIGEST_SIZE,
1908         .copy_hash      = omap_sham_copy_hash_omap4,
1909         .write_ctrl     = omap_sham_write_ctrl_omap4,
1910         .trigger        = omap_sham_trigger_omap4,
1911         .poll_irq       = omap_sham_poll_irq_omap4,
1912         .intr_hdlr      = omap_sham_irq_omap4,
1913         .idigest_ofs    = 0x020,
1914         .odigest_ofs    = 0x0,
1915         .din_ofs        = 0x080,
1916         .digcnt_ofs     = 0x040,
1917         .rev_ofs        = 0x100,
1918         .mask_ofs       = 0x110,
1919         .sysstatus_ofs  = 0x114,
1920         .mode_ofs       = 0x44,
1921         .length_ofs     = 0x48,
1922         .major_mask     = 0x0700,
1923         .major_shift    = 8,
1924         .minor_mask     = 0x003f,
1925         .minor_shift    = 0,
1926 };
1927
1928 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1929         {
1930                 .algs_list      = algs_sha1_md5,
1931                 .size           = ARRAY_SIZE(algs_sha1_md5),
1932         },
1933         {
1934                 .algs_list      = algs_sha224_sha256,
1935                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1936         },
1937         {
1938                 .algs_list      = algs_sha384_sha512,
1939                 .size           = ARRAY_SIZE(algs_sha384_sha512),
1940         },
1941 };
1942
1943 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1944         .algs_info      = omap_sham_algs_info_omap5,
1945         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1946         .flags          = BIT(FLAGS_AUTO_XOR),
1947         .digest_size    = SHA512_DIGEST_SIZE,
1948         .copy_hash      = omap_sham_copy_hash_omap4,
1949         .write_ctrl     = omap_sham_write_ctrl_omap4,
1950         .trigger        = omap_sham_trigger_omap4,
1951         .poll_irq       = omap_sham_poll_irq_omap4,
1952         .intr_hdlr      = omap_sham_irq_omap4,
1953         .idigest_ofs    = 0x240,
1954         .odigest_ofs    = 0x200,
1955         .din_ofs        = 0x080,
1956         .digcnt_ofs     = 0x280,
1957         .rev_ofs        = 0x100,
1958         .mask_ofs       = 0x110,
1959         .sysstatus_ofs  = 0x114,
1960         .mode_ofs       = 0x284,
1961         .length_ofs     = 0x288,
1962         .major_mask     = 0x0700,
1963         .major_shift    = 8,
1964         .minor_mask     = 0x003f,
1965         .minor_shift    = 0,
1966 };
1967
1968 static const struct of_device_id omap_sham_of_match[] = {
1969         {
1970                 .compatible     = "ti,omap2-sham",
1971                 .data           = &omap_sham_pdata_omap2,
1972         },
1973         {
1974                 .compatible     = "ti,omap3-sham",
1975                 .data           = &omap_sham_pdata_omap2,
1976         },
1977         {
1978                 .compatible     = "ti,omap4-sham",
1979                 .data           = &omap_sham_pdata_omap4,
1980         },
1981         {
1982                 .compatible     = "ti,omap5-sham",
1983                 .data           = &omap_sham_pdata_omap5,
1984         },
1985         {},
1986 };
1987 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1988
1989 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1990                 struct device *dev, struct resource *res)
1991 {
1992         struct device_node *node = dev->of_node;
1993         int err = 0;
1994
1995         dd->pdata = of_device_get_match_data(dev);
1996         if (!dd->pdata) {
1997                 dev_err(dev, "no compatible OF match\n");
1998                 err = -EINVAL;
1999                 goto err;
2000         }
2001
2002         err = of_address_to_resource(node, 0, res);
2003         if (err < 0) {
2004                 dev_err(dev, "can't translate OF node address\n");
2005                 err = -EINVAL;
2006                 goto err;
2007         }
2008
2009         dd->irq = irq_of_parse_and_map(node, 0);
2010         if (!dd->irq) {
2011                 dev_err(dev, "can't translate OF irq value\n");
2012                 err = -EINVAL;
2013                 goto err;
2014         }
2015
2016 err:
2017         return err;
2018 }
2019 #else
2020 static const struct of_device_id omap_sham_of_match[] = {
2021         {},
2022 };
2023
2024 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
2025                 struct device *dev, struct resource *res)
2026 {
2027         return -EINVAL;
2028 }
2029 #endif
2030
2031 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
2032                 struct platform_device *pdev, struct resource *res)
2033 {
2034         struct device *dev = &pdev->dev;
2035         struct resource *r;
2036         int err = 0;
2037
2038         /* Get the base address */
2039         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2040         if (!r) {
2041                 dev_err(dev, "no MEM resource info\n");
2042                 err = -ENODEV;
2043                 goto err;
2044         }
2045         memcpy(res, r, sizeof(*res));
2046
2047         /* Get the IRQ */
2048         dd->irq = platform_get_irq(pdev, 0);
2049         if (dd->irq < 0) {
2050                 err = dd->irq;
2051                 goto err;
2052         }
2053
2054         /* Only OMAP2/3 can be non-DT */
2055         dd->pdata = &omap_sham_pdata_omap2;
2056
2057 err:
2058         return err;
2059 }
2060
2061 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
2062                              char *buf)
2063 {
2064         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2065
2066         return sprintf(buf, "%d\n", dd->fallback_sz);
2067 }
2068
2069 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
2070                               const char *buf, size_t size)
2071 {
2072         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2073         ssize_t status;
2074         long value;
2075
2076         status = kstrtol(buf, 0, &value);
2077         if (status)
2078                 return status;
2079
2080         /* HW accelerator only works with buffers > 9 */
2081         if (value < 9) {
2082                 dev_err(dev, "minimum fallback size 9\n");
2083                 return -EINVAL;
2084         }
2085
2086         dd->fallback_sz = value;
2087
2088         return size;
2089 }
2090
2091 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
2092                               char *buf)
2093 {
2094         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2095
2096         return sprintf(buf, "%d\n", dd->queue.max_qlen);
2097 }
2098
2099 static ssize_t queue_len_store(struct device *dev,
2100                                struct device_attribute *attr, const char *buf,
2101                                size_t size)
2102 {
2103         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2104         ssize_t status;
2105         long value;
2106         unsigned long flags;
2107
2108         status = kstrtol(buf, 0, &value);
2109         if (status)
2110                 return status;
2111
2112         if (value < 1)
2113                 return -EINVAL;
2114
2115         /*
2116          * Changing the queue size in fly is safe, if size becomes smaller
2117          * than current size, it will just not accept new entries until
2118          * it has shrank enough.
2119          */
2120         spin_lock_irqsave(&dd->lock, flags);
2121         dd->queue.max_qlen = value;
2122         spin_unlock_irqrestore(&dd->lock, flags);
2123
2124         return size;
2125 }
2126
2127 static DEVICE_ATTR_RW(queue_len);
2128 static DEVICE_ATTR_RW(fallback);
2129
2130 static struct attribute *omap_sham_attrs[] = {
2131         &dev_attr_queue_len.attr,
2132         &dev_attr_fallback.attr,
2133         NULL,
2134 };
2135
2136 static struct attribute_group omap_sham_attr_group = {
2137         .attrs = omap_sham_attrs,
2138 };
2139
2140 static int omap_sham_probe(struct platform_device *pdev)
2141 {
2142         struct omap_sham_dev *dd;
2143         struct device *dev = &pdev->dev;
2144         struct resource res;
2145         dma_cap_mask_t mask;
2146         int err, i, j;
2147         u32 rev;
2148
2149         dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2150         if (dd == NULL) {
2151                 dev_err(dev, "unable to alloc data struct.\n");
2152                 err = -ENOMEM;
2153                 goto data_err;
2154         }
2155         dd->dev = dev;
2156         platform_set_drvdata(pdev, dd);
2157
2158         INIT_LIST_HEAD(&dd->list);
2159         spin_lock_init(&dd->lock);
2160         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2161         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2162
2163         err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2164                                omap_sham_get_res_pdev(dd, pdev, &res);
2165         if (err)
2166                 goto data_err;
2167
2168         dd->io_base = devm_ioremap_resource(dev, &res);
2169         if (IS_ERR(dd->io_base)) {
2170                 err = PTR_ERR(dd->io_base);
2171                 goto data_err;
2172         }
2173         dd->phys_base = res.start;
2174
2175         err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2176                                IRQF_TRIGGER_NONE, dev_name(dev), dd);
2177         if (err) {
2178                 dev_err(dev, "unable to request irq %d, err = %d\n",
2179                         dd->irq, err);
2180                 goto data_err;
2181         }
2182
2183         dma_cap_zero(mask);
2184         dma_cap_set(DMA_SLAVE, mask);
2185
2186         dd->dma_lch = dma_request_chan(dev, "rx");
2187         if (IS_ERR(dd->dma_lch)) {
2188                 err = PTR_ERR(dd->dma_lch);
2189                 if (err == -EPROBE_DEFER)
2190                         goto data_err;
2191
2192                 dd->polling_mode = 1;
2193                 dev_dbg(dev, "using polling mode instead of dma\n");
2194         }
2195
2196         dd->flags |= dd->pdata->flags;
2197
2198         pm_runtime_use_autosuspend(dev);
2199         pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2200
2201         dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD;
2202
2203         pm_runtime_enable(dev);
2204         pm_runtime_irq_safe(dev);
2205
2206         err = pm_runtime_get_sync(dev);
2207         if (err < 0) {
2208                 dev_err(dev, "failed to get sync: %d\n", err);
2209                 goto err_pm;
2210         }
2211
2212         rev = omap_sham_read(dd, SHA_REG_REV(dd));
2213         pm_runtime_put_sync(&pdev->dev);
2214
2215         dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2216                 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2217                 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2218
2219         spin_lock(&sham.lock);
2220         list_add_tail(&dd->list, &sham.dev_list);
2221         spin_unlock(&sham.lock);
2222
2223         for (i = 0; i < dd->pdata->algs_info_size; i++) {
2224                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2225                         struct ahash_alg *alg;
2226
2227                         alg = &dd->pdata->algs_info[i].algs_list[j];
2228                         alg->export = omap_sham_export;
2229                         alg->import = omap_sham_import;
2230                         alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2231                                               BUFLEN;
2232                         err = crypto_register_ahash(alg);
2233                         if (err)
2234                                 goto err_algs;
2235
2236                         dd->pdata->algs_info[i].registered++;
2237                 }
2238         }
2239
2240         err = sysfs_create_group(&dev->kobj, &omap_sham_attr_group);
2241         if (err) {
2242                 dev_err(dev, "could not create sysfs device attrs\n");
2243                 goto err_algs;
2244         }
2245
2246         return 0;
2247
2248 err_algs:
2249         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2250                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2251                         crypto_unregister_ahash(
2252                                         &dd->pdata->algs_info[i].algs_list[j]);
2253 err_pm:
2254         pm_runtime_disable(dev);
2255         if (!dd->polling_mode)
2256                 dma_release_channel(dd->dma_lch);
2257 data_err:
2258         dev_err(dev, "initialization failed.\n");
2259
2260         return err;
2261 }
2262
2263 static int omap_sham_remove(struct platform_device *pdev)
2264 {
2265         struct omap_sham_dev *dd;
2266         int i, j;
2267
2268         dd = platform_get_drvdata(pdev);
2269         if (!dd)
2270                 return -ENODEV;
2271         spin_lock(&sham.lock);
2272         list_del(&dd->list);
2273         spin_unlock(&sham.lock);
2274         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2275                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2276                         crypto_unregister_ahash(
2277                                         &dd->pdata->algs_info[i].algs_list[j]);
2278         tasklet_kill(&dd->done_task);
2279         pm_runtime_disable(&pdev->dev);
2280
2281         if (!dd->polling_mode)
2282                 dma_release_channel(dd->dma_lch);
2283
2284         sysfs_remove_group(&dd->dev->kobj, &omap_sham_attr_group);
2285
2286         return 0;
2287 }
2288
2289 #ifdef CONFIG_PM_SLEEP
2290 static int omap_sham_suspend(struct device *dev)
2291 {
2292         pm_runtime_put_sync(dev);
2293         return 0;
2294 }
2295
2296 static int omap_sham_resume(struct device *dev)
2297 {
2298         int err = pm_runtime_get_sync(dev);
2299         if (err < 0) {
2300                 dev_err(dev, "failed to get sync: %d\n", err);
2301                 return err;
2302         }
2303         return 0;
2304 }
2305 #endif
2306
2307 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2308
2309 static struct platform_driver omap_sham_driver = {
2310         .probe  = omap_sham_probe,
2311         .remove = omap_sham_remove,
2312         .driver = {
2313                 .name   = "omap-sham",
2314                 .pm     = &omap_sham_pm_ops,
2315                 .of_match_table = omap_sham_of_match,
2316         },
2317 };
2318
2319 module_platform_driver(omap_sham_driver);
2320
2321 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2322 MODULE_LICENSE("GPL v2");
2323 MODULE_AUTHOR("Dmitry Kasatkin");
2324 MODULE_ALIAS("platform:omap-sham");