drivers/crypto/ixp4xx_crypto.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Intel IXP4xx NPE-C crypto driver
   4  *
   5  * Copyright (C) 2008 Christian Hohnstaedt <chohnstaedt@innominate.com>
   6  */
   7
   8 #include <linux/platform_device.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/dmapool.h>
  11 #include <linux/crypto.h>
  12 #include <linux/kernel.h>
  13 #include <linux/rtnetlink.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/gfp.h>
  17 #include <linux/module.h>
  18
  19 #include <crypto/ctr.h>
  20 #include <crypto/des.h>
  21 #include <crypto/aes.h>
  22 #include <crypto/hmac.h>
  23 #include <crypto/sha.h>
  24 #include <crypto/algapi.h>
  25 #include <crypto/internal/aead.h>
  26 #include <crypto/authenc.h>
  27 #include <crypto/scatterwalk.h>
  28
  29 #include <linux/soc/ixp4xx/npe.h>
  30 #include <linux/soc/ixp4xx/qmgr.h>
  31
  32 #define MAX_KEYLEN 32
  33
  34 /* hash: cfgword + 2 * digestlen; crypt: keylen + cfgword */
  35 #define NPE_CTX_LEN 80
  36 #define AES_BLOCK128 16
  37
  38 #define NPE_OP_HASH_VERIFY   0x01
  39 #define NPE_OP_CCM_ENABLE    0x04
  40 #define NPE_OP_CRYPT_ENABLE  0x08
  41 #define NPE_OP_HASH_ENABLE   0x10
  42 #define NPE_OP_NOT_IN_PLACE  0x20
  43 #define NPE_OP_HMAC_DISABLE  0x40
  44 #define NPE_OP_CRYPT_ENCRYPT 0x80
  45
  46 #define NPE_OP_CCM_GEN_MIC   0xcc
  47 #define NPE_OP_HASH_GEN_ICV  0x50
  48 #define NPE_OP_ENC_GEN_KEY   0xc9
  49
  50 #define MOD_ECB     0x0000
  51 #define MOD_CTR     0x1000
  52 #define MOD_CBC_ENC 0x2000
  53 #define MOD_CBC_DEC 0x3000
  54 #define MOD_CCM_ENC 0x4000
  55 #define MOD_CCM_DEC 0x5000
  56
  57 #define KEYLEN_128  4
  58 #define KEYLEN_192  6
  59 #define KEYLEN_256  8
  60
  61 #define CIPH_DECR   0x0000
  62 #define CIPH_ENCR   0x0400
  63
  64 #define MOD_DES     0x0000
  65 #define MOD_TDEA2   0x0100
  66 #define MOD_3DES   0x0200
  67 #define MOD_AES     0x0800
  68 #define MOD_AES128  (0x0800 | KEYLEN_128)
  69 #define MOD_AES192  (0x0900 | KEYLEN_192)
  70 #define MOD_AES256  (0x0a00 | KEYLEN_256)
  71
  72 #define MAX_IVLEN   16
  73 #define NPE_ID      2  /* NPE C */
  74 #define NPE_QLEN    16
  75 /* Space for registering when the first
  76  * NPE_QLEN crypt_ctl are busy */
  77 #define NPE_QLEN_TOTAL 64
  78
  79 #define SEND_QID    29
  80 #define RECV_QID    30
  81
  82 #define CTL_FLAG_UNUSED         0x0000
  83 #define CTL_FLAG_USED           0x1000
  84 #define CTL_FLAG_PERFORM_ABLK   0x0001
  85 #define CTL_FLAG_GEN_ICV        0x0002
  86 #define CTL_FLAG_GEN_REVAES     0x0004
  87 #define CTL_FLAG_PERFORM_AEAD   0x0008
  88 #define CTL_FLAG_MASK           0x000f
  89
  90 #define HMAC_PAD_BLOCKLEN SHA1_BLOCK_SIZE
  91
  92 #define MD5_DIGEST_SIZE   16
  93
  94 struct buffer_desc {
  95         u32 phys_next;
  96 #ifdef __ARMEB__
  97         u16 buf_len;
  98         u16 pkt_len;
  99 #else
 100         u16 pkt_len;
 101         u16 buf_len;
 102 #endif
 103         u32 phys_addr;
 104         u32 __reserved[4];
 105         struct buffer_desc *next;
 106         enum dma_data_direction dir;
 107 };
 108
 109 struct crypt_ctl {
 110 #ifdef __ARMEB__
 111         u8 mode;                /* NPE_OP_*  operation mode */
 112         u8 init_len;
 113         u16 reserved;
 114 #else
 115         u16 reserved;
 116         u8 init_len;
 117         u8 mode;                /* NPE_OP_*  operation mode */
 118 #endif
 119         u8 iv[MAX_IVLEN];       /* IV for CBC mode or CTR IV for CTR mode */
 120         u32 icv_rev_aes;        /* icv or rev aes */
 121         u32 src_buf;
 122         u32 dst_buf;
 123 #ifdef __ARMEB__
 124         u16 auth_offs;          /* Authentication start offset */
 125         u16 auth_len;           /* Authentication data length */
 126         u16 crypt_offs;         /* Cryption start offset */
 127         u16 crypt_len;          /* Cryption data length */
 128 #else
 129         u16 auth_len;           /* Authentication data length */
 130         u16 auth_offs;          /* Authentication start offset */
 131         u16 crypt_len;          /* Cryption data length */
 132         u16 crypt_offs;         /* Cryption start offset */
 133 #endif
 134         u32 aadAddr;            /* Additional Auth Data Addr for CCM mode */
 135         u32 crypto_ctx;         /* NPE Crypto Param structure address */
 136
 137         /* Used by Host: 4*4 bytes*/
 138         unsigned ctl_flags;
 139         union {
 140                 struct ablkcipher_request *ablk_req;
 141                 struct aead_request *aead_req;
 142                 struct crypto_tfm *tfm;
 143         } data;
 144         struct buffer_desc *regist_buf;
 145         u8 *regist_ptr;
 146 };
 147
 148 struct ablk_ctx {
 149         struct buffer_desc *src;
 150         struct buffer_desc *dst;
 151 };
 152
 153 struct aead_ctx {
 154         struct buffer_desc *src;
 155         struct buffer_desc *dst;
 156         struct scatterlist ivlist;
 157         /* used when the hmac is not on one sg entry */
 158         u8 *hmac_virt;
 159         int encrypt;
 160 };
 161
 162 struct ix_hash_algo {
 163         u32 cfgword;
 164         unsigned char *icv;
 165 };
 166
 167 struct ix_sa_dir {
 168         unsigned char *npe_ctx;
 169         dma_addr_t npe_ctx_phys;
 170         int npe_ctx_idx;
 171         u8 npe_mode;
 172 };
 173
 174 struct ixp_ctx {
 175         struct ix_sa_dir encrypt;
 176         struct ix_sa_dir decrypt;
 177         int authkey_len;
 178         u8 authkey[MAX_KEYLEN];
 179         int enckey_len;
 180         u8 enckey[MAX_KEYLEN];
 181         u8 salt[MAX_IVLEN];
 182         u8 nonce[CTR_RFC3686_NONCE_SIZE];
 183         unsigned salted;
 184         atomic_t configuring;
 185         struct completion completion;
 186 };
 187
 188 struct ixp_alg {
 189         struct crypto_alg crypto;
 190         const struct ix_hash_algo *hash;
 191         u32 cfg_enc;
 192         u32 cfg_dec;
 193
 194         int registered;
 195 };
 196
 197 struct ixp_aead_alg {
 198         struct aead_alg crypto;
 199         const struct ix_hash_algo *hash;
 200         u32 cfg_enc;
 201         u32 cfg_dec;
 202
 203         int registered;
 204 };
 205
 206 static const struct ix_hash_algo hash_alg_md5 = {
 207         .cfgword        = 0xAA010004,
 208         .icv            = "\x01\x23\x45\x67\x89\xAB\xCD\xEF"
 209                           "\xFE\xDC\xBA\x98\x76\x54\x32\x10",
 210 };
 211 static const struct ix_hash_algo hash_alg_sha1 = {
 212         .cfgword        = 0x00000005,
 213         .icv            = "\x67\x45\x23\x01\xEF\xCD\xAB\x89\x98\xBA"
 214                           "\xDC\xFE\x10\x32\x54\x76\xC3\xD2\xE1\xF0",
 215 };
 216
 217 static struct npe *npe_c;
 218 static struct dma_pool *buffer_pool = NULL;
 219 static struct dma_pool *ctx_pool = NULL;
 220
 221 static struct crypt_ctl *crypt_virt = NULL;
 222 static dma_addr_t crypt_phys;
 223
 224 static int support_aes = 1;
 225
 226 #define DRIVER_NAME "ixp4xx_crypto"
 227
 228 static struct platform_device *pdev;
 229
 230 static inline dma_addr_t crypt_virt2phys(struct crypt_ctl *virt)
 231 {
 232         return crypt_phys + (virt - crypt_virt) * sizeof(struct crypt_ctl);
 233 }
 234
 235 static inline struct crypt_ctl *crypt_phys2virt(dma_addr_t phys)
 236 {
 237         return crypt_virt + (phys - crypt_phys) / sizeof(struct crypt_ctl);
 238 }
 239
 240 static inline u32 cipher_cfg_enc(struct crypto_tfm *tfm)
 241 {
 242         return container_of(tfm->__crt_alg, struct ixp_alg,crypto)->cfg_enc;
 243 }
 244
 245 static inline u32 cipher_cfg_dec(struct crypto_tfm *tfm)
 246 {
 247         return container_of(tfm->__crt_alg, struct ixp_alg,crypto)->cfg_dec;
 248 }
 249
 250 static inline const struct ix_hash_algo *ix_hash(struct crypto_tfm *tfm)
 251 {
 252         return container_of(tfm->__crt_alg, struct ixp_alg, crypto)->hash;
 253 }
 254
 255 static int setup_crypt_desc(void)
 256 {
 257         struct device *dev = &pdev->dev;
 258         BUILD_BUG_ON(sizeof(struct crypt_ctl) != 64);
 259         crypt_virt = dma_alloc_coherent(dev,
 260                                         NPE_QLEN * sizeof(struct crypt_ctl),
 261                                         &crypt_phys, GFP_ATOMIC);
 262         if (!crypt_virt)
 263                 return -ENOMEM;
 264         return 0;
 265 }
 266
 267 static spinlock_t desc_lock;
 268 static struct crypt_ctl *get_crypt_desc(void)
 269 {
 270         int i;
 271         static int idx = 0;
 272         unsigned long flags;
 273
 274         spin_lock_irqsave(&desc_lock, flags);
 275
 276         if (unlikely(!crypt_virt))
 277                 setup_crypt_desc();
 278         if (unlikely(!crypt_virt)) {
 279                 spin_unlock_irqrestore(&desc_lock, flags);
 280                 return NULL;
 281         }
 282         i = idx;
 283         if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
 284                 if (++idx >= NPE_QLEN)
 285                         idx = 0;
 286                 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
 287                 spin_unlock_irqrestore(&desc_lock, flags);
 288                 return crypt_virt +i;
 289         } else {
 290                 spin_unlock_irqrestore(&desc_lock, flags);
 291                 return NULL;
 292         }
 293 }
 294
 295 static spinlock_t emerg_lock;
 296 static struct crypt_ctl *get_crypt_desc_emerg(void)
 297 {
 298         int i;
 299         static int idx = NPE_QLEN;
 300         struct crypt_ctl *desc;
 301         unsigned long flags;
 302
 303         desc = get_crypt_desc();
 304         if (desc)
 305                 return desc;
 306         if (unlikely(!crypt_virt))
 307                 return NULL;
 308
 309         spin_lock_irqsave(&emerg_lock, flags);
 310         i = idx;
 311         if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
 312                 if (++idx >= NPE_QLEN_TOTAL)
 313                         idx = NPE_QLEN;
 314                 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
 315                 spin_unlock_irqrestore(&emerg_lock, flags);
 316                 return crypt_virt +i;
 317         } else {
 318                 spin_unlock_irqrestore(&emerg_lock, flags);
 319                 return NULL;
 320         }
 321 }
 322
 323 static void free_buf_chain(struct device *dev, struct buffer_desc *buf,u32 phys)
 324 {
 325         while (buf) {
 326                 struct buffer_desc *buf1;
 327                 u32 phys1;
 328
 329                 buf1 = buf->next;
 330                 phys1 = buf->phys_next;
 331                 dma_unmap_single(dev, buf->phys_next, buf->buf_len, buf->dir);
 332                 dma_pool_free(buffer_pool, buf, phys);
 333                 buf = buf1;
 334                 phys = phys1;
 335         }
 336 }
 337
 338 static struct tasklet_struct crypto_done_tasklet;
 339
 340 static void finish_scattered_hmac(struct crypt_ctl *crypt)
 341 {
 342         struct aead_request *req = crypt->data.aead_req;
 343         struct aead_ctx *req_ctx = aead_request_ctx(req);
 344         struct crypto_aead *tfm = crypto_aead_reqtfm(req);
 345         int authsize = crypto_aead_authsize(tfm);
 346         int decryptlen = req->assoclen + req->cryptlen - authsize;
 347
 348         if (req_ctx->encrypt) {
 349                 scatterwalk_map_and_copy(req_ctx->hmac_virt,
 350                         req->dst, decryptlen, authsize, 1);
 351         }
 352         dma_pool_free(buffer_pool, req_ctx->hmac_virt, crypt->icv_rev_aes);
 353 }
 354
 355 static void one_packet(dma_addr_t phys)
 356 {
 357         struct device *dev = &pdev->dev;
 358         struct crypt_ctl *crypt;
 359         struct ixp_ctx *ctx;
 360         int failed;
 361
 362         failed = phys & 0x1 ? -EBADMSG : 0;
 363         phys &= ~0x3;
 364         crypt = crypt_phys2virt(phys);
 365
 366         switch (crypt->ctl_flags & CTL_FLAG_MASK) {
 367         case CTL_FLAG_PERFORM_AEAD: {
 368                 struct aead_request *req = crypt->data.aead_req;
 369                 struct aead_ctx *req_ctx = aead_request_ctx(req);
 370
 371                 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
 372                 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
 373                 if (req_ctx->hmac_virt) {
 374                         finish_scattered_hmac(crypt);
 375                 }
 376                 req->base.complete(&req->base, failed);
 377                 break;
 378         }
 379         case CTL_FLAG_PERFORM_ABLK: {
 380                 struct ablkcipher_request *req = crypt->data.ablk_req;
 381                 struct ablk_ctx *req_ctx = ablkcipher_request_ctx(req);
 382
 383                 if (req_ctx->dst) {
 384                         free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
 385                 }
 386                 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
 387                 req->base.complete(&req->base, failed);
 388                 break;
 389         }
 390         case CTL_FLAG_GEN_ICV:
 391                 ctx = crypto_tfm_ctx(crypt->data.tfm);
 392                 dma_pool_free(ctx_pool, crypt->regist_ptr,
 393                                 crypt->regist_buf->phys_addr);
 394                 dma_pool_free(buffer_pool, crypt->regist_buf, crypt->src_buf);
 395                 if (atomic_dec_and_test(&ctx->configuring))
 396                         complete(&ctx->completion);
 397                 break;
 398         case CTL_FLAG_GEN_REVAES:
 399                 ctx = crypto_tfm_ctx(crypt->data.tfm);
 400                 *(u32*)ctx->decrypt.npe_ctx &= cpu_to_be32(~CIPH_ENCR);
 401                 if (atomic_dec_and_test(&ctx->configuring))
 402                         complete(&ctx->completion);
 403                 break;
 404         default:
 405                 BUG();
 406         }
 407         crypt->ctl_flags = CTL_FLAG_UNUSED;
 408 }
 409
 410 static void irqhandler(void *_unused)
 411 {
 412         tasklet_schedule(&crypto_done_tasklet);
 413 }
 414
 415 static void crypto_done_action(unsigned long arg)
 416 {
 417         int i;
 418
 419         for(i=0; i<4; i++) {
 420                 dma_addr_t phys = qmgr_get_entry(RECV_QID);
 421                 if (!phys)
 422                         return;
 423                 one_packet(phys);
 424         }
 425         tasklet_schedule(&crypto_done_tasklet);
 426 }
 427
 428 static int init_ixp_crypto(struct device *dev)
 429 {
 430         int ret = -ENODEV;
 431         u32 msg[2] = { 0, 0 };
 432
 433         if (! ( ~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH |
 434                                 IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) {
 435                 printk(KERN_ERR "ixp_crypto: No HW crypto available\n");
 436                 return ret;
 437         }
 438         npe_c = npe_request(NPE_ID);
 439         if (!npe_c)
 440                 return ret;
 441
 442         if (!npe_running(npe_c)) {
 443                 ret = npe_load_firmware(npe_c, npe_name(npe_c), dev);
 444                 if (ret)
 445                         goto npe_release;
 446                 if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
 447                         goto npe_error;
 448         } else {
 449                 if (npe_send_message(npe_c, msg, "STATUS_MSG"))
 450                         goto npe_error;
 451
 452                 if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
 453                         goto npe_error;
 454         }
 455
 456         switch ((msg[1]>>16) & 0xff) {
 457         case 3:
 458                 printk(KERN_WARNING "Firmware of %s lacks AES support\n",
 459                                 npe_name(npe_c));
 460                 support_aes = 0;
 461                 break;
 462         case 4:
 463         case 5:
 464                 support_aes = 1;
 465                 break;
 466         default:
 467                 printk(KERN_ERR "Firmware of %s lacks crypto support\n",
 468                         npe_name(npe_c));
 469                 ret = -ENODEV;
 470                 goto npe_release;
 471         }
 472         /* buffer_pool will also be used to sometimes store the hmac,
 473          * so assure it is large enough
 474          */
 475         BUILD_BUG_ON(SHA1_DIGEST_SIZE > sizeof(struct buffer_desc));
 476         buffer_pool = dma_pool_create("buffer", dev,
 477                         sizeof(struct buffer_desc), 32, 0);
 478         ret = -ENOMEM;
 479         if (!buffer_pool) {
 480                 goto err;
 481         }
 482         ctx_pool = dma_pool_create("context", dev,
 483                         NPE_CTX_LEN, 16, 0);
 484         if (!ctx_pool) {
 485                 goto err;
 486         }
 487         ret = qmgr_request_queue(SEND_QID, NPE_QLEN_TOTAL, 0, 0,
 488                                  "ixp_crypto:out", NULL);
 489         if (ret)
 490                 goto err;
 491         ret = qmgr_request_queue(RECV_QID, NPE_QLEN, 0, 0,
 492                                  "ixp_crypto:in", NULL);
 493         if (ret) {
 494                 qmgr_release_queue(SEND_QID);
 495                 goto err;
 496         }
 497         qmgr_set_irq(RECV_QID, QUEUE_IRQ_SRC_NOT_EMPTY, irqhandler, NULL);
 498         tasklet_init(&crypto_done_tasklet, crypto_done_action, 0);
 499
 500         qmgr_enable_irq(RECV_QID);
 501         return 0;
 502
 503 npe_error:
 504         printk(KERN_ERR "%s not responding\n", npe_name(npe_c));
 505         ret = -EIO;
 506 err:
 507         dma_pool_destroy(ctx_pool);
 508         dma_pool_destroy(buffer_pool);
 509 npe_release:
 510         npe_release(npe_c);
 511         return ret;
 512 }
 513
 514 static void release_ixp_crypto(struct device *dev)
 515 {
 516         qmgr_disable_irq(RECV_QID);
 517         tasklet_kill(&crypto_done_tasklet);
 518
 519         qmgr_release_queue(SEND_QID);
 520         qmgr_release_queue(RECV_QID);
 521
 522         dma_pool_destroy(ctx_pool);
 523         dma_pool_destroy(buffer_pool);
 524
 525         npe_release(npe_c);
 526
 527         if (crypt_virt) {
 528                 dma_free_coherent(dev,
 529                         NPE_QLEN_TOTAL * sizeof( struct crypt_ctl),
 530                         crypt_virt, crypt_phys);
 531         }
 532 }
 533
 534 static void reset_sa_dir(struct ix_sa_dir *dir)
 535 {
 536         memset(dir->npe_ctx, 0, NPE_CTX_LEN);
 537         dir->npe_ctx_idx = 0;
 538         dir->npe_mode = 0;
 539 }
 540
 541 static int init_sa_dir(struct ix_sa_dir *dir)
 542 {
 543         dir->npe_ctx = dma_pool_alloc(ctx_pool, GFP_KERNEL, &dir->npe_ctx_phys);
 544         if (!dir->npe_ctx) {
 545                 return -ENOMEM;
 546         }
 547         reset_sa_dir(dir);
 548         return 0;
 549 }
 550
 551 static void free_sa_dir(struct ix_sa_dir *dir)
 552 {
 553         memset(dir->npe_ctx, 0, NPE_CTX_LEN);
 554         dma_pool_free(ctx_pool, dir->npe_ctx, dir->npe_ctx_phys);
 555 }
 556
 557 static int init_tfm(struct crypto_tfm *tfm)
 558 {
 559         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 560         int ret;
 561
 562         atomic_set(&ctx->configuring, 0);
 563         ret = init_sa_dir(&ctx->encrypt);
 564         if (ret)
 565                 return ret;
 566         ret = init_sa_dir(&ctx->decrypt);
 567         if (ret) {
 568                 free_sa_dir(&ctx->encrypt);
 569         }
 570         return ret;
 571 }
 572
 573 static int init_tfm_ablk(struct crypto_tfm *tfm)
 574 {
 575         tfm->crt_ablkcipher.reqsize = sizeof(struct ablk_ctx);
 576         return init_tfm(tfm);
 577 }
 578
 579 static int init_tfm_aead(struct crypto_aead *tfm)
 580 {
 581         crypto_aead_set_reqsize(tfm, sizeof(struct aead_ctx));
 582         return init_tfm(crypto_aead_tfm(tfm));
 583 }
 584
 585 static void exit_tfm(struct crypto_tfm *tfm)
 586 {
 587         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 588         free_sa_dir(&ctx->encrypt);
 589         free_sa_dir(&ctx->decrypt);
 590 }
 591
 592 static void exit_tfm_aead(struct crypto_aead *tfm)
 593 {
 594         exit_tfm(crypto_aead_tfm(tfm));
 595 }
 596
 597 static int register_chain_var(struct crypto_tfm *tfm, u8 xpad, u32 target,
 598                 int init_len, u32 ctx_addr, const u8 *key, int key_len)
 599 {
 600         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 601         struct crypt_ctl *crypt;
 602         struct buffer_desc *buf;
 603         int i;
 604         u8 *pad;
 605         u32 pad_phys, buf_phys;
 606
 607         BUILD_BUG_ON(NPE_CTX_LEN < HMAC_PAD_BLOCKLEN);
 608         pad = dma_pool_alloc(ctx_pool, GFP_KERNEL, &pad_phys);
 609         if (!pad)
 610                 return -ENOMEM;
 611         buf = dma_pool_alloc(buffer_pool, GFP_KERNEL, &buf_phys);
 612         if (!buf) {
 613                 dma_pool_free(ctx_pool, pad, pad_phys);
 614                 return -ENOMEM;
 615         }
 616         crypt = get_crypt_desc_emerg();
 617         if (!crypt) {
 618                 dma_pool_free(ctx_pool, pad, pad_phys);
 619                 dma_pool_free(buffer_pool, buf, buf_phys);
 620                 return -EAGAIN;
 621         }
 622
 623         memcpy(pad, key, key_len);
 624         memset(pad + key_len, 0, HMAC_PAD_BLOCKLEN - key_len);
 625         for (i = 0; i < HMAC_PAD_BLOCKLEN; i++) {
 626                 pad[i] ^= xpad;
 627         }
 628
 629         crypt->data.tfm = tfm;
 630         crypt->regist_ptr = pad;
 631         crypt->regist_buf = buf;
 632
 633         crypt->auth_offs = 0;
 634         crypt->auth_len = HMAC_PAD_BLOCKLEN;
 635         crypt->crypto_ctx = ctx_addr;
 636         crypt->src_buf = buf_phys;
 637         crypt->icv_rev_aes = target;
 638         crypt->mode = NPE_OP_HASH_GEN_ICV;
 639         crypt->init_len = init_len;
 640         crypt->ctl_flags |= CTL_FLAG_GEN_ICV;
 641
 642         buf->next = 0;
 643         buf->buf_len = HMAC_PAD_BLOCKLEN;
 644         buf->pkt_len = 0;
 645         buf->phys_addr = pad_phys;
 646
 647         atomic_inc(&ctx->configuring);
 648         qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
 649         BUG_ON(qmgr_stat_overflow(SEND_QID));
 650         return 0;
 651 }
 652
 653 static int setup_auth(struct crypto_tfm *tfm, int encrypt, unsigned authsize,
 654                 const u8 *key, int key_len, unsigned digest_len)
 655 {
 656         u32 itarget, otarget, npe_ctx_addr;
 657         unsigned char *cinfo;
 658         int init_len, ret = 0;
 659         u32 cfgword;
 660         struct ix_sa_dir *dir;
 661         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 662         const struct ix_hash_algo *algo;
 663
 664         dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
 665         cinfo = dir->npe_ctx + dir->npe_ctx_idx;
 666         algo = ix_hash(tfm);
 667
 668         /* write cfg word to cryptinfo */
 669         cfgword = algo->cfgword | ( authsize << 6); /* (authsize/4) << 8 */
 670 #ifndef __ARMEB__
 671         cfgword ^= 0xAA000000; /* change the "byte swap" flags */
 672 #endif
 673         *(u32*)cinfo = cpu_to_be32(cfgword);
 674         cinfo += sizeof(cfgword);
 675
 676         /* write ICV to cryptinfo */
 677         memcpy(cinfo, algo->icv, digest_len);
 678         cinfo += digest_len;
 679
 680         itarget = dir->npe_ctx_phys + dir->npe_ctx_idx
 681                                 + sizeof(algo->cfgword);
 682         otarget = itarget + digest_len;
 683         init_len = cinfo - (dir->npe_ctx + dir->npe_ctx_idx);
 684         npe_ctx_addr = dir->npe_ctx_phys + dir->npe_ctx_idx;
 685
 686         dir->npe_ctx_idx += init_len;
 687         dir->npe_mode |= NPE_OP_HASH_ENABLE;
 688
 689         if (!encrypt)
 690                 dir->npe_mode |= NPE_OP_HASH_VERIFY;
 691
 692         ret = register_chain_var(tfm, HMAC_OPAD_VALUE, otarget,
 693                         init_len, npe_ctx_addr, key, key_len);
 694         if (ret)
 695                 return ret;
 696         return register_chain_var(tfm, HMAC_IPAD_VALUE, itarget,
 697                         init_len, npe_ctx_addr, key, key_len);
 698 }
 699
 700 static int gen_rev_aes_key(struct crypto_tfm *tfm)
 701 {
 702         struct crypt_ctl *crypt;
 703         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 704         struct ix_sa_dir *dir = &ctx->decrypt;
 705
 706         crypt = get_crypt_desc_emerg();
 707         if (!crypt) {
 708                 return -EAGAIN;
 709         }
 710         *(u32*)dir->npe_ctx |= cpu_to_be32(CIPH_ENCR);
 711
 712         crypt->data.tfm = tfm;
 713         crypt->crypt_offs = 0;
 714         crypt->crypt_len = AES_BLOCK128;
 715         crypt->src_buf = 0;
 716         crypt->crypto_ctx = dir->npe_ctx_phys;
 717         crypt->icv_rev_aes = dir->npe_ctx_phys + sizeof(u32);
 718         crypt->mode = NPE_OP_ENC_GEN_KEY;
 719         crypt->init_len = dir->npe_ctx_idx;
 720         crypt->ctl_flags |= CTL_FLAG_GEN_REVAES;
 721
 722         atomic_inc(&ctx->configuring);
 723         qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
 724         BUG_ON(qmgr_stat_overflow(SEND_QID));
 725         return 0;
 726 }
 727
 728 static int setup_cipher(struct crypto_tfm *tfm, int encrypt,
 729                 const u8 *key, int key_len)
 730 {
 731         u8 *cinfo;
 732         u32 cipher_cfg;
 733         u32 keylen_cfg = 0;
 734         struct ix_sa_dir *dir;
 735         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 736         u32 *flags = &tfm->crt_flags;
 737
 738         dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
 739         cinfo = dir->npe_ctx;
 740
 741         if (encrypt) {
 742                 cipher_cfg = cipher_cfg_enc(tfm);
 743                 dir->npe_mode |= NPE_OP_CRYPT_ENCRYPT;
 744         } else {
 745                 cipher_cfg = cipher_cfg_dec(tfm);
 746         }
 747         if (cipher_cfg & MOD_AES) {
 748                 switch (key_len) {
 749                 case 16: keylen_cfg = MOD_AES128; break;
 750                 case 24: keylen_cfg = MOD_AES192; break;
 751                 case 32: keylen_cfg = MOD_AES256; break;
 752                 default:
 753                         *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
 754                         return -EINVAL;
 755                 }
 756                 cipher_cfg |= keylen_cfg;
 757         } else {
 758                 u32 tmp[DES_EXPKEY_WORDS];
 759                 if (des_ekey(tmp, key) == 0) {
 760                         *flags |= CRYPTO_TFM_RES_WEAK_KEY;
 761                 }
 762         }
 763         /* write cfg word to cryptinfo */
 764         *(u32*)cinfo = cpu_to_be32(cipher_cfg);
 765         cinfo += sizeof(cipher_cfg);
 766
 767         /* write cipher key to cryptinfo */
 768         memcpy(cinfo, key, key_len);
 769         /* NPE wants keylen set to DES3_EDE_KEY_SIZE even for single DES */
 770         if (key_len < DES3_EDE_KEY_SIZE && !(cipher_cfg & MOD_AES)) {
 771                 memset(cinfo + key_len, 0, DES3_EDE_KEY_SIZE -key_len);
 772                 key_len = DES3_EDE_KEY_SIZE;
 773         }
 774         dir->npe_ctx_idx = sizeof(cipher_cfg) + key_len;
 775         dir->npe_mode |= NPE_OP_CRYPT_ENABLE;
 776         if ((cipher_cfg & MOD_AES) && !encrypt) {
 777                 return gen_rev_aes_key(tfm);
 778         }
 779         return 0;
 780 }
 781
 782 static struct buffer_desc *chainup_buffers(struct device *dev,
 783                 struct scatterlist *sg, unsigned nbytes,
 784                 struct buffer_desc *buf, gfp_t flags,
 785                 enum dma_data_direction dir)
 786 {
 787         for (; nbytes > 0; sg = sg_next(sg)) {
 788                 unsigned len = min(nbytes, sg->length);
 789                 struct buffer_desc *next_buf;
 790                 u32 next_buf_phys;
 791                 void *ptr;
 792
 793                 nbytes -= len;
 794                 ptr = sg_virt(sg);
 795                 next_buf = dma_pool_alloc(buffer_pool, flags, &next_buf_phys);
 796                 if (!next_buf) {
 797                         buf = NULL;
 798                         break;
 799                 }
 800                 sg_dma_address(sg) = dma_map_single(dev, ptr, len, dir);
 801                 buf->next = next_buf;
 802                 buf->phys_next = next_buf_phys;
 803                 buf = next_buf;
 804
 805                 buf->phys_addr = sg_dma_address(sg);
 806                 buf->buf_len = len;
 807                 buf->dir = dir;
 808         }
 809         buf->next = NULL;
 810         buf->phys_next = 0;
 811         return buf;
 812 }
 813
 814 static int ablk_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
 815                         unsigned int key_len)
 816 {
 817         struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
 818         u32 *flags = &tfm->base.crt_flags;
 819         int ret;
 820
 821         init_completion(&ctx->completion);
 822         atomic_inc(&ctx->configuring);
 823
 824         reset_sa_dir(&ctx->encrypt);
 825         reset_sa_dir(&ctx->decrypt);
 826
 827         ctx->encrypt.npe_mode = NPE_OP_HMAC_DISABLE;
 828         ctx->decrypt.npe_mode = NPE_OP_HMAC_DISABLE;
 829
 830         ret = setup_cipher(&tfm->base, 0, key, key_len);
 831         if (ret)
 832                 goto out;
 833         ret = setup_cipher(&tfm->base, 1, key, key_len);
 834         if (ret)
 835                 goto out;
 836
 837         if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
 838                 if (*flags & CRYPTO_TFM_REQ_FORBID_WEAK_KEYS) {
 839                         ret = -EINVAL;
 840                 } else {
 841                         *flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
 842                 }
 843         }
 844 out:
 845         if (!atomic_dec_and_test(&ctx->configuring))
 846                 wait_for_completion(&ctx->completion);
 847         return ret;
 848 }
 849
 850 static int ablk_des3_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
 851                             unsigned int key_len)
 852 {
 853         u32 flags = crypto_ablkcipher_get_flags(tfm);
 854         int err;
 855
 856         err = __des3_verify_key(&flags, key);
 857         if (unlikely(err))
 858                 crypto_ablkcipher_set_flags(tfm, flags);
 859
 860         return ablk_setkey(tfm, key, key_len);
 861 }
 862
 863 static int ablk_rfc3686_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
 864                 unsigned int key_len)
 865 {
 866         struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
 867
 868         /* the nonce is stored in bytes at end of key */
 869         if (key_len < CTR_RFC3686_NONCE_SIZE)
 870                 return -EINVAL;
 871
 872         memcpy(ctx->nonce, key + (key_len - CTR_RFC3686_NONCE_SIZE),
 873                         CTR_RFC3686_NONCE_SIZE);
 874
 875         key_len -= CTR_RFC3686_NONCE_SIZE;
 876         return ablk_setkey(tfm, key, key_len);
 877 }
 878
 879 static int ablk_perform(struct ablkcipher_request *req, int encrypt)
 880 {
 881         struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
 882         struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
 883         unsigned ivsize = crypto_ablkcipher_ivsize(tfm);
 884         struct ix_sa_dir *dir;
 885         struct crypt_ctl *crypt;
 886         unsigned int nbytes = req->nbytes;
 887         enum dma_data_direction src_direction = DMA_BIDIRECTIONAL;
 888         struct ablk_ctx *req_ctx = ablkcipher_request_ctx(req);
 889         struct buffer_desc src_hook;
 890         struct device *dev = &pdev->dev;
 891         gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
 892                                 GFP_KERNEL : GFP_ATOMIC;
 893
 894         if (qmgr_stat_full(SEND_QID))
 895                 return -EAGAIN;
 896         if (atomic_read(&ctx->configuring))
 897                 return -EAGAIN;
 898
 899         dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
 900
 901         crypt = get_crypt_desc();
 902         if (!crypt)
 903                 return -ENOMEM;
 904
 905         crypt->data.ablk_req = req;
 906         crypt->crypto_ctx = dir->npe_ctx_phys;
 907         crypt->mode = dir->npe_mode;
 908         crypt->init_len = dir->npe_ctx_idx;
 909
 910         crypt->crypt_offs = 0;
 911         crypt->crypt_len = nbytes;
 912
 913         BUG_ON(ivsize && !req->info);
 914         memcpy(crypt->iv, req->info, ivsize);
 915         if (req->src != req->dst) {
 916                 struct buffer_desc dst_hook;
 917                 crypt->mode |= NPE_OP_NOT_IN_PLACE;
 918                 /* This was never tested by Intel
 919                  * for more than one dst buffer, I think. */
 920                 req_ctx->dst = NULL;
 921                 if (!chainup_buffers(dev, req->dst, nbytes, &dst_hook,
 922                                         flags, DMA_FROM_DEVICE))
 923                         goto free_buf_dest;
 924                 src_direction = DMA_TO_DEVICE;
 925                 req_ctx->dst = dst_hook.next;
 926                 crypt->dst_buf = dst_hook.phys_next;
 927         } else {
 928                 req_ctx->dst = NULL;
 929         }
 930         req_ctx->src = NULL;
 931         if (!chainup_buffers(dev, req->src, nbytes, &src_hook,
 932                                 flags, src_direction))
 933                 goto free_buf_src;
 934
 935         req_ctx->src = src_hook.next;
 936         crypt->src_buf = src_hook.phys_next;
 937         crypt->ctl_flags |= CTL_FLAG_PERFORM_ABLK;
 938         qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
 939         BUG_ON(qmgr_stat_overflow(SEND_QID));
 940         return -EINPROGRESS;
 941
 942 free_buf_src:
 943         free_buf_chain(dev, req_ctx->src, crypt->src_buf);
 944 free_buf_dest:
 945         if (req->src != req->dst) {
 946                 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
 947         }
 948         crypt->ctl_flags = CTL_FLAG_UNUSED;
 949         return -ENOMEM;
 950 }
 951
 952 static int ablk_encrypt(struct ablkcipher_request *req)
 953 {
 954         return ablk_perform(req, 1);
 955 }
 956
 957 static int ablk_decrypt(struct ablkcipher_request *req)
 958 {
 959         return ablk_perform(req, 0);
 960 }
 961
 962 static int ablk_rfc3686_crypt(struct ablkcipher_request *req)
 963 {
 964         struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
 965         struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
 966         u8 iv[CTR_RFC3686_BLOCK_SIZE];
 967         u8 *info = req->info;
 968         int ret;
 969
 970         /* set up counter block */
 971         memcpy(iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
 972         memcpy(iv + CTR_RFC3686_NONCE_SIZE, info, CTR_RFC3686_IV_SIZE);
 973
 974         /* initialize counter portion of counter block */
 975         *(__be32 *)(iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
 976                 cpu_to_be32(1);
 977
 978         req->info = iv;
 979         ret = ablk_perform(req, 1);
 980         req->info = info;
 981         return ret;
 982 }
 983
 984 static int aead_perform(struct aead_request *req, int encrypt,
 985                 int cryptoffset, int eff_cryptlen, u8 *iv)
 986 {
 987         struct crypto_aead *tfm = crypto_aead_reqtfm(req);
 988         struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
 989         unsigned ivsize = crypto_aead_ivsize(tfm);
 990         unsigned authsize = crypto_aead_authsize(tfm);
 991         struct ix_sa_dir *dir;
 992         struct crypt_ctl *crypt;
 993         unsigned int cryptlen;
 994         struct buffer_desc *buf, src_hook;
 995         struct aead_ctx *req_ctx = aead_request_ctx(req);
 996         struct device *dev = &pdev->dev;
 997         gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
 998                                 GFP_KERNEL : GFP_ATOMIC;
 999         enum dma_data_direction src_direction = DMA_BIDIRECTIONAL;
1000         unsigned int lastlen;
1001
1002         if (qmgr_stat_full(SEND_QID))
1003                 return -EAGAIN;
1004         if (atomic_read(&ctx->configuring))
1005                 return -EAGAIN;
1006
1007         if (encrypt) {
1008                 dir = &ctx->encrypt;
1009                 cryptlen = req->cryptlen;
1010         } else {
1011                 dir = &ctx->decrypt;
1012                 /* req->cryptlen includes the authsize when decrypting */
1013                 cryptlen = req->cryptlen -authsize;
1014                 eff_cryptlen -= authsize;
1015         }
1016         crypt = get_crypt_desc();
1017         if (!crypt)
1018                 return -ENOMEM;
1019
1020         crypt->data.aead_req = req;
1021         crypt->crypto_ctx = dir->npe_ctx_phys;
1022         crypt->mode = dir->npe_mode;
1023         crypt->init_len = dir->npe_ctx_idx;
1024
1025         crypt->crypt_offs = cryptoffset;
1026         crypt->crypt_len = eff_cryptlen;
1027
1028         crypt->auth_offs = 0;
1029         crypt->auth_len = req->assoclen + cryptlen;
1030         BUG_ON(ivsize && !req->iv);
1031         memcpy(crypt->iv, req->iv, ivsize);
1032
1033         buf = chainup_buffers(dev, req->src, crypt->auth_len,
1034                               &src_hook, flags, src_direction);
1035         req_ctx->src = src_hook.next;
1036         crypt->src_buf = src_hook.phys_next;
1037         if (!buf)
1038                 goto free_buf_src;
1039
1040         lastlen = buf->buf_len;
1041         if (lastlen >= authsize)
1042                 crypt->icv_rev_aes = buf->phys_addr +
1043                                      buf->buf_len - authsize;
1044
1045         req_ctx->dst = NULL;
1046
1047         if (req->src != req->dst) {
1048                 struct buffer_desc dst_hook;
1049
1050                 crypt->mode |= NPE_OP_NOT_IN_PLACE;
1051                 src_direction = DMA_TO_DEVICE;
1052
1053                 buf = chainup_buffers(dev, req->dst, crypt->auth_len,
1054                                       &dst_hook, flags, DMA_FROM_DEVICE);
1055                 req_ctx->dst = dst_hook.next;
1056                 crypt->dst_buf = dst_hook.phys_next;
1057
1058                 if (!buf)
1059                         goto free_buf_dst;
1060
1061                 if (encrypt) {
1062                         lastlen = buf->buf_len;
1063                         if (lastlen >= authsize)
1064                                 crypt->icv_rev_aes = buf->phys_addr +
1065                                                      buf->buf_len - authsize;
1066                 }
1067         }
1068
1069         if (unlikely(lastlen < authsize)) {
1070                 /* The 12 hmac bytes are scattered,
1071                  * we need to copy them into a safe buffer */
1072                 req_ctx->hmac_virt = dma_pool_alloc(buffer_pool, flags,
1073                                 &crypt->icv_rev_aes);
1074                 if (unlikely(!req_ctx->hmac_virt))
1075                         goto free_buf_dst;
1076                 if (!encrypt) {
1077                         scatterwalk_map_and_copy(req_ctx->hmac_virt,
1078                                 req->src, cryptlen, authsize, 0);
1079                 }
1080                 req_ctx->encrypt = encrypt;
1081         } else {
1082                 req_ctx->hmac_virt = NULL;
1083         }
1084
1085         crypt->ctl_flags |= CTL_FLAG_PERFORM_AEAD;
1086         qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
1087         BUG_ON(qmgr_stat_overflow(SEND_QID));
1088         return -EINPROGRESS;
1089
1090 free_buf_dst:
1091         free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
1092 free_buf_src:
1093         free_buf_chain(dev, req_ctx->src, crypt->src_buf);
1094         crypt->ctl_flags = CTL_FLAG_UNUSED;
1095         return -ENOMEM;
1096 }
1097
1098 static int aead_setup(struct crypto_aead *tfm, unsigned int authsize)
1099 {
1100         struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1101         u32 *flags = &tfm->base.crt_flags;
1102         unsigned digest_len = crypto_aead_maxauthsize(tfm);
1103         int ret;
1104
1105         if (!ctx->enckey_len && !ctx->authkey_len)
1106                 return 0;
1107         init_completion(&ctx->completion);
1108         atomic_inc(&ctx->configuring);
1109
1110         reset_sa_dir(&ctx->encrypt);
1111         reset_sa_dir(&ctx->decrypt);
1112
1113         ret = setup_cipher(&tfm->base, 0, ctx->enckey, ctx->enckey_len);
1114         if (ret)
1115                 goto out;
1116         ret = setup_cipher(&tfm->base, 1, ctx->enckey, ctx->enckey_len);
1117         if (ret)
1118                 goto out;
1119         ret = setup_auth(&tfm->base, 0, authsize, ctx->authkey,
1120                         ctx->authkey_len, digest_len);
1121         if (ret)
1122                 goto out;
1123         ret = setup_auth(&tfm->base, 1, authsize,  ctx->authkey,
1124                         ctx->authkey_len, digest_len);
1125         if (ret)
1126                 goto out;
1127
1128         if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
1129                 if (*flags & CRYPTO_TFM_REQ_FORBID_WEAK_KEYS) {
1130                         ret = -EINVAL;
1131                         goto out;
1132                 } else {
1133                         *flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
1134                 }
1135         }
1136 out:
1137         if (!atomic_dec_and_test(&ctx->configuring))
1138                 wait_for_completion(&ctx->completion);
1139         return ret;
1140 }
1141
1142 static int aead_setauthsize(struct crypto_aead *tfm, unsigned int authsize)
1143 {
1144         int max = crypto_aead_maxauthsize(tfm) >> 2;
1145
1146         if ((authsize>>2) < 1 || (authsize>>2) > max || (authsize & 3))
1147                 return -EINVAL;
1148         return aead_setup(tfm, authsize);
1149 }
1150
1151 static int aead_setkey(struct crypto_aead *tfm, const u8 *key,
1152                         unsigned int keylen)
1153 {
1154         struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1155         struct crypto_authenc_keys keys;
1156
1157         if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
1158                 goto badkey;
1159
1160         if (keys.authkeylen > sizeof(ctx->authkey))
1161                 goto badkey;
1162
1163         if (keys.enckeylen > sizeof(ctx->enckey))
1164                 goto badkey;
1165
1166         memcpy(ctx->authkey, keys.authkey, keys.authkeylen);
1167         memcpy(ctx->enckey, keys.enckey, keys.enckeylen);
1168         ctx->authkey_len = keys.authkeylen;
1169         ctx->enckey_len = keys.enckeylen;
1170
1171         memzero_explicit(&keys, sizeof(keys));
1172         return aead_setup(tfm, crypto_aead_authsize(tfm));
1173 badkey:
1174         crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1175         memzero_explicit(&keys, sizeof(keys));
1176         return -EINVAL;
1177 }
1178
1179 static int des3_aead_setkey(struct crypto_aead *tfm, const u8 *key,
1180                             unsigned int keylen)
1181 {
1182         struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1183         u32 flags = CRYPTO_TFM_RES_BAD_KEY_LEN;
1184         struct crypto_authenc_keys keys;
1185         int err;
1186
1187         err = crypto_authenc_extractkeys(&keys, key, keylen);
1188         if (unlikely(err))
1189                 goto badkey;
1190
1191         err = -EINVAL;
1192         if (keys.authkeylen > sizeof(ctx->authkey))
1193                 goto badkey;
1194
1195         if (keys.enckeylen != DES3_EDE_KEY_SIZE)
1196                 goto badkey;
1197
1198         flags = crypto_aead_get_flags(tfm);
1199         err = __des3_verify_key(&flags, keys.enckey);
1200         if (unlikely(err))
1201                 goto badkey;
1202
1203         memcpy(ctx->authkey, keys.authkey, keys.authkeylen);
1204         memcpy(ctx->enckey, keys.enckey, keys.enckeylen);
1205         ctx->authkey_len = keys.authkeylen;
1206         ctx->enckey_len = keys.enckeylen;
1207
1208         memzero_explicit(&keys, sizeof(keys));
1209         return aead_setup(tfm, crypto_aead_authsize(tfm));
1210 badkey:
1211         crypto_aead_set_flags(tfm, flags);
1212         memzero_explicit(&keys, sizeof(keys));
1213         return err;
1214 }
1215
1216 static int aead_encrypt(struct aead_request *req)
1217 {
1218         return aead_perform(req, 1, req->assoclen, req->cryptlen, req->iv);
1219 }
1220
1221 static int aead_decrypt(struct aead_request *req)
1222 {
1223         return aead_perform(req, 0, req->assoclen, req->cryptlen, req->iv);
1224 }
1225
1226 static struct ixp_alg ixp4xx_algos[] = {
1227 {
1228         .crypto = {
1229                 .cra_name       = "cbc(des)",
1230                 .cra_blocksize  = DES_BLOCK_SIZE,
1231                 .cra_u          = { .ablkcipher = {
1232                         .min_keysize    = DES_KEY_SIZE,
1233                         .max_keysize    = DES_KEY_SIZE,
1234                         .ivsize         = DES_BLOCK_SIZE,
1235                         }
1236                 }
1237         },
1238         .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1239         .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1240
1241 }, {
1242         .crypto = {
1243                 .cra_name       = "ecb(des)",
1244                 .cra_blocksize  = DES_BLOCK_SIZE,
1245                 .cra_u          = { .ablkcipher = {
1246                         .min_keysize    = DES_KEY_SIZE,
1247                         .max_keysize    = DES_KEY_SIZE,
1248                         }
1249                 }
1250         },
1251         .cfg_enc = CIPH_ENCR | MOD_DES | MOD_ECB | KEYLEN_192,
1252         .cfg_dec = CIPH_DECR | MOD_DES | MOD_ECB | KEYLEN_192,
1253 }, {
1254         .crypto = {
1255                 .cra_name       = "cbc(des3_ede)",
1256                 .cra_blocksize  = DES3_EDE_BLOCK_SIZE,
1257                 .cra_u          = { .ablkcipher = {
1258                         .min_keysize    = DES3_EDE_KEY_SIZE,
1259                         .max_keysize    = DES3_EDE_KEY_SIZE,
1260                         .ivsize         = DES3_EDE_BLOCK_SIZE,
1261                         .setkey         = ablk_des3_setkey,
1262                         }
1263                 }
1264         },
1265         .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1266         .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1267 }, {
1268         .crypto = {
1269                 .cra_name       = "ecb(des3_ede)",
1270                 .cra_blocksize  = DES3_EDE_BLOCK_SIZE,
1271                 .cra_u          = { .ablkcipher = {
1272                         .min_keysize    = DES3_EDE_KEY_SIZE,
1273                         .max_keysize    = DES3_EDE_KEY_SIZE,
1274                         .setkey         = ablk_des3_setkey,
1275                         }
1276                 }
1277         },
1278         .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_ECB | KEYLEN_192,
1279         .cfg_dec = CIPH_DECR | MOD_3DES | MOD_ECB | KEYLEN_192,
1280 }, {
1281         .crypto = {
1282                 .cra_name       = "cbc(aes)",
1283                 .cra_blocksize  = AES_BLOCK_SIZE,
1284                 .cra_u          = { .ablkcipher = {
1285                         .min_keysize    = AES_MIN_KEY_SIZE,
1286                         .max_keysize    = AES_MAX_KEY_SIZE,
1287                         .ivsize         = AES_BLOCK_SIZE,
1288                         }
1289                 }
1290         },
1291         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1292         .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1293 }, {
1294         .crypto = {
1295                 .cra_name       = "ecb(aes)",
1296                 .cra_blocksize  = AES_BLOCK_SIZE,
1297                 .cra_u          = { .ablkcipher = {
1298                         .min_keysize    = AES_MIN_KEY_SIZE,
1299                         .max_keysize    = AES_MAX_KEY_SIZE,
1300                         }
1301                 }
1302         },
1303         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_ECB,
1304         .cfg_dec = CIPH_DECR | MOD_AES | MOD_ECB,
1305 }, {
1306         .crypto = {
1307                 .cra_name       = "ctr(aes)",
1308                 .cra_blocksize  = AES_BLOCK_SIZE,
1309                 .cra_u          = { .ablkcipher = {
1310                         .min_keysize    = AES_MIN_KEY_SIZE,
1311                         .max_keysize    = AES_MAX_KEY_SIZE,
1312                         .ivsize         = AES_BLOCK_SIZE,
1313                         }
1314                 }
1315         },
1316         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1317         .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1318 }, {
1319         .crypto = {
1320                 .cra_name       = "rfc3686(ctr(aes))",
1321                 .cra_blocksize  = AES_BLOCK_SIZE,
1322                 .cra_u          = { .ablkcipher = {
1323                         .min_keysize    = AES_MIN_KEY_SIZE,
1324                         .max_keysize    = AES_MAX_KEY_SIZE,
1325                         .ivsize         = AES_BLOCK_SIZE,
1326                         .setkey         = ablk_rfc3686_setkey,
1327                         .encrypt        = ablk_rfc3686_crypt,
1328                         .decrypt        = ablk_rfc3686_crypt }
1329                 }
1330         },
1331         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1332         .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1333 } };
1334
1335 static struct ixp_aead_alg ixp4xx_aeads[] = {
1336 {
1337         .crypto = {
1338                 .base = {
1339                         .cra_name       = "authenc(hmac(md5),cbc(des))",
1340                         .cra_blocksize  = DES_BLOCK_SIZE,
1341                 },
1342                 .ivsize         = DES_BLOCK_SIZE,
1343                 .maxauthsize    = MD5_DIGEST_SIZE,
1344         },
1345         .hash = &hash_alg_md5,
1346         .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1347         .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1348 }, {
1349         .crypto = {
1350                 .base = {
1351                         .cra_name       = "authenc(hmac(md5),cbc(des3_ede))",
1352                         .cra_blocksize  = DES3_EDE_BLOCK_SIZE,
1353                 },
1354                 .ivsize         = DES3_EDE_BLOCK_SIZE,
1355                 .maxauthsize    = MD5_DIGEST_SIZE,
1356                 .setkey         = des3_aead_setkey,
1357         },
1358         .hash = &hash_alg_md5,
1359         .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1360         .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1361 }, {
1362         .crypto = {
1363                 .base = {
1364                         .cra_name       = "authenc(hmac(sha1),cbc(des))",
1365                         .cra_blocksize  = DES_BLOCK_SIZE,
1366                 },
1367                         .ivsize         = DES_BLOCK_SIZE,
1368                         .maxauthsize    = SHA1_DIGEST_SIZE,
1369         },
1370         .hash = &hash_alg_sha1,
1371         .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1372         .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1373 }, {
1374         .crypto = {
1375                 .base = {
1376                         .cra_name       = "authenc(hmac(sha1),cbc(des3_ede))",
1377                         .cra_blocksize  = DES3_EDE_BLOCK_SIZE,
1378                 },
1379                 .ivsize         = DES3_EDE_BLOCK_SIZE,
1380                 .maxauthsize    = SHA1_DIGEST_SIZE,
1381                 .setkey         = des3_aead_setkey,
1382         },
1383         .hash = &hash_alg_sha1,
1384         .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1385         .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1386 }, {
1387         .crypto = {
1388                 .base = {
1389                         .cra_name       = "authenc(hmac(md5),cbc(aes))",
1390                         .cra_blocksize  = AES_BLOCK_SIZE,
1391                 },
1392                 .ivsize         = AES_BLOCK_SIZE,
1393                 .maxauthsize    = MD5_DIGEST_SIZE,
1394         },
1395         .hash = &hash_alg_md5,
1396         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1397         .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1398 }, {
1399         .crypto = {
1400                 .base = {
1401                         .cra_name       = "authenc(hmac(sha1),cbc(aes))",
1402                         .cra_blocksize  = AES_BLOCK_SIZE,
1403                 },
1404                 .ivsize         = AES_BLOCK_SIZE,
1405                 .maxauthsize    = SHA1_DIGEST_SIZE,
1406         },
1407         .hash = &hash_alg_sha1,
1408         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1409         .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1410 } };
1411
1412 #define IXP_POSTFIX "-ixp4xx"
1413
1414 static const struct platform_device_info ixp_dev_info __initdata = {
1415         .name           = DRIVER_NAME,
1416         .id             = 0,
1417         .dma_mask       = DMA_BIT_MASK(32),
1418 };
1419
1420 static int __init ixp_module_init(void)
1421 {
1422         int num = ARRAY_SIZE(ixp4xx_algos);
1423         int i, err;
1424
1425         pdev = platform_device_register_full(&ixp_dev_info);
1426         if (IS_ERR(pdev))
1427                 return PTR_ERR(pdev);
1428
1429         spin_lock_init(&desc_lock);
1430         spin_lock_init(&emerg_lock);
1431
1432         err = init_ixp_crypto(&pdev->dev);
1433         if (err) {
1434                 platform_device_unregister(pdev);
1435                 return err;
1436         }
1437         for (i=0; i< num; i++) {
1438                 struct crypto_alg *cra = &ixp4xx_algos[i].crypto;
1439
1440                 if (snprintf(cra->cra_driver_name, CRYPTO_MAX_ALG_NAME,
1441                         "%s"IXP_POSTFIX, cra->cra_name) >=
1442                         CRYPTO_MAX_ALG_NAME)
1443                 {
1444                         continue;
1445                 }
1446                 if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES)) {
1447                         continue;
1448                 }
1449
1450                 /* block ciphers */
1451                 cra->cra_type = &crypto_ablkcipher_type;
1452                 cra->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1453                                  CRYPTO_ALG_KERN_DRIVER_ONLY |
1454                                  CRYPTO_ALG_ASYNC;
1455                 if (!cra->cra_ablkcipher.setkey)
1456                         cra->cra_ablkcipher.setkey = ablk_setkey;
1457                 if (!cra->cra_ablkcipher.encrypt)
1458                         cra->cra_ablkcipher.encrypt = ablk_encrypt;
1459                 if (!cra->cra_ablkcipher.decrypt)
1460                         cra->cra_ablkcipher.decrypt = ablk_decrypt;
1461                 cra->cra_init = init_tfm_ablk;
1462
1463                 cra->cra_ctxsize = sizeof(struct ixp_ctx);
1464                 cra->cra_module = THIS_MODULE;
1465                 cra->cra_alignmask = 3;
1466                 cra->cra_priority = 300;
1467                 cra->cra_exit = exit_tfm;
1468                 if (crypto_register_alg(cra))
1469                         printk(KERN_ERR "Failed to register '%s'\n",
1470                                 cra->cra_name);
1471                 else
1472                         ixp4xx_algos[i].registered = 1;
1473         }
1474
1475         for (i = 0; i < ARRAY_SIZE(ixp4xx_aeads); i++) {
1476                 struct aead_alg *cra = &ixp4xx_aeads[i].crypto;
1477
1478                 if (snprintf(cra->base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
1479                              "%s"IXP_POSTFIX, cra->base.cra_name) >=
1480                     CRYPTO_MAX_ALG_NAME)
1481                         continue;
1482                 if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES))
1483                         continue;
1484
1485                 /* authenc */
1486                 cra->base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1487                                       CRYPTO_ALG_ASYNC;
1488                 cra->setkey = cra->setkey ?: aead_setkey;
1489                 cra->setauthsize = aead_setauthsize;
1490                 cra->encrypt = aead_encrypt;
1491                 cra->decrypt = aead_decrypt;
1492                 cra->init = init_tfm_aead;
1493                 cra->exit = exit_tfm_aead;
1494
1495                 cra->base.cra_ctxsize = sizeof(struct ixp_ctx);
1496                 cra->base.cra_module = THIS_MODULE;
1497                 cra->base.cra_alignmask = 3;
1498                 cra->base.cra_priority = 300;
1499
1500                 if (crypto_register_aead(cra))
1501                         printk(KERN_ERR "Failed to register '%s'\n",
1502                                 cra->base.cra_driver_name);
1503                 else
1504                         ixp4xx_aeads[i].registered = 1;
1505         }
1506         return 0;
1507 }
1508
1509 static void __exit ixp_module_exit(void)
1510 {
1511         int num = ARRAY_SIZE(ixp4xx_algos);
1512         int i;
1513
1514         for (i = 0; i < ARRAY_SIZE(ixp4xx_aeads); i++) {
1515                 if (ixp4xx_aeads[i].registered)
1516                         crypto_unregister_aead(&ixp4xx_aeads[i].crypto);
1517         }
1518
1519         for (i=0; i< num; i++) {
1520                 if (ixp4xx_algos[i].registered)
1521                         crypto_unregister_alg(&ixp4xx_algos[i].crypto);
1522         }
1523         release_ixp_crypto(&pdev->dev);
1524         platform_device_unregister(pdev);
1525 }
1526
1527 module_init(ixp_module_init);
1528 module_exit(ixp_module_exit);
1529
1530 MODULE_LICENSE("GPL");
1531 MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>");
1532 MODULE_DESCRIPTION("IXP4xx hardware crypto");
1533