1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel IXP4xx NPE-C crypto driver
5 * Copyright (C) 2008 Christian Hohnstaedt <chohnstaedt@innominate.com>
8 #include <linux/platform_device.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/dmapool.h>
11 #include <linux/crypto.h>
12 #include <linux/kernel.h>
13 #include <linux/rtnetlink.h>
14 #include <linux/interrupt.h>
15 #include <linux/spinlock.h>
16 #include <linux/gfp.h>
17 #include <linux/module.h>
19 #include <crypto/ctr.h>
20 #include <crypto/des.h>
21 #include <crypto/aes.h>
22 #include <crypto/hmac.h>
23 #include <crypto/sha.h>
24 #include <crypto/algapi.h>
25 #include <crypto/internal/aead.h>
26 #include <crypto/authenc.h>
27 #include <crypto/scatterwalk.h>
29 #include <linux/soc/ixp4xx/npe.h>
30 #include <linux/soc/ixp4xx/qmgr.h>
34 /* hash: cfgword + 2 * digestlen; crypt: keylen + cfgword */
35 #define NPE_CTX_LEN 80
36 #define AES_BLOCK128 16
38 #define NPE_OP_HASH_VERIFY 0x01
39 #define NPE_OP_CCM_ENABLE 0x04
40 #define NPE_OP_CRYPT_ENABLE 0x08
41 #define NPE_OP_HASH_ENABLE 0x10
42 #define NPE_OP_NOT_IN_PLACE 0x20
43 #define NPE_OP_HMAC_DISABLE 0x40
44 #define NPE_OP_CRYPT_ENCRYPT 0x80
46 #define NPE_OP_CCM_GEN_MIC 0xcc
47 #define NPE_OP_HASH_GEN_ICV 0x50
48 #define NPE_OP_ENC_GEN_KEY 0xc9
50 #define MOD_ECB 0x0000
51 #define MOD_CTR 0x1000
52 #define MOD_CBC_ENC 0x2000
53 #define MOD_CBC_DEC 0x3000
54 #define MOD_CCM_ENC 0x4000
55 #define MOD_CCM_DEC 0x5000
61 #define CIPH_DECR 0x0000
62 #define CIPH_ENCR 0x0400
64 #define MOD_DES 0x0000
65 #define MOD_TDEA2 0x0100
66 #define MOD_3DES 0x0200
67 #define MOD_AES 0x0800
68 #define MOD_AES128 (0x0800 | KEYLEN_128)
69 #define MOD_AES192 (0x0900 | KEYLEN_192)
70 #define MOD_AES256 (0x0a00 | KEYLEN_256)
73 #define NPE_ID 2 /* NPE C */
75 /* Space for registering when the first
76 * NPE_QLEN crypt_ctl are busy */
77 #define NPE_QLEN_TOTAL 64
82 #define CTL_FLAG_UNUSED 0x0000
83 #define CTL_FLAG_USED 0x1000
84 #define CTL_FLAG_PERFORM_ABLK 0x0001
85 #define CTL_FLAG_GEN_ICV 0x0002
86 #define CTL_FLAG_GEN_REVAES 0x0004
87 #define CTL_FLAG_PERFORM_AEAD 0x0008
88 #define CTL_FLAG_MASK 0x000f
90 #define HMAC_PAD_BLOCKLEN SHA1_BLOCK_SIZE
92 #define MD5_DIGEST_SIZE 16
105 struct buffer_desc *next;
106 enum dma_data_direction dir;
111 u8 mode; /* NPE_OP_* operation mode */
117 u8 mode; /* NPE_OP_* operation mode */
119 u8 iv[MAX_IVLEN]; /* IV for CBC mode or CTR IV for CTR mode */
120 u32 icv_rev_aes; /* icv or rev aes */
124 u16 auth_offs; /* Authentication start offset */
125 u16 auth_len; /* Authentication data length */
126 u16 crypt_offs; /* Cryption start offset */
127 u16 crypt_len; /* Cryption data length */
129 u16 auth_len; /* Authentication data length */
130 u16 auth_offs; /* Authentication start offset */
131 u16 crypt_len; /* Cryption data length */
132 u16 crypt_offs; /* Cryption start offset */
134 u32 aadAddr; /* Additional Auth Data Addr for CCM mode */
135 u32 crypto_ctx; /* NPE Crypto Param structure address */
137 /* Used by Host: 4*4 bytes*/
140 struct ablkcipher_request *ablk_req;
141 struct aead_request *aead_req;
142 struct crypto_tfm *tfm;
144 struct buffer_desc *regist_buf;
149 struct buffer_desc *src;
150 struct buffer_desc *dst;
154 struct buffer_desc *src;
155 struct buffer_desc *dst;
156 struct scatterlist ivlist;
157 /* used when the hmac is not on one sg entry */
162 struct ix_hash_algo {
168 unsigned char *npe_ctx;
169 dma_addr_t npe_ctx_phys;
175 struct ix_sa_dir encrypt;
176 struct ix_sa_dir decrypt;
178 u8 authkey[MAX_KEYLEN];
180 u8 enckey[MAX_KEYLEN];
182 u8 nonce[CTR_RFC3686_NONCE_SIZE];
184 atomic_t configuring;
185 struct completion completion;
189 struct crypto_alg crypto;
190 const struct ix_hash_algo *hash;
197 struct ixp_aead_alg {
198 struct aead_alg crypto;
199 const struct ix_hash_algo *hash;
206 static const struct ix_hash_algo hash_alg_md5 = {
207 .cfgword = 0xAA010004,
208 .icv = "\x01\x23\x45\x67\x89\xAB\xCD\xEF"
209 "\xFE\xDC\xBA\x98\x76\x54\x32\x10",
211 static const struct ix_hash_algo hash_alg_sha1 = {
212 .cfgword = 0x00000005,
213 .icv = "\x67\x45\x23\x01\xEF\xCD\xAB\x89\x98\xBA"
214 "\xDC\xFE\x10\x32\x54\x76\xC3\xD2\xE1\xF0",
217 static struct npe *npe_c;
218 static struct dma_pool *buffer_pool = NULL;
219 static struct dma_pool *ctx_pool = NULL;
221 static struct crypt_ctl *crypt_virt = NULL;
222 static dma_addr_t crypt_phys;
224 static int support_aes = 1;
226 #define DRIVER_NAME "ixp4xx_crypto"
228 static struct platform_device *pdev;
230 static inline dma_addr_t crypt_virt2phys(struct crypt_ctl *virt)
232 return crypt_phys + (virt - crypt_virt) * sizeof(struct crypt_ctl);
235 static inline struct crypt_ctl *crypt_phys2virt(dma_addr_t phys)
237 return crypt_virt + (phys - crypt_phys) / sizeof(struct crypt_ctl);
240 static inline u32 cipher_cfg_enc(struct crypto_tfm *tfm)
242 return container_of(tfm->__crt_alg, struct ixp_alg,crypto)->cfg_enc;
245 static inline u32 cipher_cfg_dec(struct crypto_tfm *tfm)
247 return container_of(tfm->__crt_alg, struct ixp_alg,crypto)->cfg_dec;
250 static inline const struct ix_hash_algo *ix_hash(struct crypto_tfm *tfm)
252 return container_of(tfm->__crt_alg, struct ixp_alg, crypto)->hash;
255 static int setup_crypt_desc(void)
257 struct device *dev = &pdev->dev;
258 BUILD_BUG_ON(sizeof(struct crypt_ctl) != 64);
259 crypt_virt = dma_alloc_coherent(dev,
260 NPE_QLEN * sizeof(struct crypt_ctl),
261 &crypt_phys, GFP_ATOMIC);
267 static spinlock_t desc_lock;
268 static struct crypt_ctl *get_crypt_desc(void)
274 spin_lock_irqsave(&desc_lock, flags);
276 if (unlikely(!crypt_virt))
278 if (unlikely(!crypt_virt)) {
279 spin_unlock_irqrestore(&desc_lock, flags);
283 if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
284 if (++idx >= NPE_QLEN)
286 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
287 spin_unlock_irqrestore(&desc_lock, flags);
288 return crypt_virt +i;
290 spin_unlock_irqrestore(&desc_lock, flags);
295 static spinlock_t emerg_lock;
296 static struct crypt_ctl *get_crypt_desc_emerg(void)
299 static int idx = NPE_QLEN;
300 struct crypt_ctl *desc;
303 desc = get_crypt_desc();
306 if (unlikely(!crypt_virt))
309 spin_lock_irqsave(&emerg_lock, flags);
311 if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
312 if (++idx >= NPE_QLEN_TOTAL)
314 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
315 spin_unlock_irqrestore(&emerg_lock, flags);
316 return crypt_virt +i;
318 spin_unlock_irqrestore(&emerg_lock, flags);
323 static void free_buf_chain(struct device *dev, struct buffer_desc *buf,u32 phys)
326 struct buffer_desc *buf1;
330 phys1 = buf->phys_next;
331 dma_unmap_single(dev, buf->phys_next, buf->buf_len, buf->dir);
332 dma_pool_free(buffer_pool, buf, phys);
338 static struct tasklet_struct crypto_done_tasklet;
340 static void finish_scattered_hmac(struct crypt_ctl *crypt)
342 struct aead_request *req = crypt->data.aead_req;
343 struct aead_ctx *req_ctx = aead_request_ctx(req);
344 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
345 int authsize = crypto_aead_authsize(tfm);
346 int decryptlen = req->assoclen + req->cryptlen - authsize;
348 if (req_ctx->encrypt) {
349 scatterwalk_map_and_copy(req_ctx->hmac_virt,
350 req->dst, decryptlen, authsize, 1);
352 dma_pool_free(buffer_pool, req_ctx->hmac_virt, crypt->icv_rev_aes);
355 static void one_packet(dma_addr_t phys)
357 struct device *dev = &pdev->dev;
358 struct crypt_ctl *crypt;
362 failed = phys & 0x1 ? -EBADMSG : 0;
364 crypt = crypt_phys2virt(phys);
366 switch (crypt->ctl_flags & CTL_FLAG_MASK) {
367 case CTL_FLAG_PERFORM_AEAD: {
368 struct aead_request *req = crypt->data.aead_req;
369 struct aead_ctx *req_ctx = aead_request_ctx(req);
371 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
372 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
373 if (req_ctx->hmac_virt) {
374 finish_scattered_hmac(crypt);
376 req->base.complete(&req->base, failed);
379 case CTL_FLAG_PERFORM_ABLK: {
380 struct ablkcipher_request *req = crypt->data.ablk_req;
381 struct ablk_ctx *req_ctx = ablkcipher_request_ctx(req);
384 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
386 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
387 req->base.complete(&req->base, failed);
390 case CTL_FLAG_GEN_ICV:
391 ctx = crypto_tfm_ctx(crypt->data.tfm);
392 dma_pool_free(ctx_pool, crypt->regist_ptr,
393 crypt->regist_buf->phys_addr);
394 dma_pool_free(buffer_pool, crypt->regist_buf, crypt->src_buf);
395 if (atomic_dec_and_test(&ctx->configuring))
396 complete(&ctx->completion);
398 case CTL_FLAG_GEN_REVAES:
399 ctx = crypto_tfm_ctx(crypt->data.tfm);
400 *(u32*)ctx->decrypt.npe_ctx &= cpu_to_be32(~CIPH_ENCR);
401 if (atomic_dec_and_test(&ctx->configuring))
402 complete(&ctx->completion);
407 crypt->ctl_flags = CTL_FLAG_UNUSED;
410 static void irqhandler(void *_unused)
412 tasklet_schedule(&crypto_done_tasklet);
415 static void crypto_done_action(unsigned long arg)
420 dma_addr_t phys = qmgr_get_entry(RECV_QID);
425 tasklet_schedule(&crypto_done_tasklet);
428 static int init_ixp_crypto(struct device *dev)
431 u32 msg[2] = { 0, 0 };
433 if (! ( ~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH |
434 IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) {
435 printk(KERN_ERR "ixp_crypto: No HW crypto available\n");
438 npe_c = npe_request(NPE_ID);
442 if (!npe_running(npe_c)) {
443 ret = npe_load_firmware(npe_c, npe_name(npe_c), dev);
446 if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
449 if (npe_send_message(npe_c, msg, "STATUS_MSG"))
452 if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
456 switch ((msg[1]>>16) & 0xff) {
458 printk(KERN_WARNING "Firmware of %s lacks AES support\n",
467 printk(KERN_ERR "Firmware of %s lacks crypto support\n",
472 /* buffer_pool will also be used to sometimes store the hmac,
473 * so assure it is large enough
475 BUILD_BUG_ON(SHA1_DIGEST_SIZE > sizeof(struct buffer_desc));
476 buffer_pool = dma_pool_create("buffer", dev,
477 sizeof(struct buffer_desc), 32, 0);
482 ctx_pool = dma_pool_create("context", dev,
487 ret = qmgr_request_queue(SEND_QID, NPE_QLEN_TOTAL, 0, 0,
488 "ixp_crypto:out", NULL);
491 ret = qmgr_request_queue(RECV_QID, NPE_QLEN, 0, 0,
492 "ixp_crypto:in", NULL);
494 qmgr_release_queue(SEND_QID);
497 qmgr_set_irq(RECV_QID, QUEUE_IRQ_SRC_NOT_EMPTY, irqhandler, NULL);
498 tasklet_init(&crypto_done_tasklet, crypto_done_action, 0);
500 qmgr_enable_irq(RECV_QID);
504 printk(KERN_ERR "%s not responding\n", npe_name(npe_c));
507 dma_pool_destroy(ctx_pool);
508 dma_pool_destroy(buffer_pool);
514 static void release_ixp_crypto(struct device *dev)
516 qmgr_disable_irq(RECV_QID);
517 tasklet_kill(&crypto_done_tasklet);
519 qmgr_release_queue(SEND_QID);
520 qmgr_release_queue(RECV_QID);
522 dma_pool_destroy(ctx_pool);
523 dma_pool_destroy(buffer_pool);
528 dma_free_coherent(dev,
529 NPE_QLEN_TOTAL * sizeof( struct crypt_ctl),
530 crypt_virt, crypt_phys);
534 static void reset_sa_dir(struct ix_sa_dir *dir)
536 memset(dir->npe_ctx, 0, NPE_CTX_LEN);
537 dir->npe_ctx_idx = 0;
541 static int init_sa_dir(struct ix_sa_dir *dir)
543 dir->npe_ctx = dma_pool_alloc(ctx_pool, GFP_KERNEL, &dir->npe_ctx_phys);
551 static void free_sa_dir(struct ix_sa_dir *dir)
553 memset(dir->npe_ctx, 0, NPE_CTX_LEN);
554 dma_pool_free(ctx_pool, dir->npe_ctx, dir->npe_ctx_phys);
557 static int init_tfm(struct crypto_tfm *tfm)
559 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
562 atomic_set(&ctx->configuring, 0);
563 ret = init_sa_dir(&ctx->encrypt);
566 ret = init_sa_dir(&ctx->decrypt);
568 free_sa_dir(&ctx->encrypt);
573 static int init_tfm_ablk(struct crypto_tfm *tfm)
575 tfm->crt_ablkcipher.reqsize = sizeof(struct ablk_ctx);
576 return init_tfm(tfm);
579 static int init_tfm_aead(struct crypto_aead *tfm)
581 crypto_aead_set_reqsize(tfm, sizeof(struct aead_ctx));
582 return init_tfm(crypto_aead_tfm(tfm));
585 static void exit_tfm(struct crypto_tfm *tfm)
587 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
588 free_sa_dir(&ctx->encrypt);
589 free_sa_dir(&ctx->decrypt);
592 static void exit_tfm_aead(struct crypto_aead *tfm)
594 exit_tfm(crypto_aead_tfm(tfm));
597 static int register_chain_var(struct crypto_tfm *tfm, u8 xpad, u32 target,
598 int init_len, u32 ctx_addr, const u8 *key, int key_len)
600 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
601 struct crypt_ctl *crypt;
602 struct buffer_desc *buf;
605 u32 pad_phys, buf_phys;
607 BUILD_BUG_ON(NPE_CTX_LEN < HMAC_PAD_BLOCKLEN);
608 pad = dma_pool_alloc(ctx_pool, GFP_KERNEL, &pad_phys);
611 buf = dma_pool_alloc(buffer_pool, GFP_KERNEL, &buf_phys);
613 dma_pool_free(ctx_pool, pad, pad_phys);
616 crypt = get_crypt_desc_emerg();
618 dma_pool_free(ctx_pool, pad, pad_phys);
619 dma_pool_free(buffer_pool, buf, buf_phys);
623 memcpy(pad, key, key_len);
624 memset(pad + key_len, 0, HMAC_PAD_BLOCKLEN - key_len);
625 for (i = 0; i < HMAC_PAD_BLOCKLEN; i++) {
629 crypt->data.tfm = tfm;
630 crypt->regist_ptr = pad;
631 crypt->regist_buf = buf;
633 crypt->auth_offs = 0;
634 crypt->auth_len = HMAC_PAD_BLOCKLEN;
635 crypt->crypto_ctx = ctx_addr;
636 crypt->src_buf = buf_phys;
637 crypt->icv_rev_aes = target;
638 crypt->mode = NPE_OP_HASH_GEN_ICV;
639 crypt->init_len = init_len;
640 crypt->ctl_flags |= CTL_FLAG_GEN_ICV;
643 buf->buf_len = HMAC_PAD_BLOCKLEN;
645 buf->phys_addr = pad_phys;
647 atomic_inc(&ctx->configuring);
648 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
649 BUG_ON(qmgr_stat_overflow(SEND_QID));
653 static int setup_auth(struct crypto_tfm *tfm, int encrypt, unsigned authsize,
654 const u8 *key, int key_len, unsigned digest_len)
656 u32 itarget, otarget, npe_ctx_addr;
657 unsigned char *cinfo;
658 int init_len, ret = 0;
660 struct ix_sa_dir *dir;
661 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
662 const struct ix_hash_algo *algo;
664 dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
665 cinfo = dir->npe_ctx + dir->npe_ctx_idx;
668 /* write cfg word to cryptinfo */
669 cfgword = algo->cfgword | ( authsize << 6); /* (authsize/4) << 8 */
671 cfgword ^= 0xAA000000; /* change the "byte swap" flags */
673 *(u32*)cinfo = cpu_to_be32(cfgword);
674 cinfo += sizeof(cfgword);
676 /* write ICV to cryptinfo */
677 memcpy(cinfo, algo->icv, digest_len);
680 itarget = dir->npe_ctx_phys + dir->npe_ctx_idx
681 + sizeof(algo->cfgword);
682 otarget = itarget + digest_len;
683 init_len = cinfo - (dir->npe_ctx + dir->npe_ctx_idx);
684 npe_ctx_addr = dir->npe_ctx_phys + dir->npe_ctx_idx;
686 dir->npe_ctx_idx += init_len;
687 dir->npe_mode |= NPE_OP_HASH_ENABLE;
690 dir->npe_mode |= NPE_OP_HASH_VERIFY;
692 ret = register_chain_var(tfm, HMAC_OPAD_VALUE, otarget,
693 init_len, npe_ctx_addr, key, key_len);
696 return register_chain_var(tfm, HMAC_IPAD_VALUE, itarget,
697 init_len, npe_ctx_addr, key, key_len);
700 static int gen_rev_aes_key(struct crypto_tfm *tfm)
702 struct crypt_ctl *crypt;
703 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
704 struct ix_sa_dir *dir = &ctx->decrypt;
706 crypt = get_crypt_desc_emerg();
710 *(u32*)dir->npe_ctx |= cpu_to_be32(CIPH_ENCR);
712 crypt->data.tfm = tfm;
713 crypt->crypt_offs = 0;
714 crypt->crypt_len = AES_BLOCK128;
716 crypt->crypto_ctx = dir->npe_ctx_phys;
717 crypt->icv_rev_aes = dir->npe_ctx_phys + sizeof(u32);
718 crypt->mode = NPE_OP_ENC_GEN_KEY;
719 crypt->init_len = dir->npe_ctx_idx;
720 crypt->ctl_flags |= CTL_FLAG_GEN_REVAES;
722 atomic_inc(&ctx->configuring);
723 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
724 BUG_ON(qmgr_stat_overflow(SEND_QID));
728 static int setup_cipher(struct crypto_tfm *tfm, int encrypt,
729 const u8 *key, int key_len)
734 struct ix_sa_dir *dir;
735 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
736 u32 *flags = &tfm->crt_flags;
738 dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
739 cinfo = dir->npe_ctx;
742 cipher_cfg = cipher_cfg_enc(tfm);
743 dir->npe_mode |= NPE_OP_CRYPT_ENCRYPT;
745 cipher_cfg = cipher_cfg_dec(tfm);
747 if (cipher_cfg & MOD_AES) {
749 case 16: keylen_cfg = MOD_AES128; break;
750 case 24: keylen_cfg = MOD_AES192; break;
751 case 32: keylen_cfg = MOD_AES256; break;
753 *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
756 cipher_cfg |= keylen_cfg;
758 u32 tmp[DES_EXPKEY_WORDS];
759 if (des_ekey(tmp, key) == 0) {
760 *flags |= CRYPTO_TFM_RES_WEAK_KEY;
763 /* write cfg word to cryptinfo */
764 *(u32*)cinfo = cpu_to_be32(cipher_cfg);
765 cinfo += sizeof(cipher_cfg);
767 /* write cipher key to cryptinfo */
768 memcpy(cinfo, key, key_len);
769 /* NPE wants keylen set to DES3_EDE_KEY_SIZE even for single DES */
770 if (key_len < DES3_EDE_KEY_SIZE && !(cipher_cfg & MOD_AES)) {
771 memset(cinfo + key_len, 0, DES3_EDE_KEY_SIZE -key_len);
772 key_len = DES3_EDE_KEY_SIZE;
774 dir->npe_ctx_idx = sizeof(cipher_cfg) + key_len;
775 dir->npe_mode |= NPE_OP_CRYPT_ENABLE;
776 if ((cipher_cfg & MOD_AES) && !encrypt) {
777 return gen_rev_aes_key(tfm);
782 static struct buffer_desc *chainup_buffers(struct device *dev,
783 struct scatterlist *sg, unsigned nbytes,
784 struct buffer_desc *buf, gfp_t flags,
785 enum dma_data_direction dir)
787 for (; nbytes > 0; sg = sg_next(sg)) {
788 unsigned len = min(nbytes, sg->length);
789 struct buffer_desc *next_buf;
795 next_buf = dma_pool_alloc(buffer_pool, flags, &next_buf_phys);
800 sg_dma_address(sg) = dma_map_single(dev, ptr, len, dir);
801 buf->next = next_buf;
802 buf->phys_next = next_buf_phys;
805 buf->phys_addr = sg_dma_address(sg);
814 static int ablk_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
815 unsigned int key_len)
817 struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
818 u32 *flags = &tfm->base.crt_flags;
821 init_completion(&ctx->completion);
822 atomic_inc(&ctx->configuring);
824 reset_sa_dir(&ctx->encrypt);
825 reset_sa_dir(&ctx->decrypt);
827 ctx->encrypt.npe_mode = NPE_OP_HMAC_DISABLE;
828 ctx->decrypt.npe_mode = NPE_OP_HMAC_DISABLE;
830 ret = setup_cipher(&tfm->base, 0, key, key_len);
833 ret = setup_cipher(&tfm->base, 1, key, key_len);
837 if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
838 if (*flags & CRYPTO_TFM_REQ_FORBID_WEAK_KEYS) {
841 *flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
845 if (!atomic_dec_and_test(&ctx->configuring))
846 wait_for_completion(&ctx->completion);
850 static int ablk_des3_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
851 unsigned int key_len)
853 u32 flags = crypto_ablkcipher_get_flags(tfm);
856 err = __des3_verify_key(&flags, key);
858 crypto_ablkcipher_set_flags(tfm, flags);
860 return ablk_setkey(tfm, key, key_len);
863 static int ablk_rfc3686_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
864 unsigned int key_len)
866 struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
868 /* the nonce is stored in bytes at end of key */
869 if (key_len < CTR_RFC3686_NONCE_SIZE)
872 memcpy(ctx->nonce, key + (key_len - CTR_RFC3686_NONCE_SIZE),
873 CTR_RFC3686_NONCE_SIZE);
875 key_len -= CTR_RFC3686_NONCE_SIZE;
876 return ablk_setkey(tfm, key, key_len);
879 static int ablk_perform(struct ablkcipher_request *req, int encrypt)
881 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
882 struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
883 unsigned ivsize = crypto_ablkcipher_ivsize(tfm);
884 struct ix_sa_dir *dir;
885 struct crypt_ctl *crypt;
886 unsigned int nbytes = req->nbytes;
887 enum dma_data_direction src_direction = DMA_BIDIRECTIONAL;
888 struct ablk_ctx *req_ctx = ablkcipher_request_ctx(req);
889 struct buffer_desc src_hook;
890 struct device *dev = &pdev->dev;
891 gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
892 GFP_KERNEL : GFP_ATOMIC;
894 if (qmgr_stat_full(SEND_QID))
896 if (atomic_read(&ctx->configuring))
899 dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
901 crypt = get_crypt_desc();
905 crypt->data.ablk_req = req;
906 crypt->crypto_ctx = dir->npe_ctx_phys;
907 crypt->mode = dir->npe_mode;
908 crypt->init_len = dir->npe_ctx_idx;
910 crypt->crypt_offs = 0;
911 crypt->crypt_len = nbytes;
913 BUG_ON(ivsize && !req->info);
914 memcpy(crypt->iv, req->info, ivsize);
915 if (req->src != req->dst) {
916 struct buffer_desc dst_hook;
917 crypt->mode |= NPE_OP_NOT_IN_PLACE;
918 /* This was never tested by Intel
919 * for more than one dst buffer, I think. */
921 if (!chainup_buffers(dev, req->dst, nbytes, &dst_hook,
922 flags, DMA_FROM_DEVICE))
924 src_direction = DMA_TO_DEVICE;
925 req_ctx->dst = dst_hook.next;
926 crypt->dst_buf = dst_hook.phys_next;
931 if (!chainup_buffers(dev, req->src, nbytes, &src_hook,
932 flags, src_direction))
935 req_ctx->src = src_hook.next;
936 crypt->src_buf = src_hook.phys_next;
937 crypt->ctl_flags |= CTL_FLAG_PERFORM_ABLK;
938 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
939 BUG_ON(qmgr_stat_overflow(SEND_QID));
943 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
945 if (req->src != req->dst) {
946 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
948 crypt->ctl_flags = CTL_FLAG_UNUSED;
952 static int ablk_encrypt(struct ablkcipher_request *req)
954 return ablk_perform(req, 1);
957 static int ablk_decrypt(struct ablkcipher_request *req)
959 return ablk_perform(req, 0);
962 static int ablk_rfc3686_crypt(struct ablkcipher_request *req)
964 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
965 struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
966 u8 iv[CTR_RFC3686_BLOCK_SIZE];
967 u8 *info = req->info;
970 /* set up counter block */
971 memcpy(iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
972 memcpy(iv + CTR_RFC3686_NONCE_SIZE, info, CTR_RFC3686_IV_SIZE);
974 /* initialize counter portion of counter block */
975 *(__be32 *)(iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
979 ret = ablk_perform(req, 1);
984 static int aead_perform(struct aead_request *req, int encrypt,
985 int cryptoffset, int eff_cryptlen, u8 *iv)
987 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
988 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
989 unsigned ivsize = crypto_aead_ivsize(tfm);
990 unsigned authsize = crypto_aead_authsize(tfm);
991 struct ix_sa_dir *dir;
992 struct crypt_ctl *crypt;
993 unsigned int cryptlen;
994 struct buffer_desc *buf, src_hook;
995 struct aead_ctx *req_ctx = aead_request_ctx(req);
996 struct device *dev = &pdev->dev;
997 gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
998 GFP_KERNEL : GFP_ATOMIC;
999 enum dma_data_direction src_direction = DMA_BIDIRECTIONAL;
1000 unsigned int lastlen;
1002 if (qmgr_stat_full(SEND_QID))
1004 if (atomic_read(&ctx->configuring))
1008 dir = &ctx->encrypt;
1009 cryptlen = req->cryptlen;
1011 dir = &ctx->decrypt;
1012 /* req->cryptlen includes the authsize when decrypting */
1013 cryptlen = req->cryptlen -authsize;
1014 eff_cryptlen -= authsize;
1016 crypt = get_crypt_desc();
1020 crypt->data.aead_req = req;
1021 crypt->crypto_ctx = dir->npe_ctx_phys;
1022 crypt->mode = dir->npe_mode;
1023 crypt->init_len = dir->npe_ctx_idx;
1025 crypt->crypt_offs = cryptoffset;
1026 crypt->crypt_len = eff_cryptlen;
1028 crypt->auth_offs = 0;
1029 crypt->auth_len = req->assoclen + cryptlen;
1030 BUG_ON(ivsize && !req->iv);
1031 memcpy(crypt->iv, req->iv, ivsize);
1033 buf = chainup_buffers(dev, req->src, crypt->auth_len,
1034 &src_hook, flags, src_direction);
1035 req_ctx->src = src_hook.next;
1036 crypt->src_buf = src_hook.phys_next;
1040 lastlen = buf->buf_len;
1041 if (lastlen >= authsize)
1042 crypt->icv_rev_aes = buf->phys_addr +
1043 buf->buf_len - authsize;
1045 req_ctx->dst = NULL;
1047 if (req->src != req->dst) {
1048 struct buffer_desc dst_hook;
1050 crypt->mode |= NPE_OP_NOT_IN_PLACE;
1051 src_direction = DMA_TO_DEVICE;
1053 buf = chainup_buffers(dev, req->dst, crypt->auth_len,
1054 &dst_hook, flags, DMA_FROM_DEVICE);
1055 req_ctx->dst = dst_hook.next;
1056 crypt->dst_buf = dst_hook.phys_next;
1062 lastlen = buf->buf_len;
1063 if (lastlen >= authsize)
1064 crypt->icv_rev_aes = buf->phys_addr +
1065 buf->buf_len - authsize;
1069 if (unlikely(lastlen < authsize)) {
1070 /* The 12 hmac bytes are scattered,
1071 * we need to copy them into a safe buffer */
1072 req_ctx->hmac_virt = dma_pool_alloc(buffer_pool, flags,
1073 &crypt->icv_rev_aes);
1074 if (unlikely(!req_ctx->hmac_virt))
1077 scatterwalk_map_and_copy(req_ctx->hmac_virt,
1078 req->src, cryptlen, authsize, 0);
1080 req_ctx->encrypt = encrypt;
1082 req_ctx->hmac_virt = NULL;
1085 crypt->ctl_flags |= CTL_FLAG_PERFORM_AEAD;
1086 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
1087 BUG_ON(qmgr_stat_overflow(SEND_QID));
1088 return -EINPROGRESS;
1091 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
1093 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
1094 crypt->ctl_flags = CTL_FLAG_UNUSED;
1098 static int aead_setup(struct crypto_aead *tfm, unsigned int authsize)
1100 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1101 u32 *flags = &tfm->base.crt_flags;
1102 unsigned digest_len = crypto_aead_maxauthsize(tfm);
1105 if (!ctx->enckey_len && !ctx->authkey_len)
1107 init_completion(&ctx->completion);
1108 atomic_inc(&ctx->configuring);
1110 reset_sa_dir(&ctx->encrypt);
1111 reset_sa_dir(&ctx->decrypt);
1113 ret = setup_cipher(&tfm->base, 0, ctx->enckey, ctx->enckey_len);
1116 ret = setup_cipher(&tfm->base, 1, ctx->enckey, ctx->enckey_len);
1119 ret = setup_auth(&tfm->base, 0, authsize, ctx->authkey,
1120 ctx->authkey_len, digest_len);
1123 ret = setup_auth(&tfm->base, 1, authsize, ctx->authkey,
1124 ctx->authkey_len, digest_len);
1128 if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
1129 if (*flags & CRYPTO_TFM_REQ_FORBID_WEAK_KEYS) {
1133 *flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
1137 if (!atomic_dec_and_test(&ctx->configuring))
1138 wait_for_completion(&ctx->completion);
1142 static int aead_setauthsize(struct crypto_aead *tfm, unsigned int authsize)
1144 int max = crypto_aead_maxauthsize(tfm) >> 2;
1146 if ((authsize>>2) < 1 || (authsize>>2) > max || (authsize & 3))
1148 return aead_setup(tfm, authsize);
1151 static int aead_setkey(struct crypto_aead *tfm, const u8 *key,
1152 unsigned int keylen)
1154 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1155 struct crypto_authenc_keys keys;
1157 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
1160 if (keys.authkeylen > sizeof(ctx->authkey))
1163 if (keys.enckeylen > sizeof(ctx->enckey))
1166 memcpy(ctx->authkey, keys.authkey, keys.authkeylen);
1167 memcpy(ctx->enckey, keys.enckey, keys.enckeylen);
1168 ctx->authkey_len = keys.authkeylen;
1169 ctx->enckey_len = keys.enckeylen;
1171 memzero_explicit(&keys, sizeof(keys));
1172 return aead_setup(tfm, crypto_aead_authsize(tfm));
1174 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1175 memzero_explicit(&keys, sizeof(keys));
1179 static int des3_aead_setkey(struct crypto_aead *tfm, const u8 *key,
1180 unsigned int keylen)
1182 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1183 u32 flags = CRYPTO_TFM_RES_BAD_KEY_LEN;
1184 struct crypto_authenc_keys keys;
1187 err = crypto_authenc_extractkeys(&keys, key, keylen);
1192 if (keys.authkeylen > sizeof(ctx->authkey))
1195 if (keys.enckeylen != DES3_EDE_KEY_SIZE)
1198 flags = crypto_aead_get_flags(tfm);
1199 err = __des3_verify_key(&flags, keys.enckey);
1203 memcpy(ctx->authkey, keys.authkey, keys.authkeylen);
1204 memcpy(ctx->enckey, keys.enckey, keys.enckeylen);
1205 ctx->authkey_len = keys.authkeylen;
1206 ctx->enckey_len = keys.enckeylen;
1208 memzero_explicit(&keys, sizeof(keys));
1209 return aead_setup(tfm, crypto_aead_authsize(tfm));
1211 crypto_aead_set_flags(tfm, flags);
1212 memzero_explicit(&keys, sizeof(keys));
1216 static int aead_encrypt(struct aead_request *req)
1218 return aead_perform(req, 1, req->assoclen, req->cryptlen, req->iv);
1221 static int aead_decrypt(struct aead_request *req)
1223 return aead_perform(req, 0, req->assoclen, req->cryptlen, req->iv);
1226 static struct ixp_alg ixp4xx_algos[] = {
1229 .cra_name = "cbc(des)",
1230 .cra_blocksize = DES_BLOCK_SIZE,
1231 .cra_u = { .ablkcipher = {
1232 .min_keysize = DES_KEY_SIZE,
1233 .max_keysize = DES_KEY_SIZE,
1234 .ivsize = DES_BLOCK_SIZE,
1238 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1239 .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1243 .cra_name = "ecb(des)",
1244 .cra_blocksize = DES_BLOCK_SIZE,
1245 .cra_u = { .ablkcipher = {
1246 .min_keysize = DES_KEY_SIZE,
1247 .max_keysize = DES_KEY_SIZE,
1251 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_ECB | KEYLEN_192,
1252 .cfg_dec = CIPH_DECR | MOD_DES | MOD_ECB | KEYLEN_192,
1255 .cra_name = "cbc(des3_ede)",
1256 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1257 .cra_u = { .ablkcipher = {
1258 .min_keysize = DES3_EDE_KEY_SIZE,
1259 .max_keysize = DES3_EDE_KEY_SIZE,
1260 .ivsize = DES3_EDE_BLOCK_SIZE,
1261 .setkey = ablk_des3_setkey,
1265 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1266 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1269 .cra_name = "ecb(des3_ede)",
1270 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1271 .cra_u = { .ablkcipher = {
1272 .min_keysize = DES3_EDE_KEY_SIZE,
1273 .max_keysize = DES3_EDE_KEY_SIZE,
1274 .setkey = ablk_des3_setkey,
1278 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_ECB | KEYLEN_192,
1279 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_ECB | KEYLEN_192,
1282 .cra_name = "cbc(aes)",
1283 .cra_blocksize = AES_BLOCK_SIZE,
1284 .cra_u = { .ablkcipher = {
1285 .min_keysize = AES_MIN_KEY_SIZE,
1286 .max_keysize = AES_MAX_KEY_SIZE,
1287 .ivsize = AES_BLOCK_SIZE,
1291 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1292 .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1295 .cra_name = "ecb(aes)",
1296 .cra_blocksize = AES_BLOCK_SIZE,
1297 .cra_u = { .ablkcipher = {
1298 .min_keysize = AES_MIN_KEY_SIZE,
1299 .max_keysize = AES_MAX_KEY_SIZE,
1303 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_ECB,
1304 .cfg_dec = CIPH_DECR | MOD_AES | MOD_ECB,
1307 .cra_name = "ctr(aes)",
1308 .cra_blocksize = AES_BLOCK_SIZE,
1309 .cra_u = { .ablkcipher = {
1310 .min_keysize = AES_MIN_KEY_SIZE,
1311 .max_keysize = AES_MAX_KEY_SIZE,
1312 .ivsize = AES_BLOCK_SIZE,
1316 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1317 .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1320 .cra_name = "rfc3686(ctr(aes))",
1321 .cra_blocksize = AES_BLOCK_SIZE,
1322 .cra_u = { .ablkcipher = {
1323 .min_keysize = AES_MIN_KEY_SIZE,
1324 .max_keysize = AES_MAX_KEY_SIZE,
1325 .ivsize = AES_BLOCK_SIZE,
1326 .setkey = ablk_rfc3686_setkey,
1327 .encrypt = ablk_rfc3686_crypt,
1328 .decrypt = ablk_rfc3686_crypt }
1331 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1332 .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1335 static struct ixp_aead_alg ixp4xx_aeads[] = {
1339 .cra_name = "authenc(hmac(md5),cbc(des))",
1340 .cra_blocksize = DES_BLOCK_SIZE,
1342 .ivsize = DES_BLOCK_SIZE,
1343 .maxauthsize = MD5_DIGEST_SIZE,
1345 .hash = &hash_alg_md5,
1346 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1347 .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1351 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
1352 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1354 .ivsize = DES3_EDE_BLOCK_SIZE,
1355 .maxauthsize = MD5_DIGEST_SIZE,
1356 .setkey = des3_aead_setkey,
1358 .hash = &hash_alg_md5,
1359 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1360 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1364 .cra_name = "authenc(hmac(sha1),cbc(des))",
1365 .cra_blocksize = DES_BLOCK_SIZE,
1367 .ivsize = DES_BLOCK_SIZE,
1368 .maxauthsize = SHA1_DIGEST_SIZE,
1370 .hash = &hash_alg_sha1,
1371 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1372 .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1376 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1377 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1379 .ivsize = DES3_EDE_BLOCK_SIZE,
1380 .maxauthsize = SHA1_DIGEST_SIZE,
1381 .setkey = des3_aead_setkey,
1383 .hash = &hash_alg_sha1,
1384 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1385 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1389 .cra_name = "authenc(hmac(md5),cbc(aes))",
1390 .cra_blocksize = AES_BLOCK_SIZE,
1392 .ivsize = AES_BLOCK_SIZE,
1393 .maxauthsize = MD5_DIGEST_SIZE,
1395 .hash = &hash_alg_md5,
1396 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1397 .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1401 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1402 .cra_blocksize = AES_BLOCK_SIZE,
1404 .ivsize = AES_BLOCK_SIZE,
1405 .maxauthsize = SHA1_DIGEST_SIZE,
1407 .hash = &hash_alg_sha1,
1408 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1409 .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1412 #define IXP_POSTFIX "-ixp4xx"
1414 static const struct platform_device_info ixp_dev_info __initdata = {
1415 .name = DRIVER_NAME,
1417 .dma_mask = DMA_BIT_MASK(32),
1420 static int __init ixp_module_init(void)
1422 int num = ARRAY_SIZE(ixp4xx_algos);
1425 pdev = platform_device_register_full(&ixp_dev_info);
1427 return PTR_ERR(pdev);
1429 spin_lock_init(&desc_lock);
1430 spin_lock_init(&emerg_lock);
1432 err = init_ixp_crypto(&pdev->dev);
1434 platform_device_unregister(pdev);
1437 for (i=0; i< num; i++) {
1438 struct crypto_alg *cra = &ixp4xx_algos[i].crypto;
1440 if (snprintf(cra->cra_driver_name, CRYPTO_MAX_ALG_NAME,
1441 "%s"IXP_POSTFIX, cra->cra_name) >=
1442 CRYPTO_MAX_ALG_NAME)
1446 if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES)) {
1451 cra->cra_type = &crypto_ablkcipher_type;
1452 cra->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1453 CRYPTO_ALG_KERN_DRIVER_ONLY |
1455 if (!cra->cra_ablkcipher.setkey)
1456 cra->cra_ablkcipher.setkey = ablk_setkey;
1457 if (!cra->cra_ablkcipher.encrypt)
1458 cra->cra_ablkcipher.encrypt = ablk_encrypt;
1459 if (!cra->cra_ablkcipher.decrypt)
1460 cra->cra_ablkcipher.decrypt = ablk_decrypt;
1461 cra->cra_init = init_tfm_ablk;
1463 cra->cra_ctxsize = sizeof(struct ixp_ctx);
1464 cra->cra_module = THIS_MODULE;
1465 cra->cra_alignmask = 3;
1466 cra->cra_priority = 300;
1467 cra->cra_exit = exit_tfm;
1468 if (crypto_register_alg(cra))
1469 printk(KERN_ERR "Failed to register '%s'\n",
1472 ixp4xx_algos[i].registered = 1;
1475 for (i = 0; i < ARRAY_SIZE(ixp4xx_aeads); i++) {
1476 struct aead_alg *cra = &ixp4xx_aeads[i].crypto;
1478 if (snprintf(cra->base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
1479 "%s"IXP_POSTFIX, cra->base.cra_name) >=
1480 CRYPTO_MAX_ALG_NAME)
1482 if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES))
1486 cra->base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1488 cra->setkey = cra->setkey ?: aead_setkey;
1489 cra->setauthsize = aead_setauthsize;
1490 cra->encrypt = aead_encrypt;
1491 cra->decrypt = aead_decrypt;
1492 cra->init = init_tfm_aead;
1493 cra->exit = exit_tfm_aead;
1495 cra->base.cra_ctxsize = sizeof(struct ixp_ctx);
1496 cra->base.cra_module = THIS_MODULE;
1497 cra->base.cra_alignmask = 3;
1498 cra->base.cra_priority = 300;
1500 if (crypto_register_aead(cra))
1501 printk(KERN_ERR "Failed to register '%s'\n",
1502 cra->base.cra_driver_name);
1504 ixp4xx_aeads[i].registered = 1;
1509 static void __exit ixp_module_exit(void)
1511 int num = ARRAY_SIZE(ixp4xx_algos);
1514 for (i = 0; i < ARRAY_SIZE(ixp4xx_aeads); i++) {
1515 if (ixp4xx_aeads[i].registered)
1516 crypto_unregister_aead(&ixp4xx_aeads[i].crypto);
1519 for (i=0; i< num; i++) {
1520 if (ixp4xx_algos[i].registered)
1521 crypto_unregister_alg(&ixp4xx_algos[i].crypto);
1523 release_ixp_crypto(&pdev->dev);
1524 platform_device_unregister(pdev);
1527 module_init(ixp_module_init);
1528 module_exit(ixp_module_exit);
1530 MODULE_LICENSE("GPL");
1531 MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>");
1532 MODULE_DESCRIPTION("IXP4xx hardware crypto");