drivers/crypto/ixp4xx_crypto.c

   1 /*
   2  * Intel IXP4xx NPE-C crypto driver
   3  *
   4  * Copyright (C) 2008 Christian Hohnstaedt <chohnstaedt@innominate.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License
   8  * as published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include <linux/platform_device.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/dmapool.h>
  15 #include <linux/crypto.h>
  16 #include <linux/kernel.h>
  17 #include <linux/rtnetlink.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/gfp.h>
  21 #include <linux/module.h>
  22
  23 #include <crypto/ctr.h>
  24 #include <crypto/des.h>
  25 #include <crypto/aes.h>
  26 #include <crypto/hmac.h>
  27 #include <crypto/sha.h>
  28 #include <crypto/algapi.h>
  29 #include <crypto/internal/aead.h>
  30 #include <crypto/authenc.h>
  31 #include <crypto/scatterwalk.h>
  32
  33 #include <mach/npe.h>
  34 #include <mach/qmgr.h>
  35
  36 #define MAX_KEYLEN 32
  37
  38 /* hash: cfgword + 2 * digestlen; crypt: keylen + cfgword */
  39 #define NPE_CTX_LEN 80
  40 #define AES_BLOCK128 16
  41
  42 #define NPE_OP_HASH_VERIFY   0x01
  43 #define NPE_OP_CCM_ENABLE    0x04
  44 #define NPE_OP_CRYPT_ENABLE  0x08
  45 #define NPE_OP_HASH_ENABLE   0x10
  46 #define NPE_OP_NOT_IN_PLACE  0x20
  47 #define NPE_OP_HMAC_DISABLE  0x40
  48 #define NPE_OP_CRYPT_ENCRYPT 0x80
  49
  50 #define NPE_OP_CCM_GEN_MIC   0xcc
  51 #define NPE_OP_HASH_GEN_ICV  0x50
  52 #define NPE_OP_ENC_GEN_KEY   0xc9
  53
  54 #define MOD_ECB     0x0000
  55 #define MOD_CTR     0x1000
  56 #define MOD_CBC_ENC 0x2000
  57 #define MOD_CBC_DEC 0x3000
  58 #define MOD_CCM_ENC 0x4000
  59 #define MOD_CCM_DEC 0x5000
  60
  61 #define KEYLEN_128  4
  62 #define KEYLEN_192  6
  63 #define KEYLEN_256  8
  64
  65 #define CIPH_DECR   0x0000
  66 #define CIPH_ENCR   0x0400
  67
  68 #define MOD_DES     0x0000
  69 #define MOD_TDEA2   0x0100
  70 #define MOD_3DES   0x0200
  71 #define MOD_AES     0x0800
  72 #define MOD_AES128  (0x0800 | KEYLEN_128)
  73 #define MOD_AES192  (0x0900 | KEYLEN_192)
  74 #define MOD_AES256  (0x0a00 | KEYLEN_256)
  75
  76 #define MAX_IVLEN   16
  77 #define NPE_ID      2  /* NPE C */
  78 #define NPE_QLEN    16
  79 /* Space for registering when the first
  80  * NPE_QLEN crypt_ctl are busy */
  81 #define NPE_QLEN_TOTAL 64
  82
  83 #define SEND_QID    29
  84 #define RECV_QID    30
  85
  86 #define CTL_FLAG_UNUSED         0x0000
  87 #define CTL_FLAG_USED           0x1000
  88 #define CTL_FLAG_PERFORM_ABLK   0x0001
  89 #define CTL_FLAG_GEN_ICV        0x0002
  90 #define CTL_FLAG_GEN_REVAES     0x0004
  91 #define CTL_FLAG_PERFORM_AEAD   0x0008
  92 #define CTL_FLAG_MASK           0x000f
  93
  94 #define HMAC_PAD_BLOCKLEN SHA1_BLOCK_SIZE
  95
  96 #define MD5_DIGEST_SIZE   16
  97
  98 struct buffer_desc {
  99         u32 phys_next;
 100 #ifdef __ARMEB__
 101         u16 buf_len;
 102         u16 pkt_len;
 103 #else
 104         u16 pkt_len;
 105         u16 buf_len;
 106 #endif
 107         u32 phys_addr;
 108         u32 __reserved[4];
 109         struct buffer_desc *next;
 110         enum dma_data_direction dir;
 111 };
 112
 113 struct crypt_ctl {
 114 #ifdef __ARMEB__
 115         u8 mode;                /* NPE_OP_*  operation mode */
 116         u8 init_len;
 117         u16 reserved;
 118 #else
 119         u16 reserved;
 120         u8 init_len;
 121         u8 mode;                /* NPE_OP_*  operation mode */
 122 #endif
 123         u8 iv[MAX_IVLEN];       /* IV for CBC mode or CTR IV for CTR mode */
 124         u32 icv_rev_aes;        /* icv or rev aes */
 125         u32 src_buf;
 126         u32 dst_buf;
 127 #ifdef __ARMEB__
 128         u16 auth_offs;          /* Authentication start offset */
 129         u16 auth_len;           /* Authentication data length */
 130         u16 crypt_offs;         /* Cryption start offset */
 131         u16 crypt_len;          /* Cryption data length */
 132 #else
 133         u16 auth_len;           /* Authentication data length */
 134         u16 auth_offs;          /* Authentication start offset */
 135         u16 crypt_len;          /* Cryption data length */
 136         u16 crypt_offs;         /* Cryption start offset */
 137 #endif
 138         u32 aadAddr;            /* Additional Auth Data Addr for CCM mode */
 139         u32 crypto_ctx;         /* NPE Crypto Param structure address */
 140
 141         /* Used by Host: 4*4 bytes*/
 142         unsigned ctl_flags;
 143         union {
 144                 struct ablkcipher_request *ablk_req;
 145                 struct aead_request *aead_req;
 146                 struct crypto_tfm *tfm;
 147         } data;
 148         struct buffer_desc *regist_buf;
 149         u8 *regist_ptr;
 150 };
 151
 152 struct ablk_ctx {
 153         struct buffer_desc *src;
 154         struct buffer_desc *dst;
 155 };
 156
 157 struct aead_ctx {
 158         struct buffer_desc *src;
 159         struct buffer_desc *dst;
 160         struct scatterlist ivlist;
 161         /* used when the hmac is not on one sg entry */
 162         u8 *hmac_virt;
 163         int encrypt;
 164 };
 165
 166 struct ix_hash_algo {
 167         u32 cfgword;
 168         unsigned char *icv;
 169 };
 170
 171 struct ix_sa_dir {
 172         unsigned char *npe_ctx;
 173         dma_addr_t npe_ctx_phys;
 174         int npe_ctx_idx;
 175         u8 npe_mode;
 176 };
 177
 178 struct ixp_ctx {
 179         struct ix_sa_dir encrypt;
 180         struct ix_sa_dir decrypt;
 181         int authkey_len;
 182         u8 authkey[MAX_KEYLEN];
 183         int enckey_len;
 184         u8 enckey[MAX_KEYLEN];
 185         u8 salt[MAX_IVLEN];
 186         u8 nonce[CTR_RFC3686_NONCE_SIZE];
 187         unsigned salted;
 188         atomic_t configuring;
 189         struct completion completion;
 190 };
 191
 192 struct ixp_alg {
 193         struct crypto_alg crypto;
 194         const struct ix_hash_algo *hash;
 195         u32 cfg_enc;
 196         u32 cfg_dec;
 197
 198         int registered;
 199 };
 200
 201 struct ixp_aead_alg {
 202         struct aead_alg crypto;
 203         const struct ix_hash_algo *hash;
 204         u32 cfg_enc;
 205         u32 cfg_dec;
 206
 207         int registered;
 208 };
 209
 210 static const struct ix_hash_algo hash_alg_md5 = {
 211         .cfgword        = 0xAA010004,
 212         .icv            = "\x01\x23\x45\x67\x89\xAB\xCD\xEF"
 213                           "\xFE\xDC\xBA\x98\x76\x54\x32\x10",
 214 };
 215 static const struct ix_hash_algo hash_alg_sha1 = {
 216         .cfgword        = 0x00000005,
 217         .icv            = "\x67\x45\x23\x01\xEF\xCD\xAB\x89\x98\xBA"
 218                           "\xDC\xFE\x10\x32\x54\x76\xC3\xD2\xE1\xF0",
 219 };
 220
 221 static struct npe *npe_c;
 222 static struct dma_pool *buffer_pool = NULL;
 223 static struct dma_pool *ctx_pool = NULL;
 224
 225 static struct crypt_ctl *crypt_virt = NULL;
 226 static dma_addr_t crypt_phys;
 227
 228 static int support_aes = 1;
 229
 230 #define DRIVER_NAME "ixp4xx_crypto"
 231
 232 static struct platform_device *pdev;
 233
 234 static inline dma_addr_t crypt_virt2phys(struct crypt_ctl *virt)
 235 {
 236         return crypt_phys + (virt - crypt_virt) * sizeof(struct crypt_ctl);
 237 }
 238
 239 static inline struct crypt_ctl *crypt_phys2virt(dma_addr_t phys)
 240 {
 241         return crypt_virt + (phys - crypt_phys) / sizeof(struct crypt_ctl);
 242 }
 243
 244 static inline u32 cipher_cfg_enc(struct crypto_tfm *tfm)
 245 {
 246         return container_of(tfm->__crt_alg, struct ixp_alg,crypto)->cfg_enc;
 247 }
 248
 249 static inline u32 cipher_cfg_dec(struct crypto_tfm *tfm)
 250 {
 251         return container_of(tfm->__crt_alg, struct ixp_alg,crypto)->cfg_dec;
 252 }
 253
 254 static inline const struct ix_hash_algo *ix_hash(struct crypto_tfm *tfm)
 255 {
 256         return container_of(tfm->__crt_alg, struct ixp_alg, crypto)->hash;
 257 }
 258
 259 static int setup_crypt_desc(void)
 260 {
 261         struct device *dev = &pdev->dev;
 262         BUILD_BUG_ON(sizeof(struct crypt_ctl) != 64);
 263         crypt_virt = dma_alloc_coherent(dev,
 264                         NPE_QLEN * sizeof(struct crypt_ctl),
 265                         &crypt_phys, GFP_ATOMIC);
 266         if (!crypt_virt)
 267                 return -ENOMEM;
 268         memset(crypt_virt, 0, NPE_QLEN * sizeof(struct crypt_ctl));
 269         return 0;
 270 }
 271
 272 static spinlock_t desc_lock;
 273 static struct crypt_ctl *get_crypt_desc(void)
 274 {
 275         int i;
 276         static int idx = 0;
 277         unsigned long flags;
 278
 279         spin_lock_irqsave(&desc_lock, flags);
 280
 281         if (unlikely(!crypt_virt))
 282                 setup_crypt_desc();
 283         if (unlikely(!crypt_virt)) {
 284                 spin_unlock_irqrestore(&desc_lock, flags);
 285                 return NULL;
 286         }
 287         i = idx;
 288         if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
 289                 if (++idx >= NPE_QLEN)
 290                         idx = 0;
 291                 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
 292                 spin_unlock_irqrestore(&desc_lock, flags);
 293                 return crypt_virt +i;
 294         } else {
 295                 spin_unlock_irqrestore(&desc_lock, flags);
 296                 return NULL;
 297         }
 298 }
 299
 300 static spinlock_t emerg_lock;
 301 static struct crypt_ctl *get_crypt_desc_emerg(void)
 302 {
 303         int i;
 304         static int idx = NPE_QLEN;
 305         struct crypt_ctl *desc;
 306         unsigned long flags;
 307
 308         desc = get_crypt_desc();
 309         if (desc)
 310                 return desc;
 311         if (unlikely(!crypt_virt))
 312                 return NULL;
 313
 314         spin_lock_irqsave(&emerg_lock, flags);
 315         i = idx;
 316         if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
 317                 if (++idx >= NPE_QLEN_TOTAL)
 318                         idx = NPE_QLEN;
 319                 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
 320                 spin_unlock_irqrestore(&emerg_lock, flags);
 321                 return crypt_virt +i;
 322         } else {
 323                 spin_unlock_irqrestore(&emerg_lock, flags);
 324                 return NULL;
 325         }
 326 }
 327
 328 static void free_buf_chain(struct device *dev, struct buffer_desc *buf,u32 phys)
 329 {
 330         while (buf) {
 331                 struct buffer_desc *buf1;
 332                 u32 phys1;
 333
 334                 buf1 = buf->next;
 335                 phys1 = buf->phys_next;
 336                 dma_unmap_single(dev, buf->phys_next, buf->buf_len, buf->dir);
 337                 dma_pool_free(buffer_pool, buf, phys);
 338                 buf = buf1;
 339                 phys = phys1;
 340         }
 341 }
 342
 343 static struct tasklet_struct crypto_done_tasklet;
 344
 345 static void finish_scattered_hmac(struct crypt_ctl *crypt)
 346 {
 347         struct aead_request *req = crypt->data.aead_req;
 348         struct aead_ctx *req_ctx = aead_request_ctx(req);
 349         struct crypto_aead *tfm = crypto_aead_reqtfm(req);
 350         int authsize = crypto_aead_authsize(tfm);
 351         int decryptlen = req->assoclen + req->cryptlen - authsize;
 352
 353         if (req_ctx->encrypt) {
 354                 scatterwalk_map_and_copy(req_ctx->hmac_virt,
 355                         req->dst, decryptlen, authsize, 1);
 356         }
 357         dma_pool_free(buffer_pool, req_ctx->hmac_virt, crypt->icv_rev_aes);
 358 }
 359
 360 static void one_packet(dma_addr_t phys)
 361 {
 362         struct device *dev = &pdev->dev;
 363         struct crypt_ctl *crypt;
 364         struct ixp_ctx *ctx;
 365         int failed;
 366
 367         failed = phys & 0x1 ? -EBADMSG : 0;
 368         phys &= ~0x3;
 369         crypt = crypt_phys2virt(phys);
 370
 371         switch (crypt->ctl_flags & CTL_FLAG_MASK) {
 372         case CTL_FLAG_PERFORM_AEAD: {
 373                 struct aead_request *req = crypt->data.aead_req;
 374                 struct aead_ctx *req_ctx = aead_request_ctx(req);
 375
 376                 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
 377                 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
 378                 if (req_ctx->hmac_virt) {
 379                         finish_scattered_hmac(crypt);
 380                 }
 381                 req->base.complete(&req->base, failed);
 382                 break;
 383         }
 384         case CTL_FLAG_PERFORM_ABLK: {
 385                 struct ablkcipher_request *req = crypt->data.ablk_req;
 386                 struct ablk_ctx *req_ctx = ablkcipher_request_ctx(req);
 387
 388                 if (req_ctx->dst) {
 389                         free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
 390                 }
 391                 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
 392                 req->base.complete(&req->base, failed);
 393                 break;
 394         }
 395         case CTL_FLAG_GEN_ICV:
 396                 ctx = crypto_tfm_ctx(crypt->data.tfm);
 397                 dma_pool_free(ctx_pool, crypt->regist_ptr,
 398                                 crypt->regist_buf->phys_addr);
 399                 dma_pool_free(buffer_pool, crypt->regist_buf, crypt->src_buf);
 400                 if (atomic_dec_and_test(&ctx->configuring))
 401                         complete(&ctx->completion);
 402                 break;
 403         case CTL_FLAG_GEN_REVAES:
 404                 ctx = crypto_tfm_ctx(crypt->data.tfm);
 405                 *(u32*)ctx->decrypt.npe_ctx &= cpu_to_be32(~CIPH_ENCR);
 406                 if (atomic_dec_and_test(&ctx->configuring))
 407                         complete(&ctx->completion);
 408                 break;
 409         default:
 410                 BUG();
 411         }
 412         crypt->ctl_flags = CTL_FLAG_UNUSED;
 413 }
 414
 415 static void irqhandler(void *_unused)
 416 {
 417         tasklet_schedule(&crypto_done_tasklet);
 418 }
 419
 420 static void crypto_done_action(unsigned long arg)
 421 {
 422         int i;
 423
 424         for(i=0; i<4; i++) {
 425                 dma_addr_t phys = qmgr_get_entry(RECV_QID);
 426                 if (!phys)
 427                         return;
 428                 one_packet(phys);
 429         }
 430         tasklet_schedule(&crypto_done_tasklet);
 431 }
 432
 433 static int init_ixp_crypto(struct device *dev)
 434 {
 435         int ret = -ENODEV;
 436         u32 msg[2] = { 0, 0 };
 437
 438         if (! ( ~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH |
 439                                 IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) {
 440                 printk(KERN_ERR "ixp_crypto: No HW crypto available\n");
 441                 return ret;
 442         }
 443         npe_c = npe_request(NPE_ID);
 444         if (!npe_c)
 445                 return ret;
 446
 447         if (!npe_running(npe_c)) {
 448                 ret = npe_load_firmware(npe_c, npe_name(npe_c), dev);
 449                 if (ret)
 450                         goto npe_release;
 451                 if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
 452                         goto npe_error;
 453         } else {
 454                 if (npe_send_message(npe_c, msg, "STATUS_MSG"))
 455                         goto npe_error;
 456
 457                 if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
 458                         goto npe_error;
 459         }
 460
 461         switch ((msg[1]>>16) & 0xff) {
 462         case 3:
 463                 printk(KERN_WARNING "Firmware of %s lacks AES support\n",
 464                                 npe_name(npe_c));
 465                 support_aes = 0;
 466                 break;
 467         case 4:
 468         case 5:
 469                 support_aes = 1;
 470                 break;
 471         default:
 472                 printk(KERN_ERR "Firmware of %s lacks crypto support\n",
 473                         npe_name(npe_c));
 474                 ret = -ENODEV;
 475                 goto npe_release;
 476         }
 477         /* buffer_pool will also be used to sometimes store the hmac,
 478          * so assure it is large enough
 479          */
 480         BUILD_BUG_ON(SHA1_DIGEST_SIZE > sizeof(struct buffer_desc));
 481         buffer_pool = dma_pool_create("buffer", dev,
 482                         sizeof(struct buffer_desc), 32, 0);
 483         ret = -ENOMEM;
 484         if (!buffer_pool) {
 485                 goto err;
 486         }
 487         ctx_pool = dma_pool_create("context", dev,
 488                         NPE_CTX_LEN, 16, 0);
 489         if (!ctx_pool) {
 490                 goto err;
 491         }
 492         ret = qmgr_request_queue(SEND_QID, NPE_QLEN_TOTAL, 0, 0,
 493                                  "ixp_crypto:out", NULL);
 494         if (ret)
 495                 goto err;
 496         ret = qmgr_request_queue(RECV_QID, NPE_QLEN, 0, 0,
 497                                  "ixp_crypto:in", NULL);
 498         if (ret) {
 499                 qmgr_release_queue(SEND_QID);
 500                 goto err;
 501         }
 502         qmgr_set_irq(RECV_QID, QUEUE_IRQ_SRC_NOT_EMPTY, irqhandler, NULL);
 503         tasklet_init(&crypto_done_tasklet, crypto_done_action, 0);
 504
 505         qmgr_enable_irq(RECV_QID);
 506         return 0;
 507
 508 npe_error:
 509         printk(KERN_ERR "%s not responding\n", npe_name(npe_c));
 510         ret = -EIO;
 511 err:
 512         dma_pool_destroy(ctx_pool);
 513         dma_pool_destroy(buffer_pool);
 514 npe_release:
 515         npe_release(npe_c);
 516         return ret;
 517 }
 518
 519 static void release_ixp_crypto(struct device *dev)
 520 {
 521         qmgr_disable_irq(RECV_QID);
 522         tasklet_kill(&crypto_done_tasklet);
 523
 524         qmgr_release_queue(SEND_QID);
 525         qmgr_release_queue(RECV_QID);
 526
 527         dma_pool_destroy(ctx_pool);
 528         dma_pool_destroy(buffer_pool);
 529
 530         npe_release(npe_c);
 531
 532         if (crypt_virt) {
 533                 dma_free_coherent(dev,
 534                         NPE_QLEN_TOTAL * sizeof( struct crypt_ctl),
 535                         crypt_virt, crypt_phys);
 536         }
 537 }
 538
 539 static void reset_sa_dir(struct ix_sa_dir *dir)
 540 {
 541         memset(dir->npe_ctx, 0, NPE_CTX_LEN);
 542         dir->npe_ctx_idx = 0;
 543         dir->npe_mode = 0;
 544 }
 545
 546 static int init_sa_dir(struct ix_sa_dir *dir)
 547 {
 548         dir->npe_ctx = dma_pool_alloc(ctx_pool, GFP_KERNEL, &dir->npe_ctx_phys);
 549         if (!dir->npe_ctx) {
 550                 return -ENOMEM;
 551         }
 552         reset_sa_dir(dir);
 553         return 0;
 554 }
 555
 556 static void free_sa_dir(struct ix_sa_dir *dir)
 557 {
 558         memset(dir->npe_ctx, 0, NPE_CTX_LEN);
 559         dma_pool_free(ctx_pool, dir->npe_ctx, dir->npe_ctx_phys);
 560 }
 561
 562 static int init_tfm(struct crypto_tfm *tfm)
 563 {
 564         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 565         int ret;
 566
 567         atomic_set(&ctx->configuring, 0);
 568         ret = init_sa_dir(&ctx->encrypt);
 569         if (ret)
 570                 return ret;
 571         ret = init_sa_dir(&ctx->decrypt);
 572         if (ret) {
 573                 free_sa_dir(&ctx->encrypt);
 574         }
 575         return ret;
 576 }
 577
 578 static int init_tfm_ablk(struct crypto_tfm *tfm)
 579 {
 580         tfm->crt_ablkcipher.reqsize = sizeof(struct ablk_ctx);
 581         return init_tfm(tfm);
 582 }
 583
 584 static int init_tfm_aead(struct crypto_aead *tfm)
 585 {
 586         crypto_aead_set_reqsize(tfm, sizeof(struct aead_ctx));
 587         return init_tfm(crypto_aead_tfm(tfm));
 588 }
 589
 590 static void exit_tfm(struct crypto_tfm *tfm)
 591 {
 592         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 593         free_sa_dir(&ctx->encrypt);
 594         free_sa_dir(&ctx->decrypt);
 595 }
 596
 597 static void exit_tfm_aead(struct crypto_aead *tfm)
 598 {
 599         exit_tfm(crypto_aead_tfm(tfm));
 600 }
 601
 602 static int register_chain_var(struct crypto_tfm *tfm, u8 xpad, u32 target,
 603                 int init_len, u32 ctx_addr, const u8 *key, int key_len)
 604 {
 605         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 606         struct crypt_ctl *crypt;
 607         struct buffer_desc *buf;
 608         int i;
 609         u8 *pad;
 610         u32 pad_phys, buf_phys;
 611
 612         BUILD_BUG_ON(NPE_CTX_LEN < HMAC_PAD_BLOCKLEN);
 613         pad = dma_pool_alloc(ctx_pool, GFP_KERNEL, &pad_phys);
 614         if (!pad)
 615                 return -ENOMEM;
 616         buf = dma_pool_alloc(buffer_pool, GFP_KERNEL, &buf_phys);
 617         if (!buf) {
 618                 dma_pool_free(ctx_pool, pad, pad_phys);
 619                 return -ENOMEM;
 620         }
 621         crypt = get_crypt_desc_emerg();
 622         if (!crypt) {
 623                 dma_pool_free(ctx_pool, pad, pad_phys);
 624                 dma_pool_free(buffer_pool, buf, buf_phys);
 625                 return -EAGAIN;
 626         }
 627
 628         memcpy(pad, key, key_len);
 629         memset(pad + key_len, 0, HMAC_PAD_BLOCKLEN - key_len);
 630         for (i = 0; i < HMAC_PAD_BLOCKLEN; i++) {
 631                 pad[i] ^= xpad;
 632         }
 633
 634         crypt->data.tfm = tfm;
 635         crypt->regist_ptr = pad;
 636         crypt->regist_buf = buf;
 637
 638         crypt->auth_offs = 0;
 639         crypt->auth_len = HMAC_PAD_BLOCKLEN;
 640         crypt->crypto_ctx = ctx_addr;
 641         crypt->src_buf = buf_phys;
 642         crypt->icv_rev_aes = target;
 643         crypt->mode = NPE_OP_HASH_GEN_ICV;
 644         crypt->init_len = init_len;
 645         crypt->ctl_flags |= CTL_FLAG_GEN_ICV;
 646
 647         buf->next = 0;
 648         buf->buf_len = HMAC_PAD_BLOCKLEN;
 649         buf->pkt_len = 0;
 650         buf->phys_addr = pad_phys;
 651
 652         atomic_inc(&ctx->configuring);
 653         qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
 654         BUG_ON(qmgr_stat_overflow(SEND_QID));
 655         return 0;
 656 }
 657
 658 static int setup_auth(struct crypto_tfm *tfm, int encrypt, unsigned authsize,
 659                 const u8 *key, int key_len, unsigned digest_len)
 660 {
 661         u32 itarget, otarget, npe_ctx_addr;
 662         unsigned char *cinfo;
 663         int init_len, ret = 0;
 664         u32 cfgword;
 665         struct ix_sa_dir *dir;
 666         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 667         const struct ix_hash_algo *algo;
 668
 669         dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
 670         cinfo = dir->npe_ctx + dir->npe_ctx_idx;
 671         algo = ix_hash(tfm);
 672
 673         /* write cfg word to cryptinfo */
 674         cfgword = algo->cfgword | ( authsize << 6); /* (authsize/4) << 8 */
 675 #ifndef __ARMEB__
 676         cfgword ^= 0xAA000000; /* change the "byte swap" flags */
 677 #endif
 678         *(u32*)cinfo = cpu_to_be32(cfgword);
 679         cinfo += sizeof(cfgword);
 680
 681         /* write ICV to cryptinfo */
 682         memcpy(cinfo, algo->icv, digest_len);
 683         cinfo += digest_len;
 684
 685         itarget = dir->npe_ctx_phys + dir->npe_ctx_idx
 686                                 + sizeof(algo->cfgword);
 687         otarget = itarget + digest_len;
 688         init_len = cinfo - (dir->npe_ctx + dir->npe_ctx_idx);
 689         npe_ctx_addr = dir->npe_ctx_phys + dir->npe_ctx_idx;
 690
 691         dir->npe_ctx_idx += init_len;
 692         dir->npe_mode |= NPE_OP_HASH_ENABLE;
 693
 694         if (!encrypt)
 695                 dir->npe_mode |= NPE_OP_HASH_VERIFY;
 696
 697         ret = register_chain_var(tfm, HMAC_OPAD_VALUE, otarget,
 698                         init_len, npe_ctx_addr, key, key_len);
 699         if (ret)
 700                 return ret;
 701         return register_chain_var(tfm, HMAC_IPAD_VALUE, itarget,
 702                         init_len, npe_ctx_addr, key, key_len);
 703 }
 704
 705 static int gen_rev_aes_key(struct crypto_tfm *tfm)
 706 {
 707         struct crypt_ctl *crypt;
 708         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 709         struct ix_sa_dir *dir = &ctx->decrypt;
 710
 711         crypt = get_crypt_desc_emerg();
 712         if (!crypt) {
 713                 return -EAGAIN;
 714         }
 715         *(u32*)dir->npe_ctx |= cpu_to_be32(CIPH_ENCR);
 716
 717         crypt->data.tfm = tfm;
 718         crypt->crypt_offs = 0;
 719         crypt->crypt_len = AES_BLOCK128;
 720         crypt->src_buf = 0;
 721         crypt->crypto_ctx = dir->npe_ctx_phys;
 722         crypt->icv_rev_aes = dir->npe_ctx_phys + sizeof(u32);
 723         crypt->mode = NPE_OP_ENC_GEN_KEY;
 724         crypt->init_len = dir->npe_ctx_idx;
 725         crypt->ctl_flags |= CTL_FLAG_GEN_REVAES;
 726
 727         atomic_inc(&ctx->configuring);
 728         qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
 729         BUG_ON(qmgr_stat_overflow(SEND_QID));
 730         return 0;
 731 }
 732
 733 static int setup_cipher(struct crypto_tfm *tfm, int encrypt,
 734                 const u8 *key, int key_len)
 735 {
 736         u8 *cinfo;
 737         u32 cipher_cfg;
 738         u32 keylen_cfg = 0;
 739         struct ix_sa_dir *dir;
 740         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 741         u32 *flags = &tfm->crt_flags;
 742
 743         dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
 744         cinfo = dir->npe_ctx;
 745
 746         if (encrypt) {
 747                 cipher_cfg = cipher_cfg_enc(tfm);
 748                 dir->npe_mode |= NPE_OP_CRYPT_ENCRYPT;
 749         } else {
 750                 cipher_cfg = cipher_cfg_dec(tfm);
 751         }
 752         if (cipher_cfg & MOD_AES) {
 753                 switch (key_len) {
 754                 case 16: keylen_cfg = MOD_AES128; break;
 755                 case 24: keylen_cfg = MOD_AES192; break;
 756                 case 32: keylen_cfg = MOD_AES256; break;
 757                 default:
 758                         *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
 759                         return -EINVAL;
 760                 }
 761                 cipher_cfg |= keylen_cfg;
 762         } else if (cipher_cfg & MOD_3DES) {
 763                 const u32 *K = (const u32 *)key;
 764                 if (unlikely(!((K[0] ^ K[2]) | (K[1] ^ K[3])) ||
 765                              !((K[2] ^ K[4]) | (K[3] ^ K[5]))))
 766                 {
 767                         *flags |= CRYPTO_TFM_RES_BAD_KEY_SCHED;
 768                         return -EINVAL;
 769                 }
 770         } else {
 771                 u32 tmp[DES_EXPKEY_WORDS];
 772                 if (des_ekey(tmp, key) == 0) {
 773                         *flags |= CRYPTO_TFM_RES_WEAK_KEY;
 774                 }
 775         }
 776         /* write cfg word to cryptinfo */
 777         *(u32*)cinfo = cpu_to_be32(cipher_cfg);
 778         cinfo += sizeof(cipher_cfg);
 779
 780         /* write cipher key to cryptinfo */
 781         memcpy(cinfo, key, key_len);
 782         /* NPE wants keylen set to DES3_EDE_KEY_SIZE even for single DES */
 783         if (key_len < DES3_EDE_KEY_SIZE && !(cipher_cfg & MOD_AES)) {
 784                 memset(cinfo + key_len, 0, DES3_EDE_KEY_SIZE -key_len);
 785                 key_len = DES3_EDE_KEY_SIZE;
 786         }
 787         dir->npe_ctx_idx = sizeof(cipher_cfg) + key_len;
 788         dir->npe_mode |= NPE_OP_CRYPT_ENABLE;
 789         if ((cipher_cfg & MOD_AES) && !encrypt) {
 790                 return gen_rev_aes_key(tfm);
 791         }
 792         return 0;
 793 }
 794
 795 static struct buffer_desc *chainup_buffers(struct device *dev,
 796                 struct scatterlist *sg, unsigned nbytes,
 797                 struct buffer_desc *buf, gfp_t flags,
 798                 enum dma_data_direction dir)
 799 {
 800         for (; nbytes > 0; sg = sg_next(sg)) {
 801                 unsigned len = min(nbytes, sg->length);
 802                 struct buffer_desc *next_buf;
 803                 u32 next_buf_phys;
 804                 void *ptr;
 805
 806                 nbytes -= len;
 807                 ptr = sg_virt(sg);
 808                 next_buf = dma_pool_alloc(buffer_pool, flags, &next_buf_phys);
 809                 if (!next_buf) {
 810                         buf = NULL;
 811                         break;
 812                 }
 813                 sg_dma_address(sg) = dma_map_single(dev, ptr, len, dir);
 814                 buf->next = next_buf;
 815                 buf->phys_next = next_buf_phys;
 816                 buf = next_buf;
 817
 818                 buf->phys_addr = sg_dma_address(sg);
 819                 buf->buf_len = len;
 820                 buf->dir = dir;
 821         }
 822         buf->next = NULL;
 823         buf->phys_next = 0;
 824         return buf;
 825 }
 826
 827 static int ablk_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
 828                         unsigned int key_len)
 829 {
 830         struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
 831         u32 *flags = &tfm->base.crt_flags;
 832         int ret;
 833
 834         init_completion(&ctx->completion);
 835         atomic_inc(&ctx->configuring);
 836
 837         reset_sa_dir(&ctx->encrypt);
 838         reset_sa_dir(&ctx->decrypt);
 839
 840         ctx->encrypt.npe_mode = NPE_OP_HMAC_DISABLE;
 841         ctx->decrypt.npe_mode = NPE_OP_HMAC_DISABLE;
 842
 843         ret = setup_cipher(&tfm->base, 0, key, key_len);
 844         if (ret)
 845                 goto out;
 846         ret = setup_cipher(&tfm->base, 1, key, key_len);
 847         if (ret)
 848                 goto out;
 849
 850         if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
 851                 if (*flags & CRYPTO_TFM_REQ_WEAK_KEY) {
 852                         ret = -EINVAL;
 853                 } else {
 854                         *flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
 855                 }
 856         }
 857 out:
 858         if (!atomic_dec_and_test(&ctx->configuring))
 859                 wait_for_completion(&ctx->completion);
 860         return ret;
 861 }
 862
 863 static int ablk_rfc3686_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
 864                 unsigned int key_len)
 865 {
 866         struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
 867
 868         /* the nonce is stored in bytes at end of key */
 869         if (key_len < CTR_RFC3686_NONCE_SIZE)
 870                 return -EINVAL;
 871
 872         memcpy(ctx->nonce, key + (key_len - CTR_RFC3686_NONCE_SIZE),
 873                         CTR_RFC3686_NONCE_SIZE);
 874
 875         key_len -= CTR_RFC3686_NONCE_SIZE;
 876         return ablk_setkey(tfm, key, key_len);
 877 }
 878
 879 static int ablk_perform(struct ablkcipher_request *req, int encrypt)
 880 {
 881         struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
 882         struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
 883         unsigned ivsize = crypto_ablkcipher_ivsize(tfm);
 884         struct ix_sa_dir *dir;
 885         struct crypt_ctl *crypt;
 886         unsigned int nbytes = req->nbytes;
 887         enum dma_data_direction src_direction = DMA_BIDIRECTIONAL;
 888         struct ablk_ctx *req_ctx = ablkcipher_request_ctx(req);
 889         struct buffer_desc src_hook;
 890         struct device *dev = &pdev->dev;
 891         gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
 892                                 GFP_KERNEL : GFP_ATOMIC;
 893
 894         if (qmgr_stat_full(SEND_QID))
 895                 return -EAGAIN;
 896         if (atomic_read(&ctx->configuring))
 897                 return -EAGAIN;
 898
 899         dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
 900
 901         crypt = get_crypt_desc();
 902         if (!crypt)
 903                 return -ENOMEM;
 904
 905         crypt->data.ablk_req = req;
 906         crypt->crypto_ctx = dir->npe_ctx_phys;
 907         crypt->mode = dir->npe_mode;
 908         crypt->init_len = dir->npe_ctx_idx;
 909
 910         crypt->crypt_offs = 0;
 911         crypt->crypt_len = nbytes;
 912
 913         BUG_ON(ivsize && !req->info);
 914         memcpy(crypt->iv, req->info, ivsize);
 915         if (req->src != req->dst) {
 916                 struct buffer_desc dst_hook;
 917                 crypt->mode |= NPE_OP_NOT_IN_PLACE;
 918                 /* This was never tested by Intel
 919                  * for more than one dst buffer, I think. */
 920                 req_ctx->dst = NULL;
 921                 if (!chainup_buffers(dev, req->dst, nbytes, &dst_hook,
 922                                         flags, DMA_FROM_DEVICE))
 923                         goto free_buf_dest;
 924                 src_direction = DMA_TO_DEVICE;
 925                 req_ctx->dst = dst_hook.next;
 926                 crypt->dst_buf = dst_hook.phys_next;
 927         } else {
 928                 req_ctx->dst = NULL;
 929         }
 930         req_ctx->src = NULL;
 931         if (!chainup_buffers(dev, req->src, nbytes, &src_hook,
 932                                 flags, src_direction))
 933                 goto free_buf_src;
 934
 935         req_ctx->src = src_hook.next;
 936         crypt->src_buf = src_hook.phys_next;
 937         crypt->ctl_flags |= CTL_FLAG_PERFORM_ABLK;
 938         qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
 939         BUG_ON(qmgr_stat_overflow(SEND_QID));
 940         return -EINPROGRESS;
 941
 942 free_buf_src:
 943         free_buf_chain(dev, req_ctx->src, crypt->src_buf);
 944 free_buf_dest:
 945         if (req->src != req->dst) {
 946                 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
 947         }
 948         crypt->ctl_flags = CTL_FLAG_UNUSED;
 949         return -ENOMEM;
 950 }
 951
 952 static int ablk_encrypt(struct ablkcipher_request *req)
 953 {
 954         return ablk_perform(req, 1);
 955 }
 956
 957 static int ablk_decrypt(struct ablkcipher_request *req)
 958 {
 959         return ablk_perform(req, 0);
 960 }
 961
 962 static int ablk_rfc3686_crypt(struct ablkcipher_request *req)
 963 {
 964         struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
 965         struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
 966         u8 iv[CTR_RFC3686_BLOCK_SIZE];
 967         u8 *info = req->info;
 968         int ret;
 969
 970         /* set up counter block */
 971         memcpy(iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
 972         memcpy(iv + CTR_RFC3686_NONCE_SIZE, info, CTR_RFC3686_IV_SIZE);
 973
 974         /* initialize counter portion of counter block */
 975         *(__be32 *)(iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
 976                 cpu_to_be32(1);
 977
 978         req->info = iv;
 979         ret = ablk_perform(req, 1);
 980         req->info = info;
 981         return ret;
 982 }
 983
 984 static int aead_perform(struct aead_request *req, int encrypt,
 985                 int cryptoffset, int eff_cryptlen, u8 *iv)
 986 {
 987         struct crypto_aead *tfm = crypto_aead_reqtfm(req);
 988         struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
 989         unsigned ivsize = crypto_aead_ivsize(tfm);
 990         unsigned authsize = crypto_aead_authsize(tfm);
 991         struct ix_sa_dir *dir;
 992         struct crypt_ctl *crypt;
 993         unsigned int cryptlen;
 994         struct buffer_desc *buf, src_hook;
 995         struct aead_ctx *req_ctx = aead_request_ctx(req);
 996         struct device *dev = &pdev->dev;
 997         gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
 998                                 GFP_KERNEL : GFP_ATOMIC;
 999         enum dma_data_direction src_direction = DMA_BIDIRECTIONAL;
1000         unsigned int lastlen;
1001
1002         if (qmgr_stat_full(SEND_QID))
1003                 return -EAGAIN;
1004         if (atomic_read(&ctx->configuring))
1005                 return -EAGAIN;
1006
1007         if (encrypt) {
1008                 dir = &ctx->encrypt;
1009                 cryptlen = req->cryptlen;
1010         } else {
1011                 dir = &ctx->decrypt;
1012                 /* req->cryptlen includes the authsize when decrypting */
1013                 cryptlen = req->cryptlen -authsize;
1014                 eff_cryptlen -= authsize;
1015         }
1016         crypt = get_crypt_desc();
1017         if (!crypt)
1018                 return -ENOMEM;
1019
1020         crypt->data.aead_req = req;
1021         crypt->crypto_ctx = dir->npe_ctx_phys;
1022         crypt->mode = dir->npe_mode;
1023         crypt->init_len = dir->npe_ctx_idx;
1024
1025         crypt->crypt_offs = cryptoffset;
1026         crypt->crypt_len = eff_cryptlen;
1027
1028         crypt->auth_offs = 0;
1029         crypt->auth_len = req->assoclen + cryptlen;
1030         BUG_ON(ivsize && !req->iv);
1031         memcpy(crypt->iv, req->iv, ivsize);
1032
1033         buf = chainup_buffers(dev, req->src, crypt->auth_len,
1034                               &src_hook, flags, src_direction);
1035         req_ctx->src = src_hook.next;
1036         crypt->src_buf = src_hook.phys_next;
1037         if (!buf)
1038                 goto free_buf_src;
1039
1040         lastlen = buf->buf_len;
1041         if (lastlen >= authsize)
1042                 crypt->icv_rev_aes = buf->phys_addr +
1043                                      buf->buf_len - authsize;
1044
1045         req_ctx->dst = NULL;
1046
1047         if (req->src != req->dst) {
1048                 struct buffer_desc dst_hook;
1049
1050                 crypt->mode |= NPE_OP_NOT_IN_PLACE;
1051                 src_direction = DMA_TO_DEVICE;
1052
1053                 buf = chainup_buffers(dev, req->dst, crypt->auth_len,
1054                                       &dst_hook, flags, DMA_FROM_DEVICE);
1055                 req_ctx->dst = dst_hook.next;
1056                 crypt->dst_buf = dst_hook.phys_next;
1057
1058                 if (!buf)
1059                         goto free_buf_dst;
1060
1061                 if (encrypt) {
1062                         lastlen = buf->buf_len;
1063                         if (lastlen >= authsize)
1064                                 crypt->icv_rev_aes = buf->phys_addr +
1065                                                      buf->buf_len - authsize;
1066                 }
1067         }
1068
1069         if (unlikely(lastlen < authsize)) {
1070                 /* The 12 hmac bytes are scattered,
1071                  * we need to copy them into a safe buffer */
1072                 req_ctx->hmac_virt = dma_pool_alloc(buffer_pool, flags,
1073                                 &crypt->icv_rev_aes);
1074                 if (unlikely(!req_ctx->hmac_virt))
1075                         goto free_buf_dst;
1076                 if (!encrypt) {
1077                         scatterwalk_map_and_copy(req_ctx->hmac_virt,
1078                                 req->src, cryptlen, authsize, 0);
1079                 }
1080                 req_ctx->encrypt = encrypt;
1081         } else {
1082                 req_ctx->hmac_virt = NULL;
1083         }
1084
1085         crypt->ctl_flags |= CTL_FLAG_PERFORM_AEAD;
1086         qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
1087         BUG_ON(qmgr_stat_overflow(SEND_QID));
1088         return -EINPROGRESS;
1089
1090 free_buf_dst:
1091         free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
1092 free_buf_src:
1093         free_buf_chain(dev, req_ctx->src, crypt->src_buf);
1094         crypt->ctl_flags = CTL_FLAG_UNUSED;
1095         return -ENOMEM;
1096 }
1097
1098 static int aead_setup(struct crypto_aead *tfm, unsigned int authsize)
1099 {
1100         struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1101         u32 *flags = &tfm->base.crt_flags;
1102         unsigned digest_len = crypto_aead_maxauthsize(tfm);
1103         int ret;
1104
1105         if (!ctx->enckey_len && !ctx->authkey_len)
1106                 return 0;
1107         init_completion(&ctx->completion);
1108         atomic_inc(&ctx->configuring);
1109
1110         reset_sa_dir(&ctx->encrypt);
1111         reset_sa_dir(&ctx->decrypt);
1112
1113         ret = setup_cipher(&tfm->base, 0, ctx->enckey, ctx->enckey_len);
1114         if (ret)
1115                 goto out;
1116         ret = setup_cipher(&tfm->base, 1, ctx->enckey, ctx->enckey_len);
1117         if (ret)
1118                 goto out;
1119         ret = setup_auth(&tfm->base, 0, authsize, ctx->authkey,
1120                         ctx->authkey_len, digest_len);
1121         if (ret)
1122                 goto out;
1123         ret = setup_auth(&tfm->base, 1, authsize,  ctx->authkey,
1124                         ctx->authkey_len, digest_len);
1125         if (ret)
1126                 goto out;
1127
1128         if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
1129                 if (*flags & CRYPTO_TFM_REQ_WEAK_KEY) {
1130                         ret = -EINVAL;
1131                         goto out;
1132                 } else {
1133                         *flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
1134                 }
1135         }
1136 out:
1137         if (!atomic_dec_and_test(&ctx->configuring))
1138                 wait_for_completion(&ctx->completion);
1139         return ret;
1140 }
1141
1142 static int aead_setauthsize(struct crypto_aead *tfm, unsigned int authsize)
1143 {
1144         int max = crypto_aead_maxauthsize(tfm) >> 2;
1145
1146         if ((authsize>>2) < 1 || (authsize>>2) > max || (authsize & 3))
1147                 return -EINVAL;
1148         return aead_setup(tfm, authsize);
1149 }
1150
1151 static int aead_setkey(struct crypto_aead *tfm, const u8 *key,
1152                         unsigned int keylen)
1153 {
1154         struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1155         struct crypto_authenc_keys keys;
1156
1157         if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
1158                 goto badkey;
1159
1160         if (keys.authkeylen > sizeof(ctx->authkey))
1161                 goto badkey;
1162
1163         if (keys.enckeylen > sizeof(ctx->enckey))
1164                 goto badkey;
1165
1166         memcpy(ctx->authkey, keys.authkey, keys.authkeylen);
1167         memcpy(ctx->enckey, keys.enckey, keys.enckeylen);
1168         ctx->authkey_len = keys.authkeylen;
1169         ctx->enckey_len = keys.enckeylen;
1170
1171         return aead_setup(tfm, crypto_aead_authsize(tfm));
1172 badkey:
1173         crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1174         return -EINVAL;
1175 }
1176
1177 static int aead_encrypt(struct aead_request *req)
1178 {
1179         return aead_perform(req, 1, req->assoclen, req->cryptlen, req->iv);
1180 }
1181
1182 static int aead_decrypt(struct aead_request *req)
1183 {
1184         return aead_perform(req, 0, req->assoclen, req->cryptlen, req->iv);
1185 }
1186
1187 static struct ixp_alg ixp4xx_algos[] = {
1188 {
1189         .crypto = {
1190                 .cra_name       = "cbc(des)",
1191                 .cra_blocksize  = DES_BLOCK_SIZE,
1192                 .cra_u          = { .ablkcipher = {
1193                         .min_keysize    = DES_KEY_SIZE,
1194                         .max_keysize    = DES_KEY_SIZE,
1195                         .ivsize         = DES_BLOCK_SIZE,
1196                         .geniv          = "eseqiv",
1197                         }
1198                 }
1199         },
1200         .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1201         .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1202
1203 }, {
1204         .crypto = {
1205                 .cra_name       = "ecb(des)",
1206                 .cra_blocksize  = DES_BLOCK_SIZE,
1207                 .cra_u          = { .ablkcipher = {
1208                         .min_keysize    = DES_KEY_SIZE,
1209                         .max_keysize    = DES_KEY_SIZE,
1210                         }
1211                 }
1212         },
1213         .cfg_enc = CIPH_ENCR | MOD_DES | MOD_ECB | KEYLEN_192,
1214         .cfg_dec = CIPH_DECR | MOD_DES | MOD_ECB | KEYLEN_192,
1215 }, {
1216         .crypto = {
1217                 .cra_name       = "cbc(des3_ede)",
1218                 .cra_blocksize  = DES3_EDE_BLOCK_SIZE,
1219                 .cra_u          = { .ablkcipher = {
1220                         .min_keysize    = DES3_EDE_KEY_SIZE,
1221                         .max_keysize    = DES3_EDE_KEY_SIZE,
1222                         .ivsize         = DES3_EDE_BLOCK_SIZE,
1223                         .geniv          = "eseqiv",
1224                         }
1225                 }
1226         },
1227         .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1228         .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1229 }, {
1230         .crypto = {
1231                 .cra_name       = "ecb(des3_ede)",
1232                 .cra_blocksize  = DES3_EDE_BLOCK_SIZE,
1233                 .cra_u          = { .ablkcipher = {
1234                         .min_keysize    = DES3_EDE_KEY_SIZE,
1235                         .max_keysize    = DES3_EDE_KEY_SIZE,
1236                         }
1237                 }
1238         },
1239         .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_ECB | KEYLEN_192,
1240         .cfg_dec = CIPH_DECR | MOD_3DES | MOD_ECB | KEYLEN_192,
1241 }, {
1242         .crypto = {
1243                 .cra_name       = "cbc(aes)",
1244                 .cra_blocksize  = AES_BLOCK_SIZE,
1245                 .cra_u          = { .ablkcipher = {
1246                         .min_keysize    = AES_MIN_KEY_SIZE,
1247                         .max_keysize    = AES_MAX_KEY_SIZE,
1248                         .ivsize         = AES_BLOCK_SIZE,
1249                         .geniv          = "eseqiv",
1250                         }
1251                 }
1252         },
1253         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1254         .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1255 }, {
1256         .crypto = {
1257                 .cra_name       = "ecb(aes)",
1258                 .cra_blocksize  = AES_BLOCK_SIZE,
1259                 .cra_u          = { .ablkcipher = {
1260                         .min_keysize    = AES_MIN_KEY_SIZE,
1261                         .max_keysize    = AES_MAX_KEY_SIZE,
1262                         }
1263                 }
1264         },
1265         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_ECB,
1266         .cfg_dec = CIPH_DECR | MOD_AES | MOD_ECB,
1267 }, {
1268         .crypto = {
1269                 .cra_name       = "ctr(aes)",
1270                 .cra_blocksize  = AES_BLOCK_SIZE,
1271                 .cra_u          = { .ablkcipher = {
1272                         .min_keysize    = AES_MIN_KEY_SIZE,
1273                         .max_keysize    = AES_MAX_KEY_SIZE,
1274                         .ivsize         = AES_BLOCK_SIZE,
1275                         .geniv          = "eseqiv",
1276                         }
1277                 }
1278         },
1279         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1280         .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1281 }, {
1282         .crypto = {
1283                 .cra_name       = "rfc3686(ctr(aes))",
1284                 .cra_blocksize  = AES_BLOCK_SIZE,
1285                 .cra_u          = { .ablkcipher = {
1286                         .min_keysize    = AES_MIN_KEY_SIZE,
1287                         .max_keysize    = AES_MAX_KEY_SIZE,
1288                         .ivsize         = AES_BLOCK_SIZE,
1289                         .geniv          = "eseqiv",
1290                         .setkey         = ablk_rfc3686_setkey,
1291                         .encrypt        = ablk_rfc3686_crypt,
1292                         .decrypt        = ablk_rfc3686_crypt }
1293                 }
1294         },
1295         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1296         .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1297 } };
1298
1299 static struct ixp_aead_alg ixp4xx_aeads[] = {
1300 {
1301         .crypto = {
1302                 .base = {
1303                         .cra_name       = "authenc(hmac(md5),cbc(des))",
1304                         .cra_blocksize  = DES_BLOCK_SIZE,
1305                 },
1306                 .ivsize         = DES_BLOCK_SIZE,
1307                 .maxauthsize    = MD5_DIGEST_SIZE,
1308         },
1309         .hash = &hash_alg_md5,
1310         .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1311         .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1312 }, {
1313         .crypto = {
1314                 .base = {
1315                         .cra_name       = "authenc(hmac(md5),cbc(des3_ede))",
1316                         .cra_blocksize  = DES3_EDE_BLOCK_SIZE,
1317                 },
1318                 .ivsize         = DES3_EDE_BLOCK_SIZE,
1319                 .maxauthsize    = MD5_DIGEST_SIZE,
1320         },
1321         .hash = &hash_alg_md5,
1322         .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1323         .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1324 }, {
1325         .crypto = {
1326                 .base = {
1327                         .cra_name       = "authenc(hmac(sha1),cbc(des))",
1328                         .cra_blocksize  = DES_BLOCK_SIZE,
1329                 },
1330                         .ivsize         = DES_BLOCK_SIZE,
1331                         .maxauthsize    = SHA1_DIGEST_SIZE,
1332         },
1333         .hash = &hash_alg_sha1,
1334         .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1335         .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1336 }, {
1337         .crypto = {
1338                 .base = {
1339                         .cra_name       = "authenc(hmac(sha1),cbc(des3_ede))",
1340                         .cra_blocksize  = DES3_EDE_BLOCK_SIZE,
1341                 },
1342                 .ivsize         = DES3_EDE_BLOCK_SIZE,
1343                 .maxauthsize    = SHA1_DIGEST_SIZE,
1344         },
1345         .hash = &hash_alg_sha1,
1346         .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1347         .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1348 }, {
1349         .crypto = {
1350                 .base = {
1351                         .cra_name       = "authenc(hmac(md5),cbc(aes))",
1352                         .cra_blocksize  = AES_BLOCK_SIZE,
1353                 },
1354                 .ivsize         = AES_BLOCK_SIZE,
1355                 .maxauthsize    = MD5_DIGEST_SIZE,
1356         },
1357         .hash = &hash_alg_md5,
1358         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1359         .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1360 }, {
1361         .crypto = {
1362                 .base = {
1363                         .cra_name       = "authenc(hmac(sha1),cbc(aes))",
1364                         .cra_blocksize  = AES_BLOCK_SIZE,
1365                 },
1366                 .ivsize         = AES_BLOCK_SIZE,
1367                 .maxauthsize    = SHA1_DIGEST_SIZE,
1368         },
1369         .hash = &hash_alg_sha1,
1370         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1371         .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1372 } };
1373
1374 #define IXP_POSTFIX "-ixp4xx"
1375
1376 static const struct platform_device_info ixp_dev_info __initdata = {
1377         .name           = DRIVER_NAME,
1378         .id             = 0,
1379         .dma_mask       = DMA_BIT_MASK(32),
1380 };
1381
1382 static int __init ixp_module_init(void)
1383 {
1384         int num = ARRAY_SIZE(ixp4xx_algos);
1385         int i, err;
1386
1387         pdev = platform_device_register_full(&ixp_dev_info);
1388         if (IS_ERR(pdev))
1389                 return PTR_ERR(pdev);
1390
1391         spin_lock_init(&desc_lock);
1392         spin_lock_init(&emerg_lock);
1393
1394         err = init_ixp_crypto(&pdev->dev);
1395         if (err) {
1396                 platform_device_unregister(pdev);
1397                 return err;
1398         }
1399         for (i=0; i< num; i++) {
1400                 struct crypto_alg *cra = &ixp4xx_algos[i].crypto;
1401
1402                 if (snprintf(cra->cra_driver_name, CRYPTO_MAX_ALG_NAME,
1403                         "%s"IXP_POSTFIX, cra->cra_name) >=
1404                         CRYPTO_MAX_ALG_NAME)
1405                 {
1406                         continue;
1407                 }
1408                 if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES)) {
1409                         continue;
1410                 }
1411
1412                 /* block ciphers */
1413                 cra->cra_type = &crypto_ablkcipher_type;
1414                 cra->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1415                                  CRYPTO_ALG_KERN_DRIVER_ONLY |
1416                                  CRYPTO_ALG_ASYNC;
1417                 if (!cra->cra_ablkcipher.setkey)
1418                         cra->cra_ablkcipher.setkey = ablk_setkey;
1419                 if (!cra->cra_ablkcipher.encrypt)
1420                         cra->cra_ablkcipher.encrypt = ablk_encrypt;
1421                 if (!cra->cra_ablkcipher.decrypt)
1422                         cra->cra_ablkcipher.decrypt = ablk_decrypt;
1423                 cra->cra_init = init_tfm_ablk;
1424
1425                 cra->cra_ctxsize = sizeof(struct ixp_ctx);
1426                 cra->cra_module = THIS_MODULE;
1427                 cra->cra_alignmask = 3;
1428                 cra->cra_priority = 300;
1429                 cra->cra_exit = exit_tfm;
1430                 if (crypto_register_alg(cra))
1431                         printk(KERN_ERR "Failed to register '%s'\n",
1432                                 cra->cra_name);
1433                 else
1434                         ixp4xx_algos[i].registered = 1;
1435         }
1436
1437         for (i = 0; i < ARRAY_SIZE(ixp4xx_aeads); i++) {
1438                 struct aead_alg *cra = &ixp4xx_aeads[i].crypto;
1439
1440                 if (snprintf(cra->base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
1441                              "%s"IXP_POSTFIX, cra->base.cra_name) >=
1442                     CRYPTO_MAX_ALG_NAME)
1443                         continue;
1444                 if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES))
1445                         continue;
1446
1447                 /* authenc */
1448                 cra->base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1449                                       CRYPTO_ALG_ASYNC;
1450                 cra->setkey = aead_setkey;
1451                 cra->setauthsize = aead_setauthsize;
1452                 cra->encrypt = aead_encrypt;
1453                 cra->decrypt = aead_decrypt;
1454                 cra->init = init_tfm_aead;
1455                 cra->exit = exit_tfm_aead;
1456
1457                 cra->base.cra_ctxsize = sizeof(struct ixp_ctx);
1458                 cra->base.cra_module = THIS_MODULE;
1459                 cra->base.cra_alignmask = 3;
1460                 cra->base.cra_priority = 300;
1461
1462                 if (crypto_register_aead(cra))
1463                         printk(KERN_ERR "Failed to register '%s'\n",
1464                                 cra->base.cra_driver_name);
1465                 else
1466                         ixp4xx_aeads[i].registered = 1;
1467         }
1468         return 0;
1469 }
1470
1471 static void __exit ixp_module_exit(void)
1472 {
1473         int num = ARRAY_SIZE(ixp4xx_algos);
1474         int i;
1475
1476         for (i = 0; i < ARRAY_SIZE(ixp4xx_aeads); i++) {
1477                 if (ixp4xx_aeads[i].registered)
1478                         crypto_unregister_aead(&ixp4xx_aeads[i].crypto);
1479         }
1480
1481         for (i=0; i< num; i++) {
1482                 if (ixp4xx_algos[i].registered)
1483                         crypto_unregister_alg(&ixp4xx_algos[i].crypto);
1484         }
1485         release_ixp_crypto(&pdev->dev);
1486         platform_device_unregister(pdev);
1487 }
1488
1489 module_init(ixp_module_init);
1490 module_exit(ixp_module_exit);
1491
1492 MODULE_LICENSE("GPL");
1493 MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>");
1494 MODULE_DESCRIPTION("IXP4xx hardware crypto");
1495