2 * Copyright (C) 2017 Marvell
4 * Antoine Tenart <antoine.tenart@free-electrons.com>
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmapool.h>
15 #include <linux/firmware.h>
16 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/of_platform.h>
19 #include <linux/of_irq.h>
20 #include <linux/platform_device.h>
21 #include <linux/workqueue.h>
23 #include <crypto/internal/hash.h>
24 #include <crypto/internal/skcipher.h>
28 static u32 max_rings = EIP197_MAX_RINGS;
29 module_param(max_rings, uint, 0644);
30 MODULE_PARM_DESC(max_rings, "Maximum number of rings to use.");
32 static void eip197_trc_cache_init(struct safexcel_crypto_priv *priv)
34 u32 val, htable_offset;
37 /* Enable the record cache memory access */
38 val = readl(priv->base + EIP197_CS_RAM_CTRL);
39 val &= ~EIP197_TRC_ENABLE_MASK;
40 val |= EIP197_TRC_ENABLE_0;
41 writel(val, priv->base + EIP197_CS_RAM_CTRL);
43 /* Clear all ECC errors */
44 writel(0, priv->base + EIP197_TRC_ECCCTRL);
47 * Make sure the cache memory is accessible by taking record cache into
50 val = readl(priv->base + EIP197_TRC_PARAMS);
51 val |= EIP197_TRC_PARAMS_SW_RESET;
52 val &= ~EIP197_TRC_PARAMS_DATA_ACCESS;
53 writel(val, priv->base + EIP197_TRC_PARAMS);
55 /* Clear all records */
56 for (i = 0; i < EIP197_CS_RC_MAX; i++) {
57 u32 val, offset = EIP197_CLASSIFICATION_RAMS + i * EIP197_CS_RC_SIZE;
59 writel(EIP197_CS_RC_NEXT(EIP197_RC_NULL) |
60 EIP197_CS_RC_PREV(EIP197_RC_NULL),
63 val = EIP197_CS_RC_NEXT(i+1) | EIP197_CS_RC_PREV(i-1);
65 val |= EIP197_CS_RC_PREV(EIP197_RC_NULL);
66 else if (i == EIP197_CS_RC_MAX - 1)
67 val |= EIP197_CS_RC_NEXT(EIP197_RC_NULL);
68 writel(val, priv->base + offset + sizeof(u32));
71 /* Clear the hash table entries */
72 htable_offset = EIP197_CS_RC_MAX * EIP197_CS_RC_SIZE;
73 for (i = 0; i < 64; i++)
74 writel(GENMASK(29, 0),
75 priv->base + EIP197_CLASSIFICATION_RAMS + htable_offset + i * sizeof(u32));
77 /* Disable the record cache memory access */
78 val = readl(priv->base + EIP197_CS_RAM_CTRL);
79 val &= ~EIP197_TRC_ENABLE_MASK;
80 writel(val, priv->base + EIP197_CS_RAM_CTRL);
82 /* Write head and tail pointers of the record free chain */
83 val = EIP197_TRC_FREECHAIN_HEAD_PTR(0) |
84 EIP197_TRC_FREECHAIN_TAIL_PTR(EIP197_CS_RC_MAX - 1);
85 writel(val, priv->base + EIP197_TRC_FREECHAIN);
87 /* Configure the record cache #1 */
88 val = EIP197_TRC_PARAMS2_RC_SZ_SMALL(EIP197_CS_TRC_REC_WC) |
89 EIP197_TRC_PARAMS2_HTABLE_PTR(EIP197_CS_RC_MAX);
90 writel(val, priv->base + EIP197_TRC_PARAMS2);
92 /* Configure the record cache #2 */
93 val = EIP197_TRC_PARAMS_RC_SZ_LARGE(EIP197_CS_TRC_LG_REC_WC) |
94 EIP197_TRC_PARAMS_BLK_TIMER_SPEED(1) |
95 EIP197_TRC_PARAMS_HTABLE_SZ(2);
96 writel(val, priv->base + EIP197_TRC_PARAMS);
99 static void eip197_write_firmware(struct safexcel_crypto_priv *priv,
100 const struct firmware *fw, u32 ctrl,
103 const u32 *data = (const u32 *)fw->data;
107 /* Reset the engine to make its program memory accessible */
108 writel(EIP197_PE_ICE_x_CTRL_SW_RESET |
109 EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR |
110 EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR,
113 /* Enable access to the program memory */
114 writel(prog_en, priv->base + EIP197_PE_ICE_RAM_CTRL);
116 /* Write the firmware */
117 for (i = 0; i < fw->size / sizeof(u32); i++)
118 writel(be32_to_cpu(data[i]),
119 priv->base + EIP197_CLASSIFICATION_RAMS + i * sizeof(u32));
121 /* Disable access to the program memory */
122 writel(0, priv->base + EIP197_PE_ICE_RAM_CTRL);
124 /* Release engine from reset */
125 val = readl(priv->base + ctrl);
126 val &= ~EIP197_PE_ICE_x_CTRL_SW_RESET;
127 writel(val, priv->base + ctrl);
130 static int eip197_load_firmwares(struct safexcel_crypto_priv *priv)
132 const char *fw_name[] = {"ifpp.bin", "ipue.bin"};
133 const struct firmware *fw[FW_NB];
137 for (i = 0; i < FW_NB; i++) {
138 ret = request_firmware(&fw[i], fw_name[i], priv->dev);
141 "Failed to request firmware %s (%d)\n",
147 /* Clear the scratchpad memory */
148 val = readl(priv->base + EIP197_PE_ICE_SCRATCH_CTRL);
149 val |= EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER |
150 EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN |
151 EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS |
152 EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS;
153 writel(val, priv->base + EIP197_PE_ICE_SCRATCH_CTRL);
155 memset(priv->base + EIP197_PE_ICE_SCRATCH_RAM, 0,
156 EIP197_NUM_OF_SCRATCH_BLOCKS * sizeof(u32));
158 eip197_write_firmware(priv, fw[FW_IFPP], EIP197_PE_ICE_FPP_CTRL,
159 EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN);
161 eip197_write_firmware(priv, fw[FW_IPUE], EIP197_PE_ICE_PUE_CTRL,
162 EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN);
165 for (j = 0; j < i; j++)
166 release_firmware(fw[j]);
171 static int safexcel_hw_setup_cdesc_rings(struct safexcel_crypto_priv *priv)
173 u32 hdw, cd_size_rnd, val;
176 hdw = readl(priv->base + EIP197_HIA_OPTIONS);
177 hdw &= GENMASK(27, 25);
180 cd_size_rnd = (priv->config.cd_size + (BIT(hdw) - 1)) >> hdw;
182 for (i = 0; i < priv->config.rings; i++) {
183 /* ring base address */
184 writel(lower_32_bits(priv->ring[i].cdr.base_dma),
185 priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_RING_BASE_ADDR_LO);
186 writel(upper_32_bits(priv->ring[i].cdr.base_dma),
187 priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_RING_BASE_ADDR_HI);
189 writel(EIP197_xDR_DESC_MODE_64BIT | (priv->config.cd_offset << 16) |
190 priv->config.cd_size,
191 priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_DESC_SIZE);
192 writel(((EIP197_FETCH_COUNT * (cd_size_rnd << hdw)) << 16) |
193 (EIP197_FETCH_COUNT * priv->config.cd_offset),
194 priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_CFG);
196 /* Configure DMA tx control */
197 val = EIP197_HIA_xDR_CFG_WR_CACHE(WR_CACHE_3BITS);
198 val |= EIP197_HIA_xDR_CFG_RD_CACHE(RD_CACHE_3BITS);
200 priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_DMA_CFG);
202 /* clear any pending interrupt */
203 writel(GENMASK(5, 0),
204 priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_STAT);
210 static int safexcel_hw_setup_rdesc_rings(struct safexcel_crypto_priv *priv)
212 u32 hdw, rd_size_rnd, val;
215 hdw = readl(priv->base + EIP197_HIA_OPTIONS);
216 hdw &= GENMASK(27, 25);
219 rd_size_rnd = (priv->config.rd_size + (BIT(hdw) - 1)) >> hdw;
221 for (i = 0; i < priv->config.rings; i++) {
222 /* ring base address */
223 writel(lower_32_bits(priv->ring[i].rdr.base_dma),
224 priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_RING_BASE_ADDR_LO);
225 writel(upper_32_bits(priv->ring[i].rdr.base_dma),
226 priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_RING_BASE_ADDR_HI);
228 writel(EIP197_xDR_DESC_MODE_64BIT | (priv->config.rd_offset << 16) |
229 priv->config.rd_size,
230 priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_DESC_SIZE);
232 writel(((EIP197_FETCH_COUNT * (rd_size_rnd << hdw)) << 16) |
233 (EIP197_FETCH_COUNT * priv->config.rd_offset),
234 priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_CFG);
236 /* Configure DMA tx control */
237 val = EIP197_HIA_xDR_CFG_WR_CACHE(WR_CACHE_3BITS);
238 val |= EIP197_HIA_xDR_CFG_RD_CACHE(RD_CACHE_3BITS);
239 val |= EIP197_HIA_xDR_WR_RES_BUF | EIP197_HIA_xDR_WR_CTRL_BUG;
241 priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_DMA_CFG);
243 /* clear any pending interrupt */
244 writel(GENMASK(7, 0),
245 priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_STAT);
247 /* enable ring interrupt */
248 val = readl(priv->base + EIP197_HIA_AIC_R_ENABLE_CTRL(i));
249 val |= EIP197_RDR_IRQ(i);
250 writel(val, priv->base + EIP197_HIA_AIC_R_ENABLE_CTRL(i));
256 static int safexcel_hw_init(struct safexcel_crypto_priv *priv)
261 /* Determine endianess and configure byte swap */
262 version = readl(priv->base + EIP197_HIA_VERSION);
263 val = readl(priv->base + EIP197_HIA_MST_CTRL);
265 if ((version & 0xffff) == EIP197_HIA_VERSION_BE)
266 val |= EIP197_MST_CTRL_BYTE_SWAP;
267 else if (((version >> 16) & 0xffff) == EIP197_HIA_VERSION_LE)
268 val |= (EIP197_MST_CTRL_NO_BYTE_SWAP >> 24);
270 writel(val, priv->base + EIP197_HIA_MST_CTRL);
273 /* Configure wr/rd cache values */
274 writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) |
275 EIP197_MST_CTRL_WD_CACHE(WR_CACHE_4BITS),
276 priv->base + EIP197_MST_CTRL);
278 /* Interrupts reset */
280 /* Disable all global interrupts */
281 writel(0, priv->base + EIP197_HIA_AIC_G_ENABLE_CTRL);
283 /* Clear any pending interrupt */
284 writel(GENMASK(31, 0), priv->base + EIP197_HIA_AIC_G_ACK);
286 /* Data Fetch Engine configuration */
288 /* Reset all DFE threads */
289 writel(EIP197_DxE_THR_CTRL_RESET_PE,
290 priv->base + EIP197_HIA_DFE_THR_CTRL);
292 /* Reset HIA input interface arbiter */
293 writel(EIP197_HIA_RA_PE_CTRL_RESET,
294 priv->base + EIP197_HIA_RA_PE_CTRL);
296 /* DMA transfer size to use */
297 val = EIP197_HIA_DFE_CFG_DIS_DEBUG;
298 val |= EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(5) | EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(9);
299 val |= EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(5) | EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(7);
300 val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(RD_CACHE_3BITS);
301 val |= EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(RD_CACHE_3BITS);
302 writel(val, priv->base + EIP197_HIA_DFE_CFG);
304 /* Leave the DFE threads reset state */
305 writel(0, priv->base + EIP197_HIA_DFE_THR_CTRL);
307 /* Configure the procesing engine thresholds */
308 writel(EIP197_PE_IN_xBUF_THRES_MIN(5) | EIP197_PE_IN_xBUF_THRES_MAX(9),
309 priv->base + EIP197_PE_IN_DBUF_THRES);
310 writel(EIP197_PE_IN_xBUF_THRES_MIN(5) | EIP197_PE_IN_xBUF_THRES_MAX(7),
311 priv->base + EIP197_PE_IN_TBUF_THRES);
313 /* enable HIA input interface arbiter and rings */
314 writel(EIP197_HIA_RA_PE_CTRL_EN | GENMASK(priv->config.rings - 1, 0),
315 priv->base + EIP197_HIA_RA_PE_CTRL);
317 /* Data Store Engine configuration */
319 /* Reset all DSE threads */
320 writel(EIP197_DxE_THR_CTRL_RESET_PE,
321 priv->base + EIP197_HIA_DSE_THR_CTRL);
323 /* Wait for all DSE threads to complete */
324 while ((readl(priv->base + EIP197_HIA_DSE_THR_STAT) &
325 GENMASK(15, 12)) != GENMASK(15, 12))
328 /* DMA transfer size to use */
329 val = EIP197_HIA_DSE_CFG_DIS_DEBUG;
330 val |= EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(7) | EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(8);
331 val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(WR_CACHE_3BITS);
332 val |= EIP197_HIA_DSE_CFG_ALLWAYS_BUFFERABLE;
333 val |= EIP197_HIA_DSE_CFG_EN_SINGLE_WR;
334 writel(val, priv->base + EIP197_HIA_DSE_CFG);
336 /* Leave the DSE threads reset state */
337 writel(0, priv->base + EIP197_HIA_DSE_THR_CTRL);
339 /* Configure the procesing engine thresholds */
340 writel(EIP197_PE_OUT_DBUF_THRES_MIN(7) | EIP197_PE_OUT_DBUF_THRES_MAX(8),
341 priv->base + EIP197_PE_OUT_DBUF_THRES);
343 /* Processing Engine configuration */
345 /* H/W capabilities selection */
346 val = EIP197_FUNCTION_RSVD;
347 val |= EIP197_PROTOCOL_ENCRYPT_ONLY | EIP197_PROTOCOL_HASH_ONLY;
348 val |= EIP197_ALG_AES_ECB | EIP197_ALG_AES_CBC;
349 val |= EIP197_ALG_SHA1 | EIP197_ALG_HMAC_SHA1;
350 val |= EIP197_ALG_SHA2;
351 writel(val, priv->base + EIP197_PE_EIP96_FUNCTION_EN);
353 /* Command Descriptor Rings prepare */
354 for (i = 0; i < priv->config.rings; i++) {
355 /* Clear interrupts for this ring */
356 writel(GENMASK(31, 0),
357 priv->base + EIP197_HIA_AIC_R_ENABLE_CLR(i));
359 /* Disable external triggering */
360 writel(0, priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_CFG);
362 /* Clear the pending prepared counter */
363 writel(EIP197_xDR_PREP_CLR_COUNT,
364 priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_PREP_COUNT);
366 /* Clear the pending processed counter */
367 writel(EIP197_xDR_PROC_CLR_COUNT,
368 priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_PROC_COUNT);
371 priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_PREP_PNTR);
373 priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_PROC_PNTR);
375 writel((EIP197_DEFAULT_RING_SIZE * priv->config.cd_offset) << 2,
376 priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_RING_SIZE);
379 /* Result Descriptor Ring prepare */
380 for (i = 0; i < priv->config.rings; i++) {
381 /* Disable external triggering*/
382 writel(0, priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_CFG);
384 /* Clear the pending prepared counter */
385 writel(EIP197_xDR_PREP_CLR_COUNT,
386 priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_PREP_COUNT);
388 /* Clear the pending processed counter */
389 writel(EIP197_xDR_PROC_CLR_COUNT,
390 priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_PROC_COUNT);
393 priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_PREP_PNTR);
395 priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_PROC_PNTR);
398 writel((EIP197_DEFAULT_RING_SIZE * priv->config.rd_offset) << 2,
399 priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_RING_SIZE);
402 /* Enable command descriptor rings */
403 writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0),
404 priv->base + EIP197_HIA_DFE_THR_CTRL);
406 /* Enable result descriptor rings */
407 writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0),
408 priv->base + EIP197_HIA_DSE_THR_CTRL);
410 /* Clear any HIA interrupt */
411 writel(GENMASK(30, 20), priv->base + EIP197_HIA_AIC_G_ACK);
413 eip197_trc_cache_init(priv);
415 ret = eip197_load_firmwares(priv);
419 safexcel_hw_setup_cdesc_rings(priv);
420 safexcel_hw_setup_rdesc_rings(priv);
425 void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring)
427 struct crypto_async_request *req, *backlog;
428 struct safexcel_context *ctx;
429 struct safexcel_request *request;
430 int ret, nreq = 0, cdesc = 0, rdesc = 0, commands, results;
432 priv->ring[ring].need_dequeue = false;
435 spin_lock_bh(&priv->ring[ring].queue_lock);
436 backlog = crypto_get_backlog(&priv->ring[ring].queue);
437 req = crypto_dequeue_request(&priv->ring[ring].queue);
438 spin_unlock_bh(&priv->ring[ring].queue_lock);
443 request = kzalloc(sizeof(*request), EIP197_GFP_FLAGS(*req));
445 spin_lock_bh(&priv->ring[ring].queue_lock);
446 crypto_enqueue_request(&priv->ring[ring].queue, req);
447 spin_unlock_bh(&priv->ring[ring].queue_lock);
449 priv->ring[ring].need_dequeue = true;
453 ctx = crypto_tfm_ctx(req->tfm);
454 ret = ctx->send(req, ring, request, &commands, &results);
457 req->complete(req, ret);
458 priv->ring[ring].need_dequeue = true;
463 backlog->complete(backlog, -EINPROGRESS);
465 spin_lock_bh(&priv->ring[ring].egress_lock);
466 list_add_tail(&request->list, &priv->ring[ring].list);
467 spin_unlock_bh(&priv->ring[ring].egress_lock);
471 } while (nreq++ < EIP197_MAX_BATCH_SZ);
474 if (nreq == EIP197_MAX_BATCH_SZ)
475 priv->ring[ring].need_dequeue = true;
479 spin_lock_bh(&priv->ring[ring].lock);
481 /* Configure when we want an interrupt */
482 writel(EIP197_HIA_RDR_THRESH_PKT_MODE |
483 EIP197_HIA_RDR_THRESH_PROC_PKT(nreq),
484 priv->base + EIP197_HIA_RDR(ring) + EIP197_HIA_xDR_THRESH);
486 /* let the RDR know we have pending descriptors */
487 writel((rdesc * priv->config.rd_offset) << 2,
488 priv->base + EIP197_HIA_RDR(ring) + EIP197_HIA_xDR_PREP_COUNT);
490 /* let the CDR know we have pending descriptors */
491 writel((cdesc * priv->config.cd_offset) << 2,
492 priv->base + EIP197_HIA_CDR(ring) + EIP197_HIA_xDR_PREP_COUNT);
494 spin_unlock_bh(&priv->ring[ring].lock);
497 void safexcel_free_context(struct safexcel_crypto_priv *priv,
498 struct crypto_async_request *req,
501 struct safexcel_context *ctx = crypto_tfm_ctx(req->tfm);
504 dma_unmap_single(priv->dev, ctx->result_dma, result_sz,
508 dma_unmap_single(priv->dev, ctx->cache_dma, ctx->cache_sz,
516 void safexcel_complete(struct safexcel_crypto_priv *priv, int ring)
518 struct safexcel_command_desc *cdesc;
520 /* Acknowledge the command descriptors */
522 cdesc = safexcel_ring_next_rptr(priv, &priv->ring[ring].cdr);
525 "Could not retrieve the command descriptor\n");
528 } while (!cdesc->last_seg);
531 void safexcel_inv_complete(struct crypto_async_request *req, int error)
533 struct safexcel_inv_result *result = req->data;
535 if (error == -EINPROGRESS)
538 result->error = error;
539 complete(&result->completion);
542 int safexcel_invalidate_cache(struct crypto_async_request *async,
543 struct safexcel_context *ctx,
544 struct safexcel_crypto_priv *priv,
545 dma_addr_t ctxr_dma, int ring,
546 struct safexcel_request *request)
548 struct safexcel_command_desc *cdesc;
549 struct safexcel_result_desc *rdesc;
552 spin_lock_bh(&priv->ring[ring].egress_lock);
554 /* Prepare command descriptor */
555 cdesc = safexcel_add_cdesc(priv, ring, true, true, 0, 0, 0, ctxr_dma);
557 ret = PTR_ERR(cdesc);
561 cdesc->control_data.type = EIP197_TYPE_EXTENDED;
562 cdesc->control_data.options = 0;
563 cdesc->control_data.refresh = 0;
564 cdesc->control_data.control0 = CONTEXT_CONTROL_INV_TR;
566 /* Prepare result descriptor */
567 rdesc = safexcel_add_rdesc(priv, ring, true, true, 0, 0);
570 ret = PTR_ERR(rdesc);
574 request->req = async;
578 safexcel_ring_rollback_wptr(priv, &priv->ring[ring].cdr);
581 spin_unlock_bh(&priv->ring[ring].egress_lock);
585 static inline void safexcel_handle_result_descriptor(struct safexcel_crypto_priv *priv,
588 struct safexcel_request *sreq;
589 struct safexcel_context *ctx;
590 int ret, i, nreq, ndesc = 0;
591 bool should_complete;
593 nreq = readl(priv->base + EIP197_HIA_RDR(ring) + EIP197_HIA_xDR_PROC_COUNT);
595 nreq &= GENMASK(6, 0);
599 for (i = 0; i < nreq; i++) {
600 spin_lock_bh(&priv->ring[ring].egress_lock);
601 sreq = list_first_entry(&priv->ring[ring].list,
602 struct safexcel_request, list);
603 list_del(&sreq->list);
604 spin_unlock_bh(&priv->ring[ring].egress_lock);
606 ctx = crypto_tfm_ctx(sreq->req->tfm);
607 ndesc = ctx->handle_result(priv, ring, sreq->req,
608 &should_complete, &ret);
611 dev_err(priv->dev, "failed to handle result (%d)", ndesc);
615 writel(EIP197_xDR_PROC_xD_PKT(1) |
616 EIP197_xDR_PROC_xD_COUNT(ndesc * priv->config.rd_offset),
617 priv->base + EIP197_HIA_RDR(ring) + EIP197_HIA_xDR_PROC_COUNT);
619 if (should_complete) {
621 sreq->req->complete(sreq->req, ret);
629 static void safexcel_handle_result_work(struct work_struct *work)
631 struct safexcel_work_data *data =
632 container_of(work, struct safexcel_work_data, work);
633 struct safexcel_crypto_priv *priv = data->priv;
635 safexcel_handle_result_descriptor(priv, data->ring);
637 if (priv->ring[data->ring].need_dequeue)
638 safexcel_dequeue(data->priv, data->ring);
641 struct safexcel_ring_irq_data {
642 struct safexcel_crypto_priv *priv;
646 static irqreturn_t safexcel_irq_ring(int irq, void *data)
648 struct safexcel_ring_irq_data *irq_data = data;
649 struct safexcel_crypto_priv *priv = irq_data->priv;
650 int ring = irq_data->ring;
653 status = readl(priv->base + EIP197_HIA_AIC_R_ENABLED_STAT(ring));
658 if (status & EIP197_RDR_IRQ(ring)) {
659 stat = readl(priv->base + EIP197_HIA_RDR(ring) + EIP197_HIA_xDR_STAT);
661 if (unlikely(stat & EIP197_xDR_ERR)) {
663 * Fatal error, the RDR is unusable and must be
664 * reinitialized. This should not happen under
665 * normal circumstances.
667 dev_err(priv->dev, "RDR: fatal error.");
668 } else if (likely(stat & EIP197_xDR_THRESH)) {
669 queue_work(priv->ring[ring].workqueue, &priv->ring[ring].work_data.work);
672 /* ACK the interrupts */
674 priv->base + EIP197_HIA_RDR(ring) + EIP197_HIA_xDR_STAT);
677 /* ACK the interrupts */
678 writel(status, priv->base + EIP197_HIA_AIC_R_ACK(ring));
683 static int safexcel_request_ring_irq(struct platform_device *pdev, const char *name,
684 irq_handler_t handler,
685 struct safexcel_ring_irq_data *ring_irq_priv)
687 int ret, irq = platform_get_irq_byname(pdev, name);
690 dev_err(&pdev->dev, "unable to get IRQ '%s'\n", name);
694 ret = devm_request_irq(&pdev->dev, irq, handler, 0,
695 dev_name(&pdev->dev), ring_irq_priv);
697 dev_err(&pdev->dev, "unable to request IRQ %d\n", irq);
704 static struct safexcel_alg_template *safexcel_algs[] = {
705 &safexcel_alg_ecb_aes,
706 &safexcel_alg_cbc_aes,
708 &safexcel_alg_sha224,
709 &safexcel_alg_sha256,
710 &safexcel_alg_hmac_sha1,
713 static int safexcel_register_algorithms(struct safexcel_crypto_priv *priv)
717 for (i = 0; i < ARRAY_SIZE(safexcel_algs); i++) {
718 safexcel_algs[i]->priv = priv;
720 if (safexcel_algs[i]->type == SAFEXCEL_ALG_TYPE_SKCIPHER)
721 ret = crypto_register_skcipher(&safexcel_algs[i]->alg.skcipher);
723 ret = crypto_register_ahash(&safexcel_algs[i]->alg.ahash);
732 for (j = 0; j < i; j++) {
733 if (safexcel_algs[j]->type == SAFEXCEL_ALG_TYPE_SKCIPHER)
734 crypto_unregister_skcipher(&safexcel_algs[j]->alg.skcipher);
736 crypto_unregister_ahash(&safexcel_algs[j]->alg.ahash);
742 static void safexcel_unregister_algorithms(struct safexcel_crypto_priv *priv)
746 for (i = 0; i < ARRAY_SIZE(safexcel_algs); i++) {
747 if (safexcel_algs[i]->type == SAFEXCEL_ALG_TYPE_SKCIPHER)
748 crypto_unregister_skcipher(&safexcel_algs[i]->alg.skcipher);
750 crypto_unregister_ahash(&safexcel_algs[i]->alg.ahash);
754 static void safexcel_configure(struct safexcel_crypto_priv *priv)
758 val = readl(priv->base + EIP197_HIA_OPTIONS);
759 val = (val & GENMASK(27, 25)) >> 25;
762 val = readl(priv->base + EIP197_HIA_OPTIONS);
763 priv->config.rings = min_t(u32, val & GENMASK(3, 0), max_rings);
765 priv->config.cd_size = (sizeof(struct safexcel_command_desc) / sizeof(u32));
766 priv->config.cd_offset = (priv->config.cd_size + mask) & ~mask;
768 priv->config.rd_size = (sizeof(struct safexcel_result_desc) / sizeof(u32));
769 priv->config.rd_offset = (priv->config.rd_size + mask) & ~mask;
772 static int safexcel_probe(struct platform_device *pdev)
774 struct device *dev = &pdev->dev;
775 struct resource *res;
776 struct safexcel_crypto_priv *priv;
779 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
785 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
786 priv->base = devm_ioremap_resource(dev, res);
787 if (IS_ERR(priv->base)) {
788 dev_err(dev, "failed to get resource\n");
789 return PTR_ERR(priv->base);
792 priv->clk = of_clk_get(dev->of_node, 0);
793 if (!IS_ERR(priv->clk)) {
794 ret = clk_prepare_enable(priv->clk);
796 dev_err(dev, "unable to enable clk (%d)\n", ret);
800 /* The clock isn't mandatory */
801 if (PTR_ERR(priv->clk) == -EPROBE_DEFER)
802 return -EPROBE_DEFER;
805 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
809 priv->context_pool = dmam_pool_create("safexcel-context", dev,
810 sizeof(struct safexcel_context_record),
812 if (!priv->context_pool) {
817 safexcel_configure(priv);
819 for (i = 0; i < priv->config.rings; i++) {
820 char irq_name[6] = {0}; /* "ringX\0" */
821 char wq_name[9] = {0}; /* "wq_ringX\0" */
823 struct safexcel_ring_irq_data *ring_irq;
825 ret = safexcel_init_ring_descriptors(priv,
831 ring_irq = devm_kzalloc(dev, sizeof(*ring_irq), GFP_KERNEL);
837 ring_irq->priv = priv;
840 snprintf(irq_name, 6, "ring%d", i);
841 irq = safexcel_request_ring_irq(pdev, irq_name, safexcel_irq_ring,
848 priv->ring[i].work_data.priv = priv;
849 priv->ring[i].work_data.ring = i;
850 INIT_WORK(&priv->ring[i].work_data.work, safexcel_handle_result_work);
852 snprintf(wq_name, 9, "wq_ring%d", i);
853 priv->ring[i].workqueue = create_singlethread_workqueue(wq_name);
854 if (!priv->ring[i].workqueue) {
859 crypto_init_queue(&priv->ring[i].queue,
860 EIP197_DEFAULT_RING_SIZE);
862 INIT_LIST_HEAD(&priv->ring[i].list);
863 spin_lock_init(&priv->ring[i].lock);
864 spin_lock_init(&priv->ring[i].egress_lock);
865 spin_lock_init(&priv->ring[i].queue_lock);
868 platform_set_drvdata(pdev, priv);
869 atomic_set(&priv->ring_used, 0);
871 ret = safexcel_hw_init(priv);
873 dev_err(dev, "EIP h/w init failed (%d)\n", ret);
877 ret = safexcel_register_algorithms(priv);
879 dev_err(dev, "Failed to register algorithms (%d)\n", ret);
886 clk_disable_unprepare(priv->clk);
891 static int safexcel_remove(struct platform_device *pdev)
893 struct safexcel_crypto_priv *priv = platform_get_drvdata(pdev);
896 safexcel_unregister_algorithms(priv);
897 clk_disable_unprepare(priv->clk);
899 for (i = 0; i < priv->config.rings; i++)
900 destroy_workqueue(priv->ring[i].workqueue);
905 static const struct of_device_id safexcel_of_match_table[] = {
906 { .compatible = "inside-secure,safexcel-eip197" },
911 static struct platform_driver crypto_safexcel = {
912 .probe = safexcel_probe,
913 .remove = safexcel_remove,
915 .name = "crypto-safexcel",
916 .of_match_table = safexcel_of_match_table,
919 module_platform_driver(crypto_safexcel);
921 MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
922 MODULE_AUTHOR("Ofer Heifetz <oferh@marvell.com>");
923 MODULE_AUTHOR("Igal Liberman <igall@marvell.com>");
924 MODULE_DESCRIPTION("Support for SafeXcel cryptographic engine EIP197");
925 MODULE_LICENSE("GPL v2");