drivers/crypto/hisilicon/qm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2019 HiSilicon Limited. */
   3 #include <asm/page.h>
   4 #include <linux/acpi.h>
   5 #include <linux/aer.h>
   6 #include <linux/bitmap.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/idr.h>
   9 #include <linux/io.h>
  10 #include <linux/irqreturn.h>
  11 #include <linux/log2.h>
  12 #include <linux/pm_runtime.h>
  13 #include <linux/seq_file.h>
  14 #include <linux/slab.h>
  15 #include <linux/uacce.h>
  16 #include <linux/uaccess.h>
  17 #include <uapi/misc/uacce/hisi_qm.h>
  18 #include <linux/hisi_acc_qm.h>
  19
  20 /* eq/aeq irq enable */
  21 #define QM_VF_AEQ_INT_SOURCE            0x0
  22 #define QM_VF_AEQ_INT_MASK              0x4
  23 #define QM_VF_EQ_INT_SOURCE             0x8
  24 #define QM_VF_EQ_INT_MASK               0xc
  25
  26 #define QM_IRQ_VECTOR_MASK              GENMASK(15, 0)
  27 #define QM_IRQ_TYPE_MASK                GENMASK(15, 0)
  28 #define QM_IRQ_TYPE_SHIFT               16
  29 #define QM_ABN_IRQ_TYPE_MASK            GENMASK(7, 0)
  30
  31 /* mailbox */
  32 #define QM_MB_PING_ALL_VFS              0xffff
  33 #define QM_MB_CMD_DATA_SHIFT            32
  34 #define QM_MB_CMD_DATA_MASK             GENMASK(31, 0)
  35 #define QM_MB_STATUS_MASK               GENMASK(12, 9)
  36
  37 /* sqc shift */
  38 #define QM_SQ_HOP_NUM_SHIFT             0
  39 #define QM_SQ_PAGE_SIZE_SHIFT           4
  40 #define QM_SQ_BUF_SIZE_SHIFT            8
  41 #define QM_SQ_SQE_SIZE_SHIFT            12
  42 #define QM_SQ_PRIORITY_SHIFT            0
  43 #define QM_SQ_ORDERS_SHIFT              4
  44 #define QM_SQ_TYPE_SHIFT                8
  45 #define QM_QC_PASID_ENABLE              0x1
  46 #define QM_QC_PASID_ENABLE_SHIFT        7
  47
  48 #define QM_SQ_TYPE_MASK                 GENMASK(3, 0)
  49 #define QM_SQ_TAIL_IDX(sqc)             ((le16_to_cpu((sqc)->w11) >> 6) & 0x1)
  50
  51 /* cqc shift */
  52 #define QM_CQ_HOP_NUM_SHIFT             0
  53 #define QM_CQ_PAGE_SIZE_SHIFT           4
  54 #define QM_CQ_BUF_SIZE_SHIFT            8
  55 #define QM_CQ_CQE_SIZE_SHIFT            12
  56 #define QM_CQ_PHASE_SHIFT               0
  57 #define QM_CQ_FLAG_SHIFT                1
  58
  59 #define QM_CQE_PHASE(cqe)               (le16_to_cpu((cqe)->w7) & 0x1)
  60 #define QM_QC_CQE_SIZE                  4
  61 #define QM_CQ_TAIL_IDX(cqc)             ((le16_to_cpu((cqc)->w11) >> 6) & 0x1)
  62
  63 /* eqc shift */
  64 #define QM_EQE_AEQE_SIZE                (2UL << 12)
  65 #define QM_EQC_PHASE_SHIFT              16
  66
  67 #define QM_EQE_PHASE(eqe)               ((le32_to_cpu((eqe)->dw0) >> 16) & 0x1)
  68 #define QM_EQE_CQN_MASK                 GENMASK(15, 0)
  69
  70 #define QM_AEQE_PHASE(aeqe)             ((le32_to_cpu((aeqe)->dw0) >> 16) & 0x1)
  71 #define QM_AEQE_TYPE_SHIFT              17
  72 #define QM_AEQE_CQN_MASK                GENMASK(15, 0)
  73 #define QM_CQ_OVERFLOW                  0
  74 #define QM_EQ_OVERFLOW                  1
  75 #define QM_CQE_ERROR                    2
  76
  77 #define QM_XQ_DEPTH_SHIFT               16
  78 #define QM_XQ_DEPTH_MASK                GENMASK(15, 0)
  79
  80 #define QM_DOORBELL_CMD_SQ              0
  81 #define QM_DOORBELL_CMD_CQ              1
  82 #define QM_DOORBELL_CMD_EQ              2
  83 #define QM_DOORBELL_CMD_AEQ             3
  84
  85 #define QM_DOORBELL_BASE_V1             0x340
  86 #define QM_DB_CMD_SHIFT_V1              16
  87 #define QM_DB_INDEX_SHIFT_V1            32
  88 #define QM_DB_PRIORITY_SHIFT_V1         48
  89 #define QM_PAGE_SIZE                    0x0034
  90 #define QM_QP_DB_INTERVAL               0x10000
  91
  92 #define QM_MEM_START_INIT               0x100040
  93 #define QM_MEM_INIT_DONE                0x100044
  94 #define QM_VFT_CFG_RDY                  0x10006c
  95 #define QM_VFT_CFG_OP_WR                0x100058
  96 #define QM_VFT_CFG_TYPE                 0x10005c
  97 #define QM_SQC_VFT                      0x0
  98 #define QM_CQC_VFT                      0x1
  99 #define QM_VFT_CFG                      0x100060
 100 #define QM_VFT_CFG_OP_ENABLE            0x100054
 101 #define QM_PM_CTRL                      0x100148
 102 #define QM_IDLE_DISABLE                 BIT(9)
 103
 104 #define QM_VFT_CFG_DATA_L               0x100064
 105 #define QM_VFT_CFG_DATA_H               0x100068
 106 #define QM_SQC_VFT_BUF_SIZE             (7ULL << 8)
 107 #define QM_SQC_VFT_SQC_SIZE             (5ULL << 12)
 108 #define QM_SQC_VFT_INDEX_NUMBER         (1ULL << 16)
 109 #define QM_SQC_VFT_START_SQN_SHIFT      28
 110 #define QM_SQC_VFT_VALID                (1ULL << 44)
 111 #define QM_SQC_VFT_SQN_SHIFT            45
 112 #define QM_CQC_VFT_BUF_SIZE             (7ULL << 8)
 113 #define QM_CQC_VFT_SQC_SIZE             (5ULL << 12)
 114 #define QM_CQC_VFT_INDEX_NUMBER         (1ULL << 16)
 115 #define QM_CQC_VFT_VALID                (1ULL << 28)
 116
 117 #define QM_SQC_VFT_BASE_SHIFT_V2        28
 118 #define QM_SQC_VFT_BASE_MASK_V2         GENMASK(15, 0)
 119 #define QM_SQC_VFT_NUM_SHIFT_V2         45
 120 #define QM_SQC_VFT_NUM_MASK_v2          GENMASK(9, 0)
 121
 122 #define QM_DFX_CNT_CLR_CE               0x100118
 123
 124 #define QM_ABNORMAL_INT_SOURCE          0x100000
 125 #define QM_ABNORMAL_INT_MASK            0x100004
 126 #define QM_ABNORMAL_INT_MASK_VALUE      0x7fff
 127 #define QM_ABNORMAL_INT_STATUS          0x100008
 128 #define QM_ABNORMAL_INT_SET             0x10000c
 129 #define QM_ABNORMAL_INF00               0x100010
 130 #define QM_FIFO_OVERFLOW_TYPE           0xc0
 131 #define QM_FIFO_OVERFLOW_TYPE_SHIFT     6
 132 #define QM_FIFO_OVERFLOW_VF             0x3f
 133 #define QM_ABNORMAL_INF01               0x100014
 134 #define QM_DB_TIMEOUT_TYPE              0xc0
 135 #define QM_DB_TIMEOUT_TYPE_SHIFT        6
 136 #define QM_DB_TIMEOUT_VF                0x3f
 137 #define QM_RAS_CE_ENABLE                0x1000ec
 138 #define QM_RAS_FE_ENABLE                0x1000f0
 139 #define QM_RAS_NFE_ENABLE               0x1000f4
 140 #define QM_RAS_CE_THRESHOLD             0x1000f8
 141 #define QM_RAS_CE_TIMES_PER_IRQ         1
 142 #define QM_OOO_SHUTDOWN_SEL             0x1040f8
 143 #define QM_ECC_MBIT                     BIT(2)
 144 #define QM_DB_TIMEOUT                   BIT(10)
 145 #define QM_OF_FIFO_OF                   BIT(11)
 146
 147 #define QM_RESET_WAIT_TIMEOUT           400
 148 #define QM_PEH_VENDOR_ID                0x1000d8
 149 #define ACC_VENDOR_ID_VALUE             0x5a5a
 150 #define QM_PEH_DFX_INFO0                0x1000fc
 151 #define QM_PEH_DFX_INFO1                0x100100
 152 #define QM_PEH_DFX_MASK                 (BIT(0) | BIT(2))
 153 #define QM_PEH_MSI_FINISH_MASK          GENMASK(19, 16)
 154 #define ACC_PEH_SRIOV_CTRL_VF_MSE_SHIFT 3
 155 #define ACC_PEH_MSI_DISABLE             GENMASK(31, 0)
 156 #define ACC_MASTER_GLOBAL_CTRL_SHUTDOWN 0x1
 157 #define ACC_MASTER_TRANS_RETURN_RW      3
 158 #define ACC_MASTER_TRANS_RETURN         0x300150
 159 #define ACC_MASTER_GLOBAL_CTRL          0x300000
 160 #define ACC_AM_CFG_PORT_WR_EN           0x30001c
 161 #define QM_RAS_NFE_MBIT_DISABLE         ~QM_ECC_MBIT
 162 #define ACC_AM_ROB_ECC_INT_STS          0x300104
 163 #define ACC_ROB_ECC_ERR_MULTPL          BIT(1)
 164 #define QM_MSI_CAP_ENABLE               BIT(16)
 165
 166 /* interfunction communication */
 167 #define QM_IFC_READY_STATUS             0x100128
 168 #define QM_IFC_C_STS_M                  0x10012C
 169 #define QM_IFC_INT_SET_P                0x100130
 170 #define QM_IFC_INT_CFG                  0x100134
 171 #define QM_IFC_INT_SOURCE_P             0x100138
 172 #define QM_IFC_INT_SOURCE_V             0x0020
 173 #define QM_IFC_INT_MASK                 0x0024
 174 #define QM_IFC_INT_STATUS               0x0028
 175 #define QM_IFC_INT_SET_V                0x002C
 176 #define QM_IFC_SEND_ALL_VFS             GENMASK(6, 0)
 177 #define QM_IFC_INT_SOURCE_CLR           GENMASK(63, 0)
 178 #define QM_IFC_INT_SOURCE_MASK          BIT(0)
 179 #define QM_IFC_INT_DISABLE              BIT(0)
 180 #define QM_IFC_INT_STATUS_MASK          BIT(0)
 181 #define QM_IFC_INT_SET_MASK             BIT(0)
 182 #define QM_WAIT_DST_ACK                 10
 183 #define QM_MAX_PF_WAIT_COUNT            10
 184 #define QM_MAX_VF_WAIT_COUNT            40
 185 #define QM_VF_RESET_WAIT_US            20000
 186 #define QM_VF_RESET_WAIT_CNT           3000
 187 #define QM_VF_RESET_WAIT_TIMEOUT_US    \
 188         (QM_VF_RESET_WAIT_US * QM_VF_RESET_WAIT_CNT)
 189
 190 #define QM_DFX_MB_CNT_VF                0x104010
 191 #define QM_DFX_DB_CNT_VF                0x104020
 192 #define QM_DFX_SQE_CNT_VF_SQN           0x104030
 193 #define QM_DFX_CQE_CNT_VF_CQN           0x104040
 194 #define QM_DFX_QN_SHIFT                 16
 195 #define CURRENT_FUN_MASK                GENMASK(5, 0)
 196 #define CURRENT_Q_MASK                  GENMASK(31, 16)
 197
 198 #define POLL_PERIOD                     10
 199 #define POLL_TIMEOUT                    1000
 200 #define WAIT_PERIOD_US_MAX              200
 201 #define WAIT_PERIOD_US_MIN              100
 202 #define MAX_WAIT_COUNTS                 1000
 203 #define QM_CACHE_WB_START               0x204
 204 #define QM_CACHE_WB_DONE                0x208
 205 #define QM_FUNC_CAPS_REG                0x3100
 206 #define QM_CAPBILITY_VERSION            GENMASK(7, 0)
 207
 208 #define PCI_BAR_2                       2
 209 #define PCI_BAR_4                       4
 210 #define QM_SQE_DATA_ALIGN_MASK          GENMASK(6, 0)
 211 #define QMC_ALIGN(sz)                   ALIGN(sz, 32)
 212
 213 #define QM_DBG_READ_LEN         256
 214 #define QM_DBG_WRITE_LEN                1024
 215 #define QM_DBG_TMP_BUF_LEN              22
 216 #define QM_PCI_COMMAND_INVALID          ~0
 217 #define QM_RESET_STOP_TX_OFFSET         1
 218 #define QM_RESET_STOP_RX_OFFSET         2
 219
 220 #define WAIT_PERIOD                     20
 221 #define REMOVE_WAIT_DELAY               10
 222 #define QM_SQE_ADDR_MASK                GENMASK(7, 0)
 223
 224 #define QM_DRIVER_REMOVING              0
 225 #define QM_RST_SCHED                    1
 226 #define QM_RESETTING                    2
 227 #define QM_QOS_PARAM_NUM                2
 228 #define QM_QOS_VAL_NUM                  1
 229 #define QM_QOS_BDF_PARAM_NUM            4
 230 #define QM_QOS_MAX_VAL                  1000
 231 #define QM_QOS_RATE                     100
 232 #define QM_QOS_EXPAND_RATE              1000
 233 #define QM_SHAPER_CIR_B_MASK            GENMASK(7, 0)
 234 #define QM_SHAPER_CIR_U_MASK            GENMASK(10, 8)
 235 #define QM_SHAPER_CIR_S_MASK            GENMASK(14, 11)
 236 #define QM_SHAPER_FACTOR_CIR_U_SHIFT    8
 237 #define QM_SHAPER_FACTOR_CIR_S_SHIFT    11
 238 #define QM_SHAPER_FACTOR_CBS_B_SHIFT    15
 239 #define QM_SHAPER_FACTOR_CBS_S_SHIFT    19
 240 #define QM_SHAPER_CBS_B                 1
 241 #define QM_SHAPER_CBS_S                 16
 242 #define QM_SHAPER_VFT_OFFSET            6
 243 #define WAIT_FOR_QOS_VF                 100
 244 #define QM_QOS_MIN_ERROR_RATE           5
 245 #define QM_QOS_TYPICAL_NUM              8
 246 #define QM_SHAPER_MIN_CBS_S             8
 247 #define QM_QOS_TICK                     0x300U
 248 #define QM_QOS_DIVISOR_CLK              0x1f40U
 249 #define QM_QOS_MAX_CIR_B                200
 250 #define QM_QOS_MIN_CIR_B                100
 251 #define QM_QOS_MAX_CIR_U                6
 252 #define QM_QOS_MAX_CIR_S                11
 253 #define QM_QOS_VAL_MAX_LEN              32
 254 #define QM_DFX_BASE             0x0100000
 255 #define QM_DFX_STATE1           0x0104000
 256 #define QM_DFX_STATE2           0x01040C8
 257 #define QM_DFX_COMMON           0x0000
 258 #define QM_DFX_BASE_LEN         0x5A
 259 #define QM_DFX_STATE1_LEN               0x2E
 260 #define QM_DFX_STATE2_LEN               0x11
 261 #define QM_DFX_COMMON_LEN               0xC3
 262 #define QM_DFX_REGS_LEN         4UL
 263 #define QM_AUTOSUSPEND_DELAY            3000
 264
 265 #define QM_MK_CQC_DW3_V1(hop_num, pg_sz, buf_sz, cqe_sz) \
 266         (((hop_num) << QM_CQ_HOP_NUM_SHIFT)     | \
 267         ((pg_sz) << QM_CQ_PAGE_SIZE_SHIFT)      | \
 268         ((buf_sz) << QM_CQ_BUF_SIZE_SHIFT)      | \
 269         ((cqe_sz) << QM_CQ_CQE_SIZE_SHIFT))
 270
 271 #define QM_MK_CQC_DW3_V2(cqe_sz, cq_depth) \
 272         ((((u32)cq_depth) - 1) | ((cqe_sz) << QM_CQ_CQE_SIZE_SHIFT))
 273
 274 #define QM_MK_SQC_W13(priority, orders, alg_type) \
 275         (((priority) << QM_SQ_PRIORITY_SHIFT)   | \
 276         ((orders) << QM_SQ_ORDERS_SHIFT)        | \
 277         (((alg_type) & QM_SQ_TYPE_MASK) << QM_SQ_TYPE_SHIFT))
 278
 279 #define QM_MK_SQC_DW3_V1(hop_num, pg_sz, buf_sz, sqe_sz) \
 280         (((hop_num) << QM_SQ_HOP_NUM_SHIFT)     | \
 281         ((pg_sz) << QM_SQ_PAGE_SIZE_SHIFT)      | \
 282         ((buf_sz) << QM_SQ_BUF_SIZE_SHIFT)      | \
 283         ((u32)ilog2(sqe_sz) << QM_SQ_SQE_SIZE_SHIFT))
 284
 285 #define QM_MK_SQC_DW3_V2(sqe_sz, sq_depth) \
 286         ((((u32)sq_depth) - 1) | ((u32)ilog2(sqe_sz) << QM_SQ_SQE_SIZE_SHIFT))
 287
 288 #define INIT_QC_COMMON(qc, base, pasid) do {                    \
 289         (qc)->head = 0;                                         \
 290         (qc)->tail = 0;                                         \
 291         (qc)->base_l = cpu_to_le32(lower_32_bits(base));        \
 292         (qc)->base_h = cpu_to_le32(upper_32_bits(base));        \
 293         (qc)->dw3 = 0;                                          \
 294         (qc)->w8 = 0;                                           \
 295         (qc)->rsvd0 = 0;                                        \
 296         (qc)->pasid = cpu_to_le16(pasid);                       \
 297         (qc)->w11 = 0;                                          \
 298         (qc)->rsvd1 = 0;                                        \
 299 } while (0)
 300
 301 enum vft_type {
 302         SQC_VFT = 0,
 303         CQC_VFT,
 304         SHAPER_VFT,
 305 };
 306
 307 enum acc_err_result {
 308         ACC_ERR_NONE,
 309         ACC_ERR_NEED_RESET,
 310         ACC_ERR_RECOVERED,
 311 };
 312
 313 enum qm_alg_type {
 314         ALG_TYPE_0,
 315         ALG_TYPE_1,
 316 };
 317
 318 enum qm_mb_cmd {
 319         QM_PF_FLR_PREPARE = 0x01,
 320         QM_PF_SRST_PREPARE,
 321         QM_PF_RESET_DONE,
 322         QM_VF_PREPARE_DONE,
 323         QM_VF_PREPARE_FAIL,
 324         QM_VF_START_DONE,
 325         QM_VF_START_FAIL,
 326         QM_PF_SET_QOS,
 327         QM_VF_GET_QOS,
 328 };
 329
 330 enum qm_basic_type {
 331         QM_TOTAL_QP_NUM_CAP = 0x0,
 332         QM_FUNC_MAX_QP_CAP,
 333         QM_XEQ_DEPTH_CAP,
 334         QM_QP_DEPTH_CAP,
 335         QM_EQ_IRQ_TYPE_CAP,
 336         QM_AEQ_IRQ_TYPE_CAP,
 337         QM_ABN_IRQ_TYPE_CAP,
 338         QM_PF2VF_IRQ_TYPE_CAP,
 339         QM_PF_IRQ_NUM_CAP,
 340         QM_VF_IRQ_NUM_CAP,
 341 };
 342
 343 static const struct hisi_qm_cap_info qm_cap_info_comm[] = {
 344         {QM_SUPPORT_DB_ISOLATION, 0x30,   0, BIT(0),  0x0, 0x0, 0x0},
 345         {QM_SUPPORT_FUNC_QOS,     0x3100, 0, BIT(8),  0x0, 0x0, 0x1},
 346         {QM_SUPPORT_STOP_QP,      0x3100, 0, BIT(9),  0x0, 0x0, 0x1},
 347         {QM_SUPPORT_MB_COMMAND,   0x3100, 0, BIT(11), 0x0, 0x0, 0x1},
 348         {QM_SUPPORT_SVA_PREFETCH, 0x3100, 0, BIT(14), 0x0, 0x0, 0x1},
 349 };
 350
 351 static const struct hisi_qm_cap_info qm_cap_info_pf[] = {
 352         {QM_SUPPORT_RPM, 0x3100, 0, BIT(13), 0x0, 0x0, 0x1},
 353 };
 354
 355 static const struct hisi_qm_cap_info qm_cap_info_vf[] = {
 356         {QM_SUPPORT_RPM, 0x3100, 0, BIT(12), 0x0, 0x0, 0x0},
 357 };
 358
 359 static const struct hisi_qm_cap_info qm_basic_info[] = {
 360         {QM_TOTAL_QP_NUM_CAP,   0x100158, 0,  GENMASK(10, 0), 0x1000,    0x400,     0x400},
 361         {QM_FUNC_MAX_QP_CAP,    0x100158, 11, GENMASK(10, 0), 0x1000,    0x400,     0x400},
 362         {QM_XEQ_DEPTH_CAP,      0x3104,   0,  GENMASK(15, 0), 0x800,     0x4000800, 0x4000800},
 363         {QM_QP_DEPTH_CAP,       0x3108,   0,  GENMASK(31, 0), 0x4000400, 0x4000400, 0x4000400},
 364         {QM_EQ_IRQ_TYPE_CAP,    0x310c,   0,  GENMASK(31, 0), 0x10000,   0x10000,   0x10000},
 365         {QM_AEQ_IRQ_TYPE_CAP,   0x3110,   0,  GENMASK(31, 0), 0x0,       0x10001,   0x10001},
 366         {QM_ABN_IRQ_TYPE_CAP,   0x3114,   0,  GENMASK(31, 0), 0x0,       0x10003,   0x10003},
 367         {QM_PF2VF_IRQ_TYPE_CAP, 0x3118,   0,  GENMASK(31, 0), 0x0,       0x0,       0x10002},
 368         {QM_PF_IRQ_NUM_CAP,     0x311c,   16, GENMASK(15, 0), 0x1,       0x4,       0x4},
 369         {QM_VF_IRQ_NUM_CAP,     0x311c,   0,  GENMASK(15, 0), 0x1,       0x2,       0x3},
 370 };
 371
 372 struct qm_cqe {
 373         __le32 rsvd0;
 374         __le16 cmd_id;
 375         __le16 rsvd1;
 376         __le16 sq_head;
 377         __le16 sq_num;
 378         __le16 rsvd2;
 379         __le16 w7;
 380 };
 381
 382 struct qm_eqe {
 383         __le32 dw0;
 384 };
 385
 386 struct qm_aeqe {
 387         __le32 dw0;
 388 };
 389
 390 struct qm_sqc {
 391         __le16 head;
 392         __le16 tail;
 393         __le32 base_l;
 394         __le32 base_h;
 395         __le32 dw3;
 396         __le16 w8;
 397         __le16 rsvd0;
 398         __le16 pasid;
 399         __le16 w11;
 400         __le16 cq_num;
 401         __le16 w13;
 402         __le32 rsvd1;
 403 };
 404
 405 struct qm_cqc {
 406         __le16 head;
 407         __le16 tail;
 408         __le32 base_l;
 409         __le32 base_h;
 410         __le32 dw3;
 411         __le16 w8;
 412         __le16 rsvd0;
 413         __le16 pasid;
 414         __le16 w11;
 415         __le32 dw6;
 416         __le32 rsvd1;
 417 };
 418
 419 struct qm_eqc {
 420         __le16 head;
 421         __le16 tail;
 422         __le32 base_l;
 423         __le32 base_h;
 424         __le32 dw3;
 425         __le32 rsvd[2];
 426         __le32 dw6;
 427 };
 428
 429 struct qm_aeqc {
 430         __le16 head;
 431         __le16 tail;
 432         __le32 base_l;
 433         __le32 base_h;
 434         __le32 dw3;
 435         __le32 rsvd[2];
 436         __le32 dw6;
 437 };
 438
 439 struct qm_mailbox {
 440         __le16 w0;
 441         __le16 queue_num;
 442         __le32 base_l;
 443         __le32 base_h;
 444         __le32 rsvd;
 445 };
 446
 447 struct qm_doorbell {
 448         __le16 queue_num;
 449         __le16 cmd;
 450         __le16 index;
 451         __le16 priority;
 452 };
 453
 454 struct hisi_qm_resource {
 455         struct hisi_qm *qm;
 456         int distance;
 457         struct list_head list;
 458 };
 459
 460 struct hisi_qm_hw_ops {
 461         int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number);
 462         void (*qm_db)(struct hisi_qm *qm, u16 qn,
 463                       u8 cmd, u16 index, u8 priority);
 464         int (*debug_init)(struct hisi_qm *qm);
 465         void (*hw_error_init)(struct hisi_qm *qm);
 466         void (*hw_error_uninit)(struct hisi_qm *qm);
 467         enum acc_err_result (*hw_error_handle)(struct hisi_qm *qm);
 468         int (*set_msi)(struct hisi_qm *qm, bool set);
 469 };
 470
 471 struct qm_dfx_item {
 472         const char *name;
 473         u32 offset;
 474 };
 475
 476 static struct qm_dfx_item qm_dfx_files[] = {
 477         {"err_irq", offsetof(struct qm_dfx, err_irq_cnt)},
 478         {"aeq_irq", offsetof(struct qm_dfx, aeq_irq_cnt)},
 479         {"abnormal_irq", offsetof(struct qm_dfx, abnormal_irq_cnt)},
 480         {"create_qp_err", offsetof(struct qm_dfx, create_qp_err_cnt)},
 481         {"mb_err", offsetof(struct qm_dfx, mb_err_cnt)},
 482 };
 483
 484 static const char * const qm_debug_file_name[] = {
 485         [CURRENT_QM]   = "current_qm",
 486         [CURRENT_Q]    = "current_q",
 487         [CLEAR_ENABLE] = "clear_enable",
 488 };
 489
 490 struct hisi_qm_hw_error {
 491         u32 int_msk;
 492         const char *msg;
 493 };
 494
 495 static const struct hisi_qm_hw_error qm_hw_error[] = {
 496         { .int_msk = BIT(0), .msg = "qm_axi_rresp" },
 497         { .int_msk = BIT(1), .msg = "qm_axi_bresp" },
 498         { .int_msk = BIT(2), .msg = "qm_ecc_mbit" },
 499         { .int_msk = BIT(3), .msg = "qm_ecc_1bit" },
 500         { .int_msk = BIT(4), .msg = "qm_acc_get_task_timeout" },
 501         { .int_msk = BIT(5), .msg = "qm_acc_do_task_timeout" },
 502         { .int_msk = BIT(6), .msg = "qm_acc_wb_not_ready_timeout" },
 503         { .int_msk = BIT(7), .msg = "qm_sq_cq_vf_invalid" },
 504         { .int_msk = BIT(8), .msg = "qm_cq_vf_invalid" },
 505         { .int_msk = BIT(9), .msg = "qm_sq_vf_invalid" },
 506         { .int_msk = BIT(10), .msg = "qm_db_timeout" },
 507         { .int_msk = BIT(11), .msg = "qm_of_fifo_of" },
 508         { .int_msk = BIT(12), .msg = "qm_db_random_invalid" },
 509         { .int_msk = BIT(13), .msg = "qm_mailbox_timeout" },
 510         { .int_msk = BIT(14), .msg = "qm_flr_timeout" },
 511         { /* sentinel */ }
 512 };
 513
 514 /* define the QM's dfx regs region and region length */
 515 static struct dfx_diff_registers qm_diff_regs[] = {
 516         {
 517                 .reg_offset = QM_DFX_BASE,
 518                 .reg_len = QM_DFX_BASE_LEN,
 519         }, {
 520                 .reg_offset = QM_DFX_STATE1,
 521                 .reg_len = QM_DFX_STATE1_LEN,
 522         }, {
 523                 .reg_offset = QM_DFX_STATE2,
 524                 .reg_len = QM_DFX_STATE2_LEN,
 525         }, {
 526                 .reg_offset = QM_DFX_COMMON,
 527                 .reg_len = QM_DFX_COMMON_LEN,
 528         },
 529 };
 530
 531 static const char * const qm_db_timeout[] = {
 532         "sq", "cq", "eq", "aeq",
 533 };
 534
 535 static const char * const qm_fifo_overflow[] = {
 536         "cq", "eq", "aeq",
 537 };
 538
 539 static const char * const qm_s[] = {
 540         "init", "start", "close", "stop",
 541 };
 542
 543 static const char * const qp_s[] = {
 544         "none", "init", "start", "stop", "close",
 545 };
 546
 547 struct qm_typical_qos_table {
 548         u32 start;
 549         u32 end;
 550         u32 val;
 551 };
 552
 553 /* the qos step is 100 */
 554 static struct qm_typical_qos_table shaper_cir_s[] = {
 555         {100, 100, 4},
 556         {200, 200, 3},
 557         {300, 500, 2},
 558         {600, 1000, 1},
 559         {1100, 100000, 0},
 560 };
 561
 562 static struct qm_typical_qos_table shaper_cbs_s[] = {
 563         {100, 200, 9},
 564         {300, 500, 11},
 565         {600, 1000, 12},
 566         {1100, 10000, 16},
 567         {10100, 25000, 17},
 568         {25100, 50000, 18},
 569         {50100, 100000, 19}
 570 };
 571
 572 static void qm_irqs_unregister(struct hisi_qm *qm);
 573
 574 static bool qm_avail_state(struct hisi_qm *qm, enum qm_state new)
 575 {
 576         enum qm_state curr = atomic_read(&qm->status.flags);
 577         bool avail = false;
 578
 579         switch (curr) {
 580         case QM_INIT:
 581                 if (new == QM_START || new == QM_CLOSE)
 582                         avail = true;
 583                 break;
 584         case QM_START:
 585                 if (new == QM_STOP)
 586                         avail = true;
 587                 break;
 588         case QM_STOP:
 589                 if (new == QM_CLOSE || new == QM_START)
 590                         avail = true;
 591                 break;
 592         default:
 593                 break;
 594         }
 595
 596         dev_dbg(&qm->pdev->dev, "change qm state from %s to %s\n",
 597                 qm_s[curr], qm_s[new]);
 598
 599         if (!avail)
 600                 dev_warn(&qm->pdev->dev, "Can not change qm state from %s to %s\n",
 601                          qm_s[curr], qm_s[new]);
 602
 603         return avail;
 604 }
 605
 606 static bool qm_qp_avail_state(struct hisi_qm *qm, struct hisi_qp *qp,
 607                               enum qp_state new)
 608 {
 609         enum qm_state qm_curr = atomic_read(&qm->status.flags);
 610         enum qp_state qp_curr = 0;
 611         bool avail = false;
 612
 613         if (qp)
 614                 qp_curr = atomic_read(&qp->qp_status.flags);
 615
 616         switch (new) {
 617         case QP_INIT:
 618                 if (qm_curr == QM_START || qm_curr == QM_INIT)
 619                         avail = true;
 620                 break;
 621         case QP_START:
 622                 if ((qm_curr == QM_START && qp_curr == QP_INIT) ||
 623                     (qm_curr == QM_START && qp_curr == QP_STOP))
 624                         avail = true;
 625                 break;
 626         case QP_STOP:
 627                 if ((qm_curr == QM_START && qp_curr == QP_START) ||
 628                     (qp_curr == QP_INIT))
 629                         avail = true;
 630                 break;
 631         case QP_CLOSE:
 632                 if ((qm_curr == QM_START && qp_curr == QP_INIT) ||
 633                     (qm_curr == QM_START && qp_curr == QP_STOP) ||
 634                     (qm_curr == QM_STOP && qp_curr == QP_STOP)  ||
 635                     (qm_curr == QM_STOP && qp_curr == QP_INIT))
 636                         avail = true;
 637                 break;
 638         default:
 639                 break;
 640         }
 641
 642         dev_dbg(&qm->pdev->dev, "change qp state from %s to %s in QM %s\n",
 643                 qp_s[qp_curr], qp_s[new], qm_s[qm_curr]);
 644
 645         if (!avail)
 646                 dev_warn(&qm->pdev->dev,
 647                          "Can not change qp state from %s to %s in QM %s\n",
 648                          qp_s[qp_curr], qp_s[new], qm_s[qm_curr]);
 649
 650         return avail;
 651 }
 652
 653 static u32 qm_get_hw_error_status(struct hisi_qm *qm)
 654 {
 655         return readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
 656 }
 657
 658 static u32 qm_get_dev_err_status(struct hisi_qm *qm)
 659 {
 660         return qm->err_ini->get_dev_hw_err_status(qm);
 661 }
 662
 663 /* Check if the error causes the master ooo block */
 664 static bool qm_check_dev_error(struct hisi_qm *qm)
 665 {
 666         u32 val, dev_val;
 667
 668         if (qm->fun_type == QM_HW_VF)
 669                 return false;
 670
 671         val = qm_get_hw_error_status(qm) & qm->err_info.qm_shutdown_mask;
 672         dev_val = qm_get_dev_err_status(qm) & qm->err_info.dev_shutdown_mask;
 673
 674         return val || dev_val;
 675 }
 676
 677 static int qm_wait_reset_finish(struct hisi_qm *qm)
 678 {
 679         int delay = 0;
 680
 681         /* All reset requests need to be queued for processing */
 682         while (test_and_set_bit(QM_RESETTING, &qm->misc_ctl)) {
 683                 msleep(++delay);
 684                 if (delay > QM_RESET_WAIT_TIMEOUT)
 685                         return -EBUSY;
 686         }
 687
 688         return 0;
 689 }
 690
 691 static int qm_reset_prepare_ready(struct hisi_qm *qm)
 692 {
 693         struct pci_dev *pdev = qm->pdev;
 694         struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(pdev));
 695
 696         /*
 697          * PF and VF on host doesnot support resetting at the
 698          * same time on Kunpeng920.
 699          */
 700         if (qm->ver < QM_HW_V3)
 701                 return qm_wait_reset_finish(pf_qm);
 702
 703         return qm_wait_reset_finish(qm);
 704 }
 705
 706 static void qm_reset_bit_clear(struct hisi_qm *qm)
 707 {
 708         struct pci_dev *pdev = qm->pdev;
 709         struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(pdev));
 710
 711         if (qm->ver < QM_HW_V3)
 712                 clear_bit(QM_RESETTING, &pf_qm->misc_ctl);
 713
 714         clear_bit(QM_RESETTING, &qm->misc_ctl);
 715 }
 716
 717 static void qm_mb_pre_init(struct qm_mailbox *mailbox, u8 cmd,
 718                            u64 base, u16 queue, bool op)
 719 {
 720         mailbox->w0 = cpu_to_le16((cmd) |
 721                 ((op) ? 0x1 << QM_MB_OP_SHIFT : 0) |
 722                 (0x1 << QM_MB_BUSY_SHIFT));
 723         mailbox->queue_num = cpu_to_le16(queue);
 724         mailbox->base_l = cpu_to_le32(lower_32_bits(base));
 725         mailbox->base_h = cpu_to_le32(upper_32_bits(base));
 726         mailbox->rsvd = 0;
 727 }
 728
 729 /* return 0 mailbox ready, -ETIMEDOUT hardware timeout */
 730 int hisi_qm_wait_mb_ready(struct hisi_qm *qm)
 731 {
 732         u32 val;
 733
 734         return readl_relaxed_poll_timeout(qm->io_base + QM_MB_CMD_SEND_BASE,
 735                                           val, !((val >> QM_MB_BUSY_SHIFT) &
 736                                           0x1), POLL_PERIOD, POLL_TIMEOUT);
 737 }
 738 EXPORT_SYMBOL_GPL(hisi_qm_wait_mb_ready);
 739
 740 /* 128 bit should be written to hardware at one time to trigger a mailbox */
 741 static void qm_mb_write(struct hisi_qm *qm, const void *src)
 742 {
 743         void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;
 744         unsigned long tmp0 = 0, tmp1 = 0;
 745
 746         if (!IS_ENABLED(CONFIG_ARM64)) {
 747                 memcpy_toio(fun_base, src, 16);
 748                 dma_wmb();
 749                 return;
 750         }
 751
 752         asm volatile("ldp %0, %1, %3\n"
 753                      "stp %0, %1, %2\n"
 754                      "dmb oshst\n"
 755                      : "=&r" (tmp0),
 756                        "=&r" (tmp1),
 757                        "+Q" (*((char __iomem *)fun_base))
 758                      : "Q" (*((char *)src))
 759                      : "memory");
 760 }
 761
 762 static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox)
 763 {
 764         int ret;
 765         u32 val;
 766
 767         if (unlikely(hisi_qm_wait_mb_ready(qm))) {
 768                 dev_err(&qm->pdev->dev, "QM mailbox is busy to start!\n");
 769                 ret = -EBUSY;
 770                 goto mb_busy;
 771         }
 772
 773         qm_mb_write(qm, mailbox);
 774
 775         if (unlikely(hisi_qm_wait_mb_ready(qm))) {
 776                 dev_err(&qm->pdev->dev, "QM mailbox operation timeout!\n");
 777                 ret = -ETIMEDOUT;
 778                 goto mb_busy;
 779         }
 780
 781         val = readl(qm->io_base + QM_MB_CMD_SEND_BASE);
 782         if (val & QM_MB_STATUS_MASK) {
 783                 dev_err(&qm->pdev->dev, "QM mailbox operation failed!\n");
 784                 ret = -EIO;
 785                 goto mb_busy;
 786         }
 787
 788         return 0;
 789
 790 mb_busy:
 791         atomic64_inc(&qm->debug.dfx.mb_err_cnt);
 792         return ret;
 793 }
 794
 795 int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
 796                bool op)
 797 {
 798         struct qm_mailbox mailbox;
 799         int ret;
 800
 801         dev_dbg(&qm->pdev->dev, "QM mailbox request to q%u: %u-%llx\n",
 802                 queue, cmd, (unsigned long long)dma_addr);
 803
 804         qm_mb_pre_init(&mailbox, cmd, dma_addr, queue, op);
 805
 806         mutex_lock(&qm->mailbox_lock);
 807         ret = qm_mb_nolock(qm, &mailbox);
 808         mutex_unlock(&qm->mailbox_lock);
 809
 810         return ret;
 811 }
 812 EXPORT_SYMBOL_GPL(hisi_qm_mb);
 813
 814 static void qm_db_v1(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
 815 {
 816         u64 doorbell;
 817
 818         doorbell = qn | ((u64)cmd << QM_DB_CMD_SHIFT_V1) |
 819                    ((u64)index << QM_DB_INDEX_SHIFT_V1)  |
 820                    ((u64)priority << QM_DB_PRIORITY_SHIFT_V1);
 821
 822         writeq(doorbell, qm->io_base + QM_DOORBELL_BASE_V1);
 823 }
 824
 825 static void qm_db_v2(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
 826 {
 827         void __iomem *io_base = qm->io_base;
 828         u16 randata = 0;
 829         u64 doorbell;
 830
 831         if (cmd == QM_DOORBELL_CMD_SQ || cmd == QM_DOORBELL_CMD_CQ)
 832                 io_base = qm->db_io_base + (u64)qn * qm->db_interval +
 833                           QM_DOORBELL_SQ_CQ_BASE_V2;
 834         else
 835                 io_base += QM_DOORBELL_EQ_AEQ_BASE_V2;
 836
 837         doorbell = qn | ((u64)cmd << QM_DB_CMD_SHIFT_V2) |
 838                    ((u64)randata << QM_DB_RAND_SHIFT_V2) |
 839                    ((u64)index << QM_DB_INDEX_SHIFT_V2)  |
 840                    ((u64)priority << QM_DB_PRIORITY_SHIFT_V2);
 841
 842         writeq(doorbell, io_base);
 843 }
 844
 845 static void qm_db(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
 846 {
 847         dev_dbg(&qm->pdev->dev, "QM doorbell request: qn=%u, cmd=%u, index=%u\n",
 848                 qn, cmd, index);
 849
 850         qm->ops->qm_db(qm, qn, cmd, index, priority);
 851 }
 852
 853 static void qm_disable_clock_gate(struct hisi_qm *qm)
 854 {
 855         u32 val;
 856
 857         /* if qm enables clock gating in Kunpeng930, qos will be inaccurate. */
 858         if (qm->ver < QM_HW_V3)
 859                 return;
 860
 861         val = readl(qm->io_base + QM_PM_CTRL);
 862         val |= QM_IDLE_DISABLE;
 863         writel(val, qm->io_base +  QM_PM_CTRL);
 864 }
 865
 866 static int qm_dev_mem_reset(struct hisi_qm *qm)
 867 {
 868         u32 val;
 869
 870         writel(0x1, qm->io_base + QM_MEM_START_INIT);
 871         return readl_relaxed_poll_timeout(qm->io_base + QM_MEM_INIT_DONE, val,
 872                                           val & BIT(0), POLL_PERIOD,
 873                                           POLL_TIMEOUT);
 874 }
 875
 876 /**
 877  * hisi_qm_get_hw_info() - Get device information.
 878  * @qm: The qm which want to get information.
 879  * @info_table: Array for storing device information.
 880  * @index: Index in info_table.
 881  * @is_read: Whether read from reg, 0: not support read from reg.
 882  *
 883  * This function returns device information the caller needs.
 884  */
 885 u32 hisi_qm_get_hw_info(struct hisi_qm *qm,
 886                         const struct hisi_qm_cap_info *info_table,
 887                         u32 index, bool is_read)
 888 {
 889         u32 val;
 890
 891         switch (qm->ver) {
 892         case QM_HW_V1:
 893                 return info_table[index].v1_val;
 894         case QM_HW_V2:
 895                 return info_table[index].v2_val;
 896         default:
 897                 if (!is_read)
 898                         return info_table[index].v3_val;
 899
 900                 val = readl(qm->io_base + info_table[index].offset);
 901                 return (val >> info_table[index].shift) & info_table[index].mask;
 902         }
 903 }
 904 EXPORT_SYMBOL_GPL(hisi_qm_get_hw_info);
 905
 906 static void qm_get_xqc_depth(struct hisi_qm *qm, u16 *low_bits,
 907                              u16 *high_bits, enum qm_basic_type type)
 908 {
 909         u32 depth;
 910
 911         depth = hisi_qm_get_hw_info(qm, qm_basic_info, type, qm->cap_ver);
 912         *high_bits = depth & QM_XQ_DEPTH_MASK;
 913         *low_bits = (depth >> QM_XQ_DEPTH_SHIFT) & QM_XQ_DEPTH_MASK;
 914 }
 915
 916 static u32 qm_get_irq_num(struct hisi_qm *qm)
 917 {
 918         if (qm->fun_type == QM_HW_PF)
 919                 return hisi_qm_get_hw_info(qm, qm_basic_info, QM_PF_IRQ_NUM_CAP, qm->cap_ver);
 920
 921         return hisi_qm_get_hw_info(qm, qm_basic_info, QM_VF_IRQ_NUM_CAP, qm->cap_ver);
 922 }
 923
 924 static int qm_pm_get_sync(struct hisi_qm *qm)
 925 {
 926         struct device *dev = &qm->pdev->dev;
 927         int ret;
 928
 929         if (!test_bit(QM_SUPPORT_RPM, &qm->caps))
 930                 return 0;
 931
 932         ret = pm_runtime_resume_and_get(dev);
 933         if (ret < 0) {
 934                 dev_err(dev, "failed to get_sync(%d).\n", ret);
 935                 return ret;
 936         }
 937
 938         return 0;
 939 }
 940
 941 static void qm_pm_put_sync(struct hisi_qm *qm)
 942 {
 943         struct device *dev = &qm->pdev->dev;
 944
 945         if (!test_bit(QM_SUPPORT_RPM, &qm->caps))
 946                 return;
 947
 948         pm_runtime_mark_last_busy(dev);
 949         pm_runtime_put_autosuspend(dev);
 950 }
 951
 952 static void qm_cq_head_update(struct hisi_qp *qp)
 953 {
 954         if (qp->qp_status.cq_head == qp->cq_depth - 1) {
 955                 qp->qp_status.cqc_phase = !qp->qp_status.cqc_phase;
 956                 qp->qp_status.cq_head = 0;
 957         } else {
 958                 qp->qp_status.cq_head++;
 959         }
 960 }
 961
 962 static void qm_poll_req_cb(struct hisi_qp *qp)
 963 {
 964         struct qm_cqe *cqe = qp->cqe + qp->qp_status.cq_head;
 965         struct hisi_qm *qm = qp->qm;
 966
 967         while (QM_CQE_PHASE(cqe) == qp->qp_status.cqc_phase) {
 968                 dma_rmb();
 969                 qp->req_cb(qp, qp->sqe + qm->sqe_size *
 970                            le16_to_cpu(cqe->sq_head));
 971                 qm_cq_head_update(qp);
 972                 cqe = qp->cqe + qp->qp_status.cq_head;
 973                 qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ,
 974                       qp->qp_status.cq_head, 0);
 975                 atomic_dec(&qp->qp_status.used);
 976         }
 977
 978         /* set c_flag */
 979         qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ, qp->qp_status.cq_head, 1);
 980 }
 981
 982 static int qm_get_complete_eqe_num(struct hisi_qm_poll_data *poll_data)
 983 {
 984         struct hisi_qm *qm = poll_data->qm;
 985         struct qm_eqe *eqe = qm->eqe + qm->status.eq_head;
 986         u16 eq_depth = qm->eq_depth;
 987         int eqe_num = 0;
 988         u16 cqn;
 989
 990         while (QM_EQE_PHASE(eqe) == qm->status.eqc_phase) {
 991                 cqn = le32_to_cpu(eqe->dw0) & QM_EQE_CQN_MASK;
 992                 poll_data->qp_finish_id[eqe_num] = cqn;
 993                 eqe_num++;
 994
 995                 if (qm->status.eq_head == eq_depth - 1) {
 996                         qm->status.eqc_phase = !qm->status.eqc_phase;
 997                         eqe = qm->eqe;
 998                         qm->status.eq_head = 0;
 999                 } else {
1000                         eqe++;
1001                         qm->status.eq_head++;
1002                 }
1003
1004                 if (eqe_num == (eq_depth >> 1) - 1)
1005                         break;
1006         }
1007
1008         qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
1009
1010         return eqe_num;
1011 }
1012
1013 static void qm_work_process(struct work_struct *work)
1014 {
1015         struct hisi_qm_poll_data *poll_data =
1016                 container_of(work, struct hisi_qm_poll_data, work);
1017         struct hisi_qm *qm = poll_data->qm;
1018         struct hisi_qp *qp;
1019         int eqe_num, i;
1020
1021         /* Get qp id of completed tasks and re-enable the interrupt. */
1022         eqe_num = qm_get_complete_eqe_num(poll_data);
1023         for (i = eqe_num - 1; i >= 0; i--) {
1024                 qp = &qm->qp_array[poll_data->qp_finish_id[i]];
1025                 if (unlikely(atomic_read(&qp->qp_status.flags) == QP_STOP))
1026                         continue;
1027
1028                 if (qp->event_cb) {
1029                         qp->event_cb(qp);
1030                         continue;
1031                 }
1032
1033                 if (likely(qp->req_cb))
1034                         qm_poll_req_cb(qp);
1035         }
1036 }
1037
1038 static bool do_qm_irq(struct hisi_qm *qm)
1039 {
1040         struct qm_eqe *eqe = qm->eqe + qm->status.eq_head;
1041         struct hisi_qm_poll_data *poll_data;
1042         u16 cqn;
1043
1044         if (!readl(qm->io_base + QM_VF_EQ_INT_SOURCE))
1045                 return false;
1046
1047         if (QM_EQE_PHASE(eqe) == qm->status.eqc_phase) {
1048                 cqn = le32_to_cpu(eqe->dw0) & QM_EQE_CQN_MASK;
1049                 poll_data = &qm->poll_data[cqn];
1050                 queue_work(qm->wq, &poll_data->work);
1051
1052                 return true;
1053         }
1054
1055         return false;
1056 }
1057
1058 static irqreturn_t qm_irq(int irq, void *data)
1059 {
1060         struct hisi_qm *qm = data;
1061         bool ret;
1062
1063         ret = do_qm_irq(qm);
1064         if (ret)
1065                 return IRQ_HANDLED;
1066
1067         atomic64_inc(&qm->debug.dfx.err_irq_cnt);
1068         qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
1069
1070         return IRQ_NONE;
1071 }
1072
1073 static irqreturn_t qm_mb_cmd_irq(int irq, void *data)
1074 {
1075         struct hisi_qm *qm = data;
1076         u32 val;
1077
1078         val = readl(qm->io_base + QM_IFC_INT_STATUS);
1079         val &= QM_IFC_INT_STATUS_MASK;
1080         if (!val)
1081                 return IRQ_NONE;
1082
1083         schedule_work(&qm->cmd_process);
1084
1085         return IRQ_HANDLED;
1086 }
1087
1088 static void qm_set_qp_disable(struct hisi_qp *qp, int offset)
1089 {
1090         u32 *addr;
1091
1092         if (qp->is_in_kernel)
1093                 return;
1094
1095         addr = (u32 *)(qp->qdma.va + qp->qdma.size) - offset;
1096         *addr = 1;
1097
1098         /* make sure setup is completed */
1099         smp_wmb();
1100 }
1101
1102 static void qm_disable_qp(struct hisi_qm *qm, u32 qp_id)
1103 {
1104         struct hisi_qp *qp = &qm->qp_array[qp_id];
1105
1106         qm_set_qp_disable(qp, QM_RESET_STOP_TX_OFFSET);
1107         hisi_qm_stop_qp(qp);
1108         qm_set_qp_disable(qp, QM_RESET_STOP_RX_OFFSET);
1109 }
1110
1111 static void qm_reset_function(struct hisi_qm *qm)
1112 {
1113         struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(qm->pdev));
1114         struct device *dev = &qm->pdev->dev;
1115         int ret;
1116
1117         if (qm_check_dev_error(pf_qm))
1118                 return;
1119
1120         ret = qm_reset_prepare_ready(qm);
1121         if (ret) {
1122                 dev_err(dev, "reset function not ready\n");
1123                 return;
1124         }
1125
1126         ret = hisi_qm_stop(qm, QM_FLR);
1127         if (ret) {
1128                 dev_err(dev, "failed to stop qm when reset function\n");
1129                 goto clear_bit;
1130         }
1131
1132         ret = hisi_qm_start(qm);
1133         if (ret)
1134                 dev_err(dev, "failed to start qm when reset function\n");
1135
1136 clear_bit:
1137         qm_reset_bit_clear(qm);
1138 }
1139
1140 static irqreturn_t qm_aeq_thread(int irq, void *data)
1141 {
1142         struct hisi_qm *qm = data;
1143         struct qm_aeqe *aeqe = qm->aeqe + qm->status.aeq_head;
1144         u16 aeq_depth = qm->aeq_depth;
1145         u32 type, qp_id;
1146
1147         while (QM_AEQE_PHASE(aeqe) == qm->status.aeqc_phase) {
1148                 type = le32_to_cpu(aeqe->dw0) >> QM_AEQE_TYPE_SHIFT;
1149                 qp_id = le32_to_cpu(aeqe->dw0) & QM_AEQE_CQN_MASK;
1150
1151                 switch (type) {
1152                 case QM_EQ_OVERFLOW:
1153                         dev_err(&qm->pdev->dev, "eq overflow, reset function\n");
1154                         qm_reset_function(qm);
1155                         return IRQ_HANDLED;
1156                 case QM_CQ_OVERFLOW:
1157                         dev_err(&qm->pdev->dev, "cq overflow, stop qp(%u)\n",
1158                                 qp_id);
1159                         fallthrough;
1160                 case QM_CQE_ERROR:
1161                         qm_disable_qp(qm, qp_id);
1162                         break;
1163                 default:
1164                         dev_err(&qm->pdev->dev, "unknown error type %u\n",
1165                                 type);
1166                         break;
1167                 }
1168
1169                 if (qm->status.aeq_head == aeq_depth - 1) {
1170                         qm->status.aeqc_phase = !qm->status.aeqc_phase;
1171                         aeqe = qm->aeqe;
1172                         qm->status.aeq_head = 0;
1173                 } else {
1174                         aeqe++;
1175                         qm->status.aeq_head++;
1176                 }
1177         }
1178
1179         qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0);
1180
1181         return IRQ_HANDLED;
1182 }
1183
1184 static irqreturn_t qm_aeq_irq(int irq, void *data)
1185 {
1186         struct hisi_qm *qm = data;
1187
1188         atomic64_inc(&qm->debug.dfx.aeq_irq_cnt);
1189         if (!readl(qm->io_base + QM_VF_AEQ_INT_SOURCE))
1190                 return IRQ_NONE;
1191
1192         return IRQ_WAKE_THREAD;
1193 }
1194
1195 static void qm_init_qp_status(struct hisi_qp *qp)
1196 {
1197         struct hisi_qp_status *qp_status = &qp->qp_status;
1198
1199         qp_status->sq_tail = 0;
1200         qp_status->cq_head = 0;
1201         qp_status->cqc_phase = true;
1202         atomic_set(&qp_status->used, 0);
1203 }
1204
1205 static void qm_init_prefetch(struct hisi_qm *qm)
1206 {
1207         struct device *dev = &qm->pdev->dev;
1208         u32 page_type = 0x0;
1209
1210         if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
1211                 return;
1212
1213         switch (PAGE_SIZE) {
1214         case SZ_4K:
1215                 page_type = 0x0;
1216                 break;
1217         case SZ_16K:
1218                 page_type = 0x1;
1219                 break;
1220         case SZ_64K:
1221                 page_type = 0x2;
1222                 break;
1223         default:
1224                 dev_err(dev, "system page size is not support: %lu, default set to 4KB",
1225                         PAGE_SIZE);
1226         }
1227
1228         writel(page_type, qm->io_base + QM_PAGE_SIZE);
1229 }
1230
1231 /*
1232  * acc_shaper_para_calc() Get the IR value by the qos formula, the return value
1233  * is the expected qos calculated.
1234  * the formula:
1235  * IR = X Mbps if ir = 1 means IR = 100 Mbps, if ir = 10000 means = 10Gbps
1236  *
1237  *              IR_b * (2 ^ IR_u) * 8000
1238  * IR(Mbps) = -------------------------
1239  *                Tick * (2 ^ IR_s)
1240  */
1241 static u32 acc_shaper_para_calc(u64 cir_b, u64 cir_u, u64 cir_s)
1242 {
1243         return ((cir_b * QM_QOS_DIVISOR_CLK) * (1 << cir_u)) /
1244                                         (QM_QOS_TICK * (1 << cir_s));
1245 }
1246
1247 static u32 acc_shaper_calc_cbs_s(u32 ir)
1248 {
1249         int table_size = ARRAY_SIZE(shaper_cbs_s);
1250         int i;
1251
1252         for (i = 0; i < table_size; i++) {
1253                 if (ir >= shaper_cbs_s[i].start && ir <= shaper_cbs_s[i].end)
1254                         return shaper_cbs_s[i].val;
1255         }
1256
1257         return QM_SHAPER_MIN_CBS_S;
1258 }
1259
1260 static u32 acc_shaper_calc_cir_s(u32 ir)
1261 {
1262         int table_size = ARRAY_SIZE(shaper_cir_s);
1263         int i;
1264
1265         for (i = 0; i < table_size; i++) {
1266                 if (ir >= shaper_cir_s[i].start && ir <= shaper_cir_s[i].end)
1267                         return shaper_cir_s[i].val;
1268         }
1269
1270         return 0;
1271 }
1272
1273 static int qm_get_shaper_para(u32 ir, struct qm_shaper_factor *factor)
1274 {
1275         u32 cir_b, cir_u, cir_s, ir_calc;
1276         u32 error_rate;
1277
1278         factor->cbs_s = acc_shaper_calc_cbs_s(ir);
1279         cir_s = acc_shaper_calc_cir_s(ir);
1280
1281         for (cir_b = QM_QOS_MIN_CIR_B; cir_b <= QM_QOS_MAX_CIR_B; cir_b++) {
1282                 for (cir_u = 0; cir_u <= QM_QOS_MAX_CIR_U; cir_u++) {
1283                         ir_calc = acc_shaper_para_calc(cir_b, cir_u, cir_s);
1284
1285                         error_rate = QM_QOS_EXPAND_RATE * (u32)abs(ir_calc - ir) / ir;
1286                         if (error_rate <= QM_QOS_MIN_ERROR_RATE) {
1287                                 factor->cir_b = cir_b;
1288                                 factor->cir_u = cir_u;
1289                                 factor->cir_s = cir_s;
1290                                 return 0;
1291                         }
1292                 }
1293         }
1294
1295         return -EINVAL;
1296 }
1297
1298 static void qm_vft_data_cfg(struct hisi_qm *qm, enum vft_type type, u32 base,
1299                             u32 number, struct qm_shaper_factor *factor)
1300 {
1301         u64 tmp = 0;
1302
1303         if (number > 0) {
1304                 switch (type) {
1305                 case SQC_VFT:
1306                         if (qm->ver == QM_HW_V1) {
1307                                 tmp = QM_SQC_VFT_BUF_SIZE       |
1308                                       QM_SQC_VFT_SQC_SIZE       |
1309                                       QM_SQC_VFT_INDEX_NUMBER   |
1310                                       QM_SQC_VFT_VALID          |
1311                                       (u64)base << QM_SQC_VFT_START_SQN_SHIFT;
1312                         } else {
1313                                 tmp = (u64)base << QM_SQC_VFT_START_SQN_SHIFT |
1314                                       QM_SQC_VFT_VALID |
1315                                       (u64)(number - 1) << QM_SQC_VFT_SQN_SHIFT;
1316                         }
1317                         break;
1318                 case CQC_VFT:
1319                         if (qm->ver == QM_HW_V1) {
1320                                 tmp = QM_CQC_VFT_BUF_SIZE       |
1321                                       QM_CQC_VFT_SQC_SIZE       |
1322                                       QM_CQC_VFT_INDEX_NUMBER   |
1323                                       QM_CQC_VFT_VALID;
1324                         } else {
1325                                 tmp = QM_CQC_VFT_VALID;
1326                         }
1327                         break;
1328                 case SHAPER_VFT:
1329                         if (factor) {
1330                                 tmp = factor->cir_b |
1331                                 (factor->cir_u << QM_SHAPER_FACTOR_CIR_U_SHIFT) |
1332                                 (factor->cir_s << QM_SHAPER_FACTOR_CIR_S_SHIFT) |
1333                                 (QM_SHAPER_CBS_B << QM_SHAPER_FACTOR_CBS_B_SHIFT) |
1334                                 (factor->cbs_s << QM_SHAPER_FACTOR_CBS_S_SHIFT);
1335                         }
1336                         break;
1337                 }
1338         }
1339
1340         writel(lower_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_L);
1341         writel(upper_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_H);
1342 }
1343
1344 static int qm_set_vft_common(struct hisi_qm *qm, enum vft_type type,
1345                              u32 fun_num, u32 base, u32 number)
1346 {
1347         struct qm_shaper_factor *factor = NULL;
1348         unsigned int val;
1349         int ret;
1350
1351         if (type == SHAPER_VFT && test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps))
1352                 factor = &qm->factor[fun_num];
1353
1354         ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
1355                                          val & BIT(0), POLL_PERIOD,
1356                                          POLL_TIMEOUT);
1357         if (ret)
1358                 return ret;
1359
1360         writel(0x0, qm->io_base + QM_VFT_CFG_OP_WR);
1361         writel(type, qm->io_base + QM_VFT_CFG_TYPE);
1362         if (type == SHAPER_VFT)
1363                 fun_num |= base << QM_SHAPER_VFT_OFFSET;
1364
1365         writel(fun_num, qm->io_base + QM_VFT_CFG);
1366
1367         qm_vft_data_cfg(qm, type, base, number, factor);
1368
1369         writel(0x0, qm->io_base + QM_VFT_CFG_RDY);
1370         writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);
1371
1372         return readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
1373                                           val & BIT(0), POLL_PERIOD,
1374                                           POLL_TIMEOUT);
1375 }
1376
1377 static int qm_shaper_init_vft(struct hisi_qm *qm, u32 fun_num)
1378 {
1379         u32 qos = qm->factor[fun_num].func_qos;
1380         int ret, i;
1381
1382         ret = qm_get_shaper_para(qos * QM_QOS_RATE, &qm->factor[fun_num]);
1383         if (ret) {
1384                 dev_err(&qm->pdev->dev, "failed to calculate shaper parameter!\n");
1385                 return ret;
1386         }
1387         writel(qm->type_rate, qm->io_base + QM_SHAPER_CFG);
1388         for (i = ALG_TYPE_0; i <= ALG_TYPE_1; i++) {
1389                 /* The base number of queue reuse for different alg type */
1390                 ret = qm_set_vft_common(qm, SHAPER_VFT, fun_num, i, 1);
1391                 if (ret)
1392                         return ret;
1393         }
1394
1395         return 0;
1396 }
1397
1398 /* The config should be conducted after qm_dev_mem_reset() */
1399 static int qm_set_sqc_cqc_vft(struct hisi_qm *qm, u32 fun_num, u32 base,
1400                               u32 number)
1401 {
1402         int ret, i;
1403
1404         for (i = SQC_VFT; i <= CQC_VFT; i++) {
1405                 ret = qm_set_vft_common(qm, i, fun_num, base, number);
1406                 if (ret)
1407                         return ret;
1408         }
1409
1410         /* init default shaper qos val */
1411         if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps)) {
1412                 ret = qm_shaper_init_vft(qm, fun_num);
1413                 if (ret)
1414                         goto back_sqc_cqc;
1415         }
1416
1417         return 0;
1418 back_sqc_cqc:
1419         for (i = SQC_VFT; i <= CQC_VFT; i++)
1420                 qm_set_vft_common(qm, i, fun_num, 0, 0);
1421
1422         return ret;
1423 }
1424
1425 static int qm_get_vft_v2(struct hisi_qm *qm, u32 *base, u32 *number)
1426 {
1427         u64 sqc_vft;
1428         int ret;
1429
1430         ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1);
1431         if (ret)
1432                 return ret;
1433
1434         sqc_vft = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
1435                   ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32);
1436         *base = QM_SQC_VFT_BASE_MASK_V2 & (sqc_vft >> QM_SQC_VFT_BASE_SHIFT_V2);
1437         *number = (QM_SQC_VFT_NUM_MASK_v2 &
1438                    (sqc_vft >> QM_SQC_VFT_NUM_SHIFT_V2)) + 1;
1439
1440         return 0;
1441 }
1442
1443 static int qm_get_vf_qp_num(struct hisi_qm *qm, u32 fun_num)
1444 {
1445         u32 remain_q_num, vfq_num;
1446         u32 num_vfs = qm->vfs_num;
1447
1448         vfq_num = (qm->ctrl_qp_num - qm->qp_num) / num_vfs;
1449         if (vfq_num >= qm->max_qp_num)
1450                 return qm->max_qp_num;
1451
1452         remain_q_num = (qm->ctrl_qp_num - qm->qp_num) % num_vfs;
1453         if (vfq_num + remain_q_num <= qm->max_qp_num)
1454                 return fun_num == num_vfs ? vfq_num + remain_q_num : vfq_num;
1455
1456         /*
1457          * if vfq_num + remain_q_num > max_qp_num, the last VFs,
1458          * each with one more queue.
1459          */
1460         return fun_num + remain_q_num > num_vfs ? vfq_num + 1 : vfq_num;
1461 }
1462
1463 static struct hisi_qm *file_to_qm(struct debugfs_file *file)
1464 {
1465         struct qm_debug *debug = file->debug;
1466
1467         return container_of(debug, struct hisi_qm, debug);
1468 }
1469
1470 static u32 current_q_read(struct hisi_qm *qm)
1471 {
1472         return readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) >> QM_DFX_QN_SHIFT;
1473 }
1474
1475 static int current_q_write(struct hisi_qm *qm, u32 val)
1476 {
1477         u32 tmp;
1478
1479         if (val >= qm->debug.curr_qm_qp_num)
1480                 return -EINVAL;
1481
1482         tmp = val << QM_DFX_QN_SHIFT |
1483               (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_FUN_MASK);
1484         writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
1485
1486         tmp = val << QM_DFX_QN_SHIFT |
1487               (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_FUN_MASK);
1488         writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
1489
1490         return 0;
1491 }
1492
1493 static u32 clear_enable_read(struct hisi_qm *qm)
1494 {
1495         return readl(qm->io_base + QM_DFX_CNT_CLR_CE);
1496 }
1497
1498 /* rd_clr_ctrl 1 enable read clear, otherwise 0 disable it */
1499 static int clear_enable_write(struct hisi_qm *qm, u32 rd_clr_ctrl)
1500 {
1501         if (rd_clr_ctrl > 1)
1502                 return -EINVAL;
1503
1504         writel(rd_clr_ctrl, qm->io_base + QM_DFX_CNT_CLR_CE);
1505
1506         return 0;
1507 }
1508
1509 static u32 current_qm_read(struct hisi_qm *qm)
1510 {
1511         return readl(qm->io_base + QM_DFX_MB_CNT_VF);
1512 }
1513
1514 static int current_qm_write(struct hisi_qm *qm, u32 val)
1515 {
1516         u32 tmp;
1517
1518         if (val > qm->vfs_num)
1519                 return -EINVAL;
1520
1521         /* According PF or VF Dev ID to calculation curr_qm_qp_num and store */
1522         if (!val)
1523                 qm->debug.curr_qm_qp_num = qm->qp_num;
1524         else
1525                 qm->debug.curr_qm_qp_num = qm_get_vf_qp_num(qm, val);
1526
1527         writel(val, qm->io_base + QM_DFX_MB_CNT_VF);
1528         writel(val, qm->io_base + QM_DFX_DB_CNT_VF);
1529
1530         tmp = val |
1531               (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK);
1532         writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
1533
1534         tmp = val |
1535               (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK);
1536         writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
1537
1538         return 0;
1539 }
1540
1541 static ssize_t qm_debug_read(struct file *filp, char __user *buf,
1542                              size_t count, loff_t *pos)
1543 {
1544         struct debugfs_file *file = filp->private_data;
1545         enum qm_debug_file index = file->index;
1546         struct hisi_qm *qm = file_to_qm(file);
1547         char tbuf[QM_DBG_TMP_BUF_LEN];
1548         u32 val;
1549         int ret;
1550
1551         ret = hisi_qm_get_dfx_access(qm);
1552         if (ret)
1553                 return ret;
1554
1555         mutex_lock(&file->lock);
1556         switch (index) {
1557         case CURRENT_QM:
1558                 val = current_qm_read(qm);
1559                 break;
1560         case CURRENT_Q:
1561                 val = current_q_read(qm);
1562                 break;
1563         case CLEAR_ENABLE:
1564                 val = clear_enable_read(qm);
1565                 break;
1566         default:
1567                 goto err_input;
1568         }
1569         mutex_unlock(&file->lock);
1570
1571         hisi_qm_put_dfx_access(qm);
1572         ret = scnprintf(tbuf, QM_DBG_TMP_BUF_LEN, "%u\n", val);
1573         return simple_read_from_buffer(buf, count, pos, tbuf, ret);
1574
1575 err_input:
1576         mutex_unlock(&file->lock);
1577         hisi_qm_put_dfx_access(qm);
1578         return -EINVAL;
1579 }
1580
1581 static ssize_t qm_debug_write(struct file *filp, const char __user *buf,
1582                               size_t count, loff_t *pos)
1583 {
1584         struct debugfs_file *file = filp->private_data;
1585         enum qm_debug_file index = file->index;
1586         struct hisi_qm *qm = file_to_qm(file);
1587         unsigned long val;
1588         char tbuf[QM_DBG_TMP_BUF_LEN];
1589         int len, ret;
1590
1591         if (*pos != 0)
1592                 return 0;
1593
1594         if (count >= QM_DBG_TMP_BUF_LEN)
1595                 return -ENOSPC;
1596
1597         len = simple_write_to_buffer(tbuf, QM_DBG_TMP_BUF_LEN - 1, pos, buf,
1598                                      count);
1599         if (len < 0)
1600                 return len;
1601
1602         tbuf[len] = '\0';
1603         if (kstrtoul(tbuf, 0, &val))
1604                 return -EFAULT;
1605
1606         ret = hisi_qm_get_dfx_access(qm);
1607         if (ret)
1608                 return ret;
1609
1610         mutex_lock(&file->lock);
1611         switch (index) {
1612         case CURRENT_QM:
1613                 ret = current_qm_write(qm, val);
1614                 break;
1615         case CURRENT_Q:
1616                 ret = current_q_write(qm, val);
1617                 break;
1618         case CLEAR_ENABLE:
1619                 ret = clear_enable_write(qm, val);
1620                 break;
1621         default:
1622                 ret = -EINVAL;
1623         }
1624         mutex_unlock(&file->lock);
1625
1626         hisi_qm_put_dfx_access(qm);
1627
1628         if (ret)
1629                 return ret;
1630
1631         return count;
1632 }
1633
1634 static const struct file_operations qm_debug_fops = {
1635         .owner = THIS_MODULE,
1636         .open = simple_open,
1637         .read = qm_debug_read,
1638         .write = qm_debug_write,
1639 };
1640
1641 #define CNT_CYC_REGS_NUM                10
1642 static const struct debugfs_reg32 qm_dfx_regs[] = {
1643         /* XXX_CNT are reading clear register */
1644         {"QM_ECC_1BIT_CNT               ",  0x104000ull},
1645         {"QM_ECC_MBIT_CNT               ",  0x104008ull},
1646         {"QM_DFX_MB_CNT                 ",  0x104018ull},
1647         {"QM_DFX_DB_CNT                 ",  0x104028ull},
1648         {"QM_DFX_SQE_CNT                ",  0x104038ull},
1649         {"QM_DFX_CQE_CNT                ",  0x104048ull},
1650         {"QM_DFX_SEND_SQE_TO_ACC_CNT    ",  0x104050ull},
1651         {"QM_DFX_WB_SQE_FROM_ACC_CNT    ",  0x104058ull},
1652         {"QM_DFX_ACC_FINISH_CNT         ",  0x104060ull},
1653         {"QM_DFX_CQE_ERR_CNT            ",  0x1040b4ull},
1654         {"QM_DFX_FUNS_ACTIVE_ST         ",  0x200ull},
1655         {"QM_ECC_1BIT_INF               ",  0x104004ull},
1656         {"QM_ECC_MBIT_INF               ",  0x10400cull},
1657         {"QM_DFX_ACC_RDY_VLD0           ",  0x1040a0ull},
1658         {"QM_DFX_ACC_RDY_VLD1           ",  0x1040a4ull},
1659         {"QM_DFX_AXI_RDY_VLD            ",  0x1040a8ull},
1660         {"QM_DFX_FF_ST0                 ",  0x1040c8ull},
1661         {"QM_DFX_FF_ST1                 ",  0x1040ccull},
1662         {"QM_DFX_FF_ST2                 ",  0x1040d0ull},
1663         {"QM_DFX_FF_ST3                 ",  0x1040d4ull},
1664         {"QM_DFX_FF_ST4                 ",  0x1040d8ull},
1665         {"QM_DFX_FF_ST5                 ",  0x1040dcull},
1666         {"QM_DFX_FF_ST6                 ",  0x1040e0ull},
1667         {"QM_IN_IDLE_ST                 ",  0x1040e4ull},
1668 };
1669
1670 static const struct debugfs_reg32 qm_vf_dfx_regs[] = {
1671         {"QM_DFX_FUNS_ACTIVE_ST         ",  0x200ull},
1672 };
1673
1674 /**
1675  * hisi_qm_regs_dump() - Dump registers's value.
1676  * @s: debugfs file handle.
1677  * @regset: accelerator registers information.
1678  *
1679  * Dump accelerator registers.
1680  */
1681 void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset)
1682 {
1683         struct pci_dev *pdev = to_pci_dev(regset->dev);
1684         struct hisi_qm *qm = pci_get_drvdata(pdev);
1685         const struct debugfs_reg32 *regs = regset->regs;
1686         int regs_len = regset->nregs;
1687         int i, ret;
1688         u32 val;
1689
1690         ret = hisi_qm_get_dfx_access(qm);
1691         if (ret)
1692                 return;
1693
1694         for (i = 0; i < regs_len; i++) {
1695                 val = readl(regset->base + regs[i].offset);
1696                 seq_printf(s, "%s= 0x%08x\n", regs[i].name, val);
1697         }
1698
1699         hisi_qm_put_dfx_access(qm);
1700 }
1701 EXPORT_SYMBOL_GPL(hisi_qm_regs_dump);
1702
1703 static int qm_regs_show(struct seq_file *s, void *unused)
1704 {
1705         struct hisi_qm *qm = s->private;
1706         struct debugfs_regset32 regset;
1707
1708         if (qm->fun_type == QM_HW_PF) {
1709                 regset.regs = qm_dfx_regs;
1710                 regset.nregs = ARRAY_SIZE(qm_dfx_regs);
1711         } else {
1712                 regset.regs = qm_vf_dfx_regs;
1713                 regset.nregs = ARRAY_SIZE(qm_vf_dfx_regs);
1714         }
1715
1716         regset.base = qm->io_base;
1717         regset.dev = &qm->pdev->dev;
1718
1719         hisi_qm_regs_dump(s, &regset);
1720
1721         return 0;
1722 }
1723
1724 DEFINE_SHOW_ATTRIBUTE(qm_regs);
1725
1726 static struct dfx_diff_registers *dfx_regs_init(struct hisi_qm *qm,
1727         const struct dfx_diff_registers *cregs, int reg_len)
1728 {
1729         struct dfx_diff_registers *diff_regs;
1730         u32 j, base_offset;
1731         int i;
1732
1733         diff_regs = kcalloc(reg_len, sizeof(*diff_regs), GFP_KERNEL);
1734         if (!diff_regs)
1735                 return ERR_PTR(-ENOMEM);
1736
1737         for (i = 0; i < reg_len; i++) {
1738                 if (!cregs[i].reg_len)
1739                         continue;
1740
1741                 diff_regs[i].reg_offset = cregs[i].reg_offset;
1742                 diff_regs[i].reg_len = cregs[i].reg_len;
1743                 diff_regs[i].regs = kcalloc(QM_DFX_REGS_LEN, cregs[i].reg_len,
1744                                          GFP_KERNEL);
1745                 if (!diff_regs[i].regs)
1746                         goto alloc_error;
1747
1748                 for (j = 0; j < diff_regs[i].reg_len; j++) {
1749                         base_offset = diff_regs[i].reg_offset +
1750                                         j * QM_DFX_REGS_LEN;
1751                         diff_regs[i].regs[j] = readl(qm->io_base + base_offset);
1752                 }
1753         }
1754
1755         return diff_regs;
1756
1757 alloc_error:
1758         while (i > 0) {
1759                 i--;
1760                 kfree(diff_regs[i].regs);
1761         }
1762         kfree(diff_regs);
1763         return ERR_PTR(-ENOMEM);
1764 }
1765
1766 static void dfx_regs_uninit(struct hisi_qm *qm,
1767                 struct dfx_diff_registers *dregs, int reg_len)
1768 {
1769         int i;
1770
1771         /* Setting the pointer is NULL to prevent double free */
1772         for (i = 0; i < reg_len; i++) {
1773                 kfree(dregs[i].regs);
1774                 dregs[i].regs = NULL;
1775         }
1776         kfree(dregs);
1777         dregs = NULL;
1778 }
1779
1780 /**
1781  * hisi_qm_diff_regs_init() - Allocate memory for registers.
1782  * @qm: device qm handle.
1783  * @dregs: diff registers handle.
1784  * @reg_len: diff registers region length.
1785  */
1786 int hisi_qm_diff_regs_init(struct hisi_qm *qm,
1787                 struct dfx_diff_registers *dregs, int reg_len)
1788 {
1789         if (!qm || !dregs || reg_len <= 0)
1790                 return -EINVAL;
1791
1792         if (qm->fun_type != QM_HW_PF)
1793                 return 0;
1794
1795         qm->debug.qm_diff_regs = dfx_regs_init(qm, qm_diff_regs,
1796                                                 ARRAY_SIZE(qm_diff_regs));
1797         if (IS_ERR(qm->debug.qm_diff_regs))
1798                 return PTR_ERR(qm->debug.qm_diff_regs);
1799
1800         qm->debug.acc_diff_regs = dfx_regs_init(qm, dregs, reg_len);
1801         if (IS_ERR(qm->debug.acc_diff_regs)) {
1802                 dfx_regs_uninit(qm, qm->debug.qm_diff_regs,
1803                                 ARRAY_SIZE(qm_diff_regs));
1804                 return PTR_ERR(qm->debug.acc_diff_regs);
1805         }
1806
1807         return 0;
1808 }
1809 EXPORT_SYMBOL_GPL(hisi_qm_diff_regs_init);
1810
1811 /**
1812  * hisi_qm_diff_regs_uninit() - Free memory for registers.
1813  * @qm: device qm handle.
1814  * @reg_len: diff registers region length.
1815  */
1816 void hisi_qm_diff_regs_uninit(struct hisi_qm *qm, int reg_len)
1817 {
1818         if (!qm  || reg_len <= 0 || qm->fun_type != QM_HW_PF)
1819                 return;
1820
1821         dfx_regs_uninit(qm, qm->debug.acc_diff_regs, reg_len);
1822         dfx_regs_uninit(qm, qm->debug.qm_diff_regs, ARRAY_SIZE(qm_diff_regs));
1823 }
1824 EXPORT_SYMBOL_GPL(hisi_qm_diff_regs_uninit);
1825
1826 /**
1827  * hisi_qm_acc_diff_regs_dump() - Dump registers's value.
1828  * @qm: device qm handle.
1829  * @s: Debugfs file handle.
1830  * @dregs: diff registers handle.
1831  * @regs_len: diff registers region length.
1832  */
1833 void hisi_qm_acc_diff_regs_dump(struct hisi_qm *qm, struct seq_file *s,
1834         struct dfx_diff_registers *dregs, int regs_len)
1835 {
1836         u32 j, val, base_offset;
1837         int i, ret;
1838
1839         if (!qm || !s || !dregs || regs_len <= 0)
1840                 return;
1841
1842         ret = hisi_qm_get_dfx_access(qm);
1843         if (ret)
1844                 return;
1845
1846         down_read(&qm->qps_lock);
1847         for (i = 0; i < regs_len; i++) {
1848                 if (!dregs[i].reg_len)
1849                         continue;
1850
1851                 for (j = 0; j < dregs[i].reg_len; j++) {
1852                         base_offset = dregs[i].reg_offset + j * QM_DFX_REGS_LEN;
1853                         val = readl(qm->io_base + base_offset);
1854                         if (val != dregs[i].regs[j])
1855                                 seq_printf(s, "0x%08x = 0x%08x ---> 0x%08x\n",
1856                                            base_offset, dregs[i].regs[j], val);
1857                 }
1858         }
1859         up_read(&qm->qps_lock);
1860
1861         hisi_qm_put_dfx_access(qm);
1862 }
1863 EXPORT_SYMBOL_GPL(hisi_qm_acc_diff_regs_dump);
1864
1865 static int qm_diff_regs_show(struct seq_file *s, void *unused)
1866 {
1867         struct hisi_qm *qm = s->private;
1868
1869         hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.qm_diff_regs,
1870                                         ARRAY_SIZE(qm_diff_regs));
1871
1872         return 0;
1873 }
1874 DEFINE_SHOW_ATTRIBUTE(qm_diff_regs);
1875
1876 static ssize_t qm_cmd_read(struct file *filp, char __user *buffer,
1877                            size_t count, loff_t *pos)
1878 {
1879         char buf[QM_DBG_READ_LEN];
1880         int len;
1881
1882         len = scnprintf(buf, QM_DBG_READ_LEN, "%s\n",
1883                         "Please echo help to cmd to get help information");
1884
1885         return simple_read_from_buffer(buffer, count, pos, buf, len);
1886 }
1887
1888 static void *qm_ctx_alloc(struct hisi_qm *qm, size_t ctx_size,
1889                           dma_addr_t *dma_addr)
1890 {
1891         struct device *dev = &qm->pdev->dev;
1892         void *ctx_addr;
1893
1894         ctx_addr = kzalloc(ctx_size, GFP_KERNEL);
1895         if (!ctx_addr)
1896                 return ERR_PTR(-ENOMEM);
1897
1898         *dma_addr = dma_map_single(dev, ctx_addr, ctx_size, DMA_FROM_DEVICE);
1899         if (dma_mapping_error(dev, *dma_addr)) {
1900                 dev_err(dev, "DMA mapping error!\n");
1901                 kfree(ctx_addr);
1902                 return ERR_PTR(-ENOMEM);
1903         }
1904
1905         return ctx_addr;
1906 }
1907
1908 static void qm_ctx_free(struct hisi_qm *qm, size_t ctx_size,
1909                         const void *ctx_addr, dma_addr_t *dma_addr)
1910 {
1911         struct device *dev = &qm->pdev->dev;
1912
1913         dma_unmap_single(dev, *dma_addr, ctx_size, DMA_FROM_DEVICE);
1914         kfree(ctx_addr);
1915 }
1916
1917 static void dump_show(struct hisi_qm *qm, void *info,
1918                      unsigned int info_size, char *info_name)
1919 {
1920         struct device *dev = &qm->pdev->dev;
1921         u8 *info_curr = info;
1922         u32 i;
1923 #define BYTE_PER_DW     4
1924
1925         dev_info(dev, "%s DUMP\n", info_name);
1926         for (i = 0; i < info_size; i += BYTE_PER_DW, info_curr += BYTE_PER_DW) {
1927                 pr_info("DW%u: %02X%02X %02X%02X\n", i / BYTE_PER_DW,
1928                         *(info_curr + 3), *(info_curr + 2), *(info_curr + 1), *(info_curr));
1929         }
1930 }
1931
1932 static int qm_dump_sqc_raw(struct hisi_qm *qm, dma_addr_t dma_addr, u16 qp_id)
1933 {
1934         return hisi_qm_mb(qm, QM_MB_CMD_SQC, dma_addr, qp_id, 1);
1935 }
1936
1937 static int qm_dump_cqc_raw(struct hisi_qm *qm, dma_addr_t dma_addr, u16 qp_id)
1938 {
1939         return hisi_qm_mb(qm, QM_MB_CMD_CQC, dma_addr, qp_id, 1);
1940 }
1941
1942 static int qm_sqc_dump(struct hisi_qm *qm, const char *s)
1943 {
1944         struct device *dev = &qm->pdev->dev;
1945         struct qm_sqc *sqc, *sqc_curr;
1946         dma_addr_t sqc_dma;
1947         u32 qp_id;
1948         int ret;
1949
1950         if (!s)
1951                 return -EINVAL;
1952
1953         ret = kstrtou32(s, 0, &qp_id);
1954         if (ret || qp_id >= qm->qp_num) {
1955                 dev_err(dev, "Please input qp num (0-%u)", qm->qp_num - 1);
1956                 return -EINVAL;
1957         }
1958
1959         sqc = qm_ctx_alloc(qm, sizeof(*sqc), &sqc_dma);
1960         if (IS_ERR(sqc))
1961                 return PTR_ERR(sqc);
1962
1963         ret = qm_dump_sqc_raw(qm, sqc_dma, qp_id);
1964         if (ret) {
1965                 down_read(&qm->qps_lock);
1966                 if (qm->sqc) {
1967                         sqc_curr = qm->sqc + qp_id;
1968
1969                         dump_show(qm, sqc_curr, sizeof(*sqc), "SOFT SQC");
1970                 }
1971                 up_read(&qm->qps_lock);
1972
1973                 goto free_ctx;
1974         }
1975
1976         dump_show(qm, sqc, sizeof(*sqc), "SQC");
1977
1978 free_ctx:
1979         qm_ctx_free(qm, sizeof(*sqc), sqc, &sqc_dma);
1980         return 0;
1981 }
1982
1983 static int qm_cqc_dump(struct hisi_qm *qm, const char *s)
1984 {
1985         struct device *dev = &qm->pdev->dev;
1986         struct qm_cqc *cqc, *cqc_curr;
1987         dma_addr_t cqc_dma;
1988         u32 qp_id;
1989         int ret;
1990
1991         if (!s)
1992                 return -EINVAL;
1993
1994         ret = kstrtou32(s, 0, &qp_id);
1995         if (ret || qp_id >= qm->qp_num) {
1996                 dev_err(dev, "Please input qp num (0-%u)", qm->qp_num - 1);
1997                 return -EINVAL;
1998         }
1999
2000         cqc = qm_ctx_alloc(qm, sizeof(*cqc), &cqc_dma);
2001         if (IS_ERR(cqc))
2002                 return PTR_ERR(cqc);
2003
2004         ret = qm_dump_cqc_raw(qm, cqc_dma, qp_id);
2005         if (ret) {
2006                 down_read(&qm->qps_lock);
2007                 if (qm->cqc) {
2008                         cqc_curr = qm->cqc + qp_id;
2009
2010                         dump_show(qm, cqc_curr, sizeof(*cqc), "SOFT CQC");
2011                 }
2012                 up_read(&qm->qps_lock);
2013
2014                 goto free_ctx;
2015         }
2016
2017         dump_show(qm, cqc, sizeof(*cqc), "CQC");
2018
2019 free_ctx:
2020         qm_ctx_free(qm, sizeof(*cqc), cqc, &cqc_dma);
2021         return 0;
2022 }
2023
2024 static int qm_eqc_aeqc_dump(struct hisi_qm *qm, char *s, size_t size,
2025                             int cmd, char *name)
2026 {
2027         struct device *dev = &qm->pdev->dev;
2028         dma_addr_t xeqc_dma;
2029         void *xeqc;
2030         int ret;
2031
2032         if (strsep(&s, " ")) {
2033                 dev_err(dev, "Please do not input extra characters!\n");
2034                 return -EINVAL;
2035         }
2036
2037         xeqc = qm_ctx_alloc(qm, size, &xeqc_dma);
2038         if (IS_ERR(xeqc))
2039                 return PTR_ERR(xeqc);
2040
2041         ret = hisi_qm_mb(qm, cmd, xeqc_dma, 0, 1);
2042         if (ret)
2043                 goto err_free_ctx;
2044
2045         dump_show(qm, xeqc, size, name);
2046
2047 err_free_ctx:
2048         qm_ctx_free(qm, size, xeqc, &xeqc_dma);
2049         return ret;
2050 }
2051
2052 static int q_dump_param_parse(struct hisi_qm *qm, char *s,
2053                               u32 *e_id, u32 *q_id, u16 q_depth)
2054 {
2055         struct device *dev = &qm->pdev->dev;
2056         unsigned int qp_num = qm->qp_num;
2057         char *presult;
2058         int ret;
2059
2060         presult = strsep(&s, " ");
2061         if (!presult) {
2062                 dev_err(dev, "Please input qp number!\n");
2063                 return -EINVAL;
2064         }
2065
2066         ret = kstrtou32(presult, 0, q_id);
2067         if (ret || *q_id >= qp_num) {
2068                 dev_err(dev, "Please input qp num (0-%u)", qp_num - 1);
2069                 return -EINVAL;
2070         }
2071
2072         presult = strsep(&s, " ");
2073         if (!presult) {
2074                 dev_err(dev, "Please input sqe number!\n");
2075                 return -EINVAL;
2076         }
2077
2078         ret = kstrtou32(presult, 0, e_id);
2079         if (ret || *e_id >= q_depth) {
2080                 dev_err(dev, "Please input sqe num (0-%u)", q_depth - 1);
2081                 return -EINVAL;
2082         }
2083
2084         if (strsep(&s, " ")) {
2085                 dev_err(dev, "Please do not input extra characters!\n");
2086                 return -EINVAL;
2087         }
2088
2089         return 0;
2090 }
2091
2092 static int qm_sq_dump(struct hisi_qm *qm, char *s)
2093 {
2094         u16 sq_depth = qm->qp_array->cq_depth;
2095         void *sqe, *sqe_curr;
2096         struct hisi_qp *qp;
2097         u32 qp_id, sqe_id;
2098         int ret;
2099
2100         ret = q_dump_param_parse(qm, s, &sqe_id, &qp_id, sq_depth);
2101         if (ret)
2102                 return ret;
2103
2104         sqe = kzalloc(qm->sqe_size * sq_depth, GFP_KERNEL);
2105         if (!sqe)
2106                 return -ENOMEM;
2107
2108         qp = &qm->qp_array[qp_id];
2109         memcpy(sqe, qp->sqe, qm->sqe_size * sq_depth);
2110         sqe_curr = sqe + (u32)(sqe_id * qm->sqe_size);
2111         memset(sqe_curr + qm->debug.sqe_mask_offset, QM_SQE_ADDR_MASK,
2112                qm->debug.sqe_mask_len);
2113
2114         dump_show(qm, sqe_curr, qm->sqe_size, "SQE");
2115
2116         kfree(sqe);
2117
2118         return 0;
2119 }
2120
2121 static int qm_cq_dump(struct hisi_qm *qm, char *s)
2122 {
2123         struct qm_cqe *cqe_curr;
2124         struct hisi_qp *qp;
2125         u32 qp_id, cqe_id;
2126         int ret;
2127
2128         ret = q_dump_param_parse(qm, s, &cqe_id, &qp_id, qm->qp_array->cq_depth);
2129         if (ret)
2130                 return ret;
2131
2132         qp = &qm->qp_array[qp_id];
2133         cqe_curr = qp->cqe + cqe_id;
2134         dump_show(qm, cqe_curr, sizeof(struct qm_cqe), "CQE");
2135
2136         return 0;
2137 }
2138
2139 static int qm_eq_aeq_dump(struct hisi_qm *qm, const char *s,
2140                           size_t size, char *name)
2141 {
2142         struct device *dev = &qm->pdev->dev;
2143         void *xeqe;
2144         u32 xeqe_id;
2145         int ret;
2146
2147         if (!s)
2148                 return -EINVAL;
2149
2150         ret = kstrtou32(s, 0, &xeqe_id);
2151         if (ret)
2152                 return -EINVAL;
2153
2154         if (!strcmp(name, "EQE") && xeqe_id >= qm->eq_depth) {
2155                 dev_err(dev, "Please input eqe num (0-%u)", qm->eq_depth - 1);
2156                 return -EINVAL;
2157         } else if (!strcmp(name, "AEQE") && xeqe_id >= qm->aeq_depth) {
2158                 dev_err(dev, "Please input aeqe num (0-%u)", qm->eq_depth - 1);
2159                 return -EINVAL;
2160         }
2161
2162         down_read(&qm->qps_lock);
2163
2164         if (qm->eqe && !strcmp(name, "EQE")) {
2165                 xeqe = qm->eqe + xeqe_id;
2166         } else if (qm->aeqe && !strcmp(name, "AEQE")) {
2167                 xeqe = qm->aeqe + xeqe_id;
2168         } else {
2169                 ret = -EINVAL;
2170                 goto err_unlock;
2171         }
2172
2173         dump_show(qm, xeqe, size, name);
2174
2175 err_unlock:
2176         up_read(&qm->qps_lock);
2177         return ret;
2178 }
2179
2180 static int qm_dbg_help(struct hisi_qm *qm, char *s)
2181 {
2182         struct device *dev = &qm->pdev->dev;
2183
2184         if (strsep(&s, " ")) {
2185                 dev_err(dev, "Please do not input extra characters!\n");
2186                 return -EINVAL;
2187         }
2188
2189         dev_info(dev, "available commands:\n");
2190         dev_info(dev, "sqc <num>\n");
2191         dev_info(dev, "cqc <num>\n");
2192         dev_info(dev, "eqc\n");
2193         dev_info(dev, "aeqc\n");
2194         dev_info(dev, "sq <num> <e>\n");
2195         dev_info(dev, "cq <num> <e>\n");
2196         dev_info(dev, "eq <e>\n");
2197         dev_info(dev, "aeq <e>\n");
2198
2199         return 0;
2200 }
2201
2202 static int qm_cmd_write_dump(struct hisi_qm *qm, const char *cmd_buf)
2203 {
2204         struct device *dev = &qm->pdev->dev;
2205         char *presult, *s, *s_tmp;
2206         int ret;
2207
2208         s = kstrdup(cmd_buf, GFP_KERNEL);
2209         if (!s)
2210                 return -ENOMEM;
2211
2212         s_tmp = s;
2213         presult = strsep(&s, " ");
2214         if (!presult) {
2215                 ret = -EINVAL;
2216                 goto err_buffer_free;
2217         }
2218
2219         if (!strcmp(presult, "sqc"))
2220                 ret = qm_sqc_dump(qm, s);
2221         else if (!strcmp(presult, "cqc"))
2222                 ret = qm_cqc_dump(qm, s);
2223         else if (!strcmp(presult, "eqc"))
2224                 ret = qm_eqc_aeqc_dump(qm, s, sizeof(struct qm_eqc),
2225                                        QM_MB_CMD_EQC, "EQC");
2226         else if (!strcmp(presult, "aeqc"))
2227                 ret = qm_eqc_aeqc_dump(qm, s, sizeof(struct qm_aeqc),
2228                                        QM_MB_CMD_AEQC, "AEQC");
2229         else if (!strcmp(presult, "sq"))
2230                 ret = qm_sq_dump(qm, s);
2231         else if (!strcmp(presult, "cq"))
2232                 ret = qm_cq_dump(qm, s);
2233         else if (!strcmp(presult, "eq"))
2234                 ret = qm_eq_aeq_dump(qm, s, sizeof(struct qm_eqe), "EQE");
2235         else if (!strcmp(presult, "aeq"))
2236                 ret = qm_eq_aeq_dump(qm, s, sizeof(struct qm_aeqe), "AEQE");
2237         else if (!strcmp(presult, "help"))
2238                 ret = qm_dbg_help(qm, s);
2239         else
2240                 ret = -EINVAL;
2241
2242         if (ret)
2243                 dev_info(dev, "Please echo help\n");
2244
2245 err_buffer_free:
2246         kfree(s_tmp);
2247
2248         return ret;
2249 }
2250
2251 static ssize_t qm_cmd_write(struct file *filp, const char __user *buffer,
2252                             size_t count, loff_t *pos)
2253 {
2254         struct hisi_qm *qm = filp->private_data;
2255         char *cmd_buf, *cmd_buf_tmp;
2256         int ret;
2257
2258         if (*pos)
2259                 return 0;
2260
2261         ret = hisi_qm_get_dfx_access(qm);
2262         if (ret)
2263                 return ret;
2264
2265         /* Judge if the instance is being reset. */
2266         if (unlikely(atomic_read(&qm->status.flags) == QM_STOP)) {
2267                 ret = 0;
2268                 goto put_dfx_access;
2269         }
2270
2271         if (count > QM_DBG_WRITE_LEN) {
2272                 ret = -ENOSPC;
2273                 goto put_dfx_access;
2274         }
2275
2276         cmd_buf = memdup_user_nul(buffer, count);
2277         if (IS_ERR(cmd_buf)) {
2278                 ret = PTR_ERR(cmd_buf);
2279                 goto put_dfx_access;
2280         }
2281
2282         cmd_buf_tmp = strchr(cmd_buf, '\n');
2283         if (cmd_buf_tmp) {
2284                 *cmd_buf_tmp = '\0';
2285                 count = cmd_buf_tmp - cmd_buf + 1;
2286         }
2287
2288         ret = qm_cmd_write_dump(qm, cmd_buf);
2289         if (ret) {
2290                 kfree(cmd_buf);
2291                 goto put_dfx_access;
2292         }
2293
2294         kfree(cmd_buf);
2295
2296         ret = count;
2297
2298 put_dfx_access:
2299         hisi_qm_put_dfx_access(qm);
2300         return ret;
2301 }
2302
2303 static const struct file_operations qm_cmd_fops = {
2304         .owner = THIS_MODULE,
2305         .open = simple_open,
2306         .read = qm_cmd_read,
2307         .write = qm_cmd_write,
2308 };
2309
2310 static void qm_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir,
2311                                    enum qm_debug_file index)
2312 {
2313         struct debugfs_file *file = qm->debug.files + index;
2314
2315         debugfs_create_file(qm_debug_file_name[index], 0600, dir, file,
2316                             &qm_debug_fops);
2317
2318         file->index = index;
2319         mutex_init(&file->lock);
2320         file->debug = &qm->debug;
2321 }
2322
2323 static void qm_hw_error_init_v1(struct hisi_qm *qm)
2324 {
2325         writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK);
2326 }
2327
2328 static void qm_hw_error_cfg(struct hisi_qm *qm)
2329 {
2330         struct hisi_qm_err_info *err_info = &qm->err_info;
2331
2332         qm->error_mask = err_info->nfe | err_info->ce | err_info->fe;
2333         /* clear QM hw residual error source */
2334         writel(qm->error_mask, qm->io_base + QM_ABNORMAL_INT_SOURCE);
2335
2336         /* configure error type */
2337         writel(err_info->ce, qm->io_base + QM_RAS_CE_ENABLE);
2338         writel(QM_RAS_CE_TIMES_PER_IRQ, qm->io_base + QM_RAS_CE_THRESHOLD);
2339         writel(err_info->nfe, qm->io_base + QM_RAS_NFE_ENABLE);
2340         writel(err_info->fe, qm->io_base + QM_RAS_FE_ENABLE);
2341 }
2342
2343 static void qm_hw_error_init_v2(struct hisi_qm *qm)
2344 {
2345         u32 irq_unmask;
2346
2347         qm_hw_error_cfg(qm);
2348
2349         irq_unmask = ~qm->error_mask;
2350         irq_unmask &= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
2351         writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK);
2352 }
2353
2354 static void qm_hw_error_uninit_v2(struct hisi_qm *qm)
2355 {
2356         u32 irq_mask = qm->error_mask;
2357
2358         irq_mask |= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
2359         writel(irq_mask, qm->io_base + QM_ABNORMAL_INT_MASK);
2360 }
2361
2362 static void qm_hw_error_init_v3(struct hisi_qm *qm)
2363 {
2364         u32 irq_unmask;
2365
2366         qm_hw_error_cfg(qm);
2367
2368         /* enable close master ooo when hardware error happened */
2369         writel(qm->err_info.qm_shutdown_mask, qm->io_base + QM_OOO_SHUTDOWN_SEL);
2370
2371         irq_unmask = ~qm->error_mask;
2372         irq_unmask &= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
2373         writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK);
2374 }
2375
2376 static void qm_hw_error_uninit_v3(struct hisi_qm *qm)
2377 {
2378         u32 irq_mask = qm->error_mask;
2379
2380         irq_mask |= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
2381         writel(irq_mask, qm->io_base + QM_ABNORMAL_INT_MASK);
2382
2383         /* disable close master ooo when hardware error happened */
2384         writel(0x0, qm->io_base + QM_OOO_SHUTDOWN_SEL);
2385 }
2386
2387 static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status)
2388 {
2389         const struct hisi_qm_hw_error *err;
2390         struct device *dev = &qm->pdev->dev;
2391         u32 reg_val, type, vf_num;
2392         int i;
2393
2394         for (i = 0; i < ARRAY_SIZE(qm_hw_error); i++) {
2395                 err = &qm_hw_error[i];
2396                 if (!(err->int_msk & error_status))
2397                         continue;
2398
2399                 dev_err(dev, "%s [error status=0x%x] found\n",
2400                         err->msg, err->int_msk);
2401
2402                 if (err->int_msk & QM_DB_TIMEOUT) {
2403                         reg_val = readl(qm->io_base + QM_ABNORMAL_INF01);
2404                         type = (reg_val & QM_DB_TIMEOUT_TYPE) >>
2405                                QM_DB_TIMEOUT_TYPE_SHIFT;
2406                         vf_num = reg_val & QM_DB_TIMEOUT_VF;
2407                         dev_err(dev, "qm %s doorbell timeout in function %u\n",
2408                                 qm_db_timeout[type], vf_num);
2409                 } else if (err->int_msk & QM_OF_FIFO_OF) {
2410                         reg_val = readl(qm->io_base + QM_ABNORMAL_INF00);
2411                         type = (reg_val & QM_FIFO_OVERFLOW_TYPE) >>
2412                                QM_FIFO_OVERFLOW_TYPE_SHIFT;
2413                         vf_num = reg_val & QM_FIFO_OVERFLOW_VF;
2414
2415                         if (type < ARRAY_SIZE(qm_fifo_overflow))
2416                                 dev_err(dev, "qm %s fifo overflow in function %u\n",
2417                                         qm_fifo_overflow[type], vf_num);
2418                         else
2419                                 dev_err(dev, "unknown error type\n");
2420                 }
2421         }
2422 }
2423
2424 static enum acc_err_result qm_hw_error_handle_v2(struct hisi_qm *qm)
2425 {
2426         u32 error_status, tmp;
2427
2428         /* read err sts */
2429         tmp = readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
2430         error_status = qm->error_mask & tmp;
2431
2432         if (error_status) {
2433                 if (error_status & QM_ECC_MBIT)
2434                         qm->err_status.is_qm_ecc_mbit = true;
2435
2436                 qm_log_hw_error(qm, error_status);
2437                 if (error_status & qm->err_info.qm_reset_mask)
2438                         return ACC_ERR_NEED_RESET;
2439
2440                 writel(error_status, qm->io_base + QM_ABNORMAL_INT_SOURCE);
2441                 writel(qm->err_info.nfe, qm->io_base + QM_RAS_NFE_ENABLE);
2442         }
2443
2444         return ACC_ERR_RECOVERED;
2445 }
2446
2447 static int qm_get_mb_cmd(struct hisi_qm *qm, u64 *msg, u16 fun_num)
2448 {
2449         struct qm_mailbox mailbox;
2450         int ret;
2451
2452         qm_mb_pre_init(&mailbox, QM_MB_CMD_DST, 0, fun_num, 0);
2453         mutex_lock(&qm->mailbox_lock);
2454         ret = qm_mb_nolock(qm, &mailbox);
2455         if (ret)
2456                 goto err_unlock;
2457
2458         *msg = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
2459                   ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32);
2460
2461 err_unlock:
2462         mutex_unlock(&qm->mailbox_lock);
2463         return ret;
2464 }
2465
2466 static void qm_clear_cmd_interrupt(struct hisi_qm *qm, u64 vf_mask)
2467 {
2468         u32 val;
2469
2470         if (qm->fun_type == QM_HW_PF)
2471                 writeq(vf_mask, qm->io_base + QM_IFC_INT_SOURCE_P);
2472
2473         val = readl(qm->io_base + QM_IFC_INT_SOURCE_V);
2474         val |= QM_IFC_INT_SOURCE_MASK;
2475         writel(val, qm->io_base + QM_IFC_INT_SOURCE_V);
2476 }
2477
2478 static void qm_handle_vf_msg(struct hisi_qm *qm, u32 vf_id)
2479 {
2480         struct device *dev = &qm->pdev->dev;
2481         u32 cmd;
2482         u64 msg;
2483         int ret;
2484
2485         ret = qm_get_mb_cmd(qm, &msg, vf_id);
2486         if (ret) {
2487                 dev_err(dev, "failed to get msg from VF(%u)!\n", vf_id);
2488                 return;
2489         }
2490
2491         cmd = msg & QM_MB_CMD_DATA_MASK;
2492         switch (cmd) {
2493         case QM_VF_PREPARE_FAIL:
2494                 dev_err(dev, "failed to stop VF(%u)!\n", vf_id);
2495                 break;
2496         case QM_VF_START_FAIL:
2497                 dev_err(dev, "failed to start VF(%u)!\n", vf_id);
2498                 break;
2499         case QM_VF_PREPARE_DONE:
2500         case QM_VF_START_DONE:
2501                 break;
2502         default:
2503                 dev_err(dev, "unsupported cmd %u sent by VF(%u)!\n", cmd, vf_id);
2504                 break;
2505         }
2506 }
2507
2508 static int qm_wait_vf_prepare_finish(struct hisi_qm *qm)
2509 {
2510         struct device *dev = &qm->pdev->dev;
2511         u32 vfs_num = qm->vfs_num;
2512         int cnt = 0;
2513         int ret = 0;
2514         u64 val;
2515         u32 i;
2516
2517         if (!qm->vfs_num || !test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps))
2518                 return 0;
2519
2520         while (true) {
2521                 val = readq(qm->io_base + QM_IFC_INT_SOURCE_P);
2522                 /* All VFs send command to PF, break */
2523                 if ((val & GENMASK(vfs_num, 1)) == GENMASK(vfs_num, 1))
2524                         break;
2525
2526                 if (++cnt > QM_MAX_PF_WAIT_COUNT) {
2527                         ret = -EBUSY;
2528                         break;
2529                 }
2530
2531                 msleep(QM_WAIT_DST_ACK);
2532         }
2533
2534         /* PF check VFs msg */
2535         for (i = 1; i <= vfs_num; i++) {
2536                 if (val & BIT(i))
2537                         qm_handle_vf_msg(qm, i);
2538                 else
2539                         dev_err(dev, "VF(%u) not ping PF!\n", i);
2540         }
2541
2542         /* PF clear interrupt to ack VFs */
2543         qm_clear_cmd_interrupt(qm, val);
2544
2545         return ret;
2546 }
2547
2548 static void qm_trigger_vf_interrupt(struct hisi_qm *qm, u32 fun_num)
2549 {
2550         u32 val;
2551
2552         val = readl(qm->io_base + QM_IFC_INT_CFG);
2553         val &= ~QM_IFC_SEND_ALL_VFS;
2554         val |= fun_num;
2555         writel(val, qm->io_base + QM_IFC_INT_CFG);
2556
2557         val = readl(qm->io_base + QM_IFC_INT_SET_P);
2558         val |= QM_IFC_INT_SET_MASK;
2559         writel(val, qm->io_base + QM_IFC_INT_SET_P);
2560 }
2561
2562 static void qm_trigger_pf_interrupt(struct hisi_qm *qm)
2563 {
2564         u32 val;
2565
2566         val = readl(qm->io_base + QM_IFC_INT_SET_V);
2567         val |= QM_IFC_INT_SET_MASK;
2568         writel(val, qm->io_base + QM_IFC_INT_SET_V);
2569 }
2570
2571 static int qm_ping_single_vf(struct hisi_qm *qm, u64 cmd, u32 fun_num)
2572 {
2573         struct device *dev = &qm->pdev->dev;
2574         struct qm_mailbox mailbox;
2575         int cnt = 0;
2576         u64 val;
2577         int ret;
2578
2579         qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, cmd, fun_num, 0);
2580         mutex_lock(&qm->mailbox_lock);
2581         ret = qm_mb_nolock(qm, &mailbox);
2582         if (ret) {
2583                 dev_err(dev, "failed to send command to vf(%u)!\n", fun_num);
2584                 goto err_unlock;
2585         }
2586
2587         qm_trigger_vf_interrupt(qm, fun_num);
2588         while (true) {
2589                 msleep(QM_WAIT_DST_ACK);
2590                 val = readq(qm->io_base + QM_IFC_READY_STATUS);
2591                 /* if VF respond, PF notifies VF successfully. */
2592                 if (!(val & BIT(fun_num)))
2593                         goto err_unlock;
2594
2595                 if (++cnt > QM_MAX_PF_WAIT_COUNT) {
2596                         dev_err(dev, "failed to get response from VF(%u)!\n", fun_num);
2597                         ret = -ETIMEDOUT;
2598                         break;
2599                 }
2600         }
2601
2602 err_unlock:
2603         mutex_unlock(&qm->mailbox_lock);
2604         return ret;
2605 }
2606
2607 static int qm_ping_all_vfs(struct hisi_qm *qm, u64 cmd)
2608 {
2609         struct device *dev = &qm->pdev->dev;
2610         u32 vfs_num = qm->vfs_num;
2611         struct qm_mailbox mailbox;
2612         u64 val = 0;
2613         int cnt = 0;
2614         int ret;
2615         u32 i;
2616
2617         qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, cmd, QM_MB_PING_ALL_VFS, 0);
2618         mutex_lock(&qm->mailbox_lock);
2619         /* PF sends command to all VFs by mailbox */
2620         ret = qm_mb_nolock(qm, &mailbox);
2621         if (ret) {
2622                 dev_err(dev, "failed to send command to VFs!\n");
2623                 mutex_unlock(&qm->mailbox_lock);
2624                 return ret;
2625         }
2626
2627         qm_trigger_vf_interrupt(qm, QM_IFC_SEND_ALL_VFS);
2628         while (true) {
2629                 msleep(QM_WAIT_DST_ACK);
2630                 val = readq(qm->io_base + QM_IFC_READY_STATUS);
2631                 /* If all VFs acked, PF notifies VFs successfully. */
2632                 if (!(val & GENMASK(vfs_num, 1))) {
2633                         mutex_unlock(&qm->mailbox_lock);
2634                         return 0;
2635                 }
2636
2637                 if (++cnt > QM_MAX_PF_WAIT_COUNT)
2638                         break;
2639         }
2640
2641         mutex_unlock(&qm->mailbox_lock);
2642
2643         /* Check which vf respond timeout. */
2644         for (i = 1; i <= vfs_num; i++) {
2645                 if (val & BIT(i))
2646                         dev_err(dev, "failed to get response from VF(%u)!\n", i);
2647         }
2648
2649         return -ETIMEDOUT;
2650 }
2651
2652 static int qm_ping_pf(struct hisi_qm *qm, u64 cmd)
2653 {
2654         struct qm_mailbox mailbox;
2655         int cnt = 0;
2656         u32 val;
2657         int ret;
2658
2659         qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, cmd, 0, 0);
2660         mutex_lock(&qm->mailbox_lock);
2661         ret = qm_mb_nolock(qm, &mailbox);
2662         if (ret) {
2663                 dev_err(&qm->pdev->dev, "failed to send command to PF!\n");
2664                 goto unlock;
2665         }
2666
2667         qm_trigger_pf_interrupt(qm);
2668         /* Waiting for PF response */
2669         while (true) {
2670                 msleep(QM_WAIT_DST_ACK);
2671                 val = readl(qm->io_base + QM_IFC_INT_SET_V);
2672                 if (!(val & QM_IFC_INT_STATUS_MASK))
2673                         break;
2674
2675                 if (++cnt > QM_MAX_VF_WAIT_COUNT) {
2676                         ret = -ETIMEDOUT;
2677                         break;
2678                 }
2679         }
2680
2681 unlock:
2682         mutex_unlock(&qm->mailbox_lock);
2683         return ret;
2684 }
2685
2686 static int qm_stop_qp(struct hisi_qp *qp)
2687 {
2688         return hisi_qm_mb(qp->qm, QM_MB_CMD_STOP_QP, 0, qp->qp_id, 0);
2689 }
2690
2691 static int qm_set_msi(struct hisi_qm *qm, bool set)
2692 {
2693         struct pci_dev *pdev = qm->pdev;
2694
2695         if (set) {
2696                 pci_write_config_dword(pdev, pdev->msi_cap + PCI_MSI_MASK_64,
2697                                        0);
2698         } else {
2699                 pci_write_config_dword(pdev, pdev->msi_cap + PCI_MSI_MASK_64,
2700                                        ACC_PEH_MSI_DISABLE);
2701                 if (qm->err_status.is_qm_ecc_mbit ||
2702                     qm->err_status.is_dev_ecc_mbit)
2703                         return 0;
2704
2705                 mdelay(1);
2706                 if (readl(qm->io_base + QM_PEH_DFX_INFO0))
2707                         return -EFAULT;
2708         }
2709
2710         return 0;
2711 }
2712
2713 static void qm_wait_msi_finish(struct hisi_qm *qm)
2714 {
2715         struct pci_dev *pdev = qm->pdev;
2716         u32 cmd = ~0;
2717         int cnt = 0;
2718         u32 val;
2719         int ret;
2720
2721         while (true) {
2722                 pci_read_config_dword(pdev, pdev->msi_cap +
2723                                       PCI_MSI_PENDING_64, &cmd);
2724                 if (!cmd)
2725                         break;
2726
2727                 if (++cnt > MAX_WAIT_COUNTS) {
2728                         pci_warn(pdev, "failed to empty MSI PENDING!\n");
2729                         break;
2730                 }
2731
2732                 udelay(1);
2733         }
2734
2735         ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_DFX_INFO0,
2736                                          val, !(val & QM_PEH_DFX_MASK),
2737                                          POLL_PERIOD, POLL_TIMEOUT);
2738         if (ret)
2739                 pci_warn(pdev, "failed to empty PEH MSI!\n");
2740
2741         ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_DFX_INFO1,
2742                                          val, !(val & QM_PEH_MSI_FINISH_MASK),
2743                                          POLL_PERIOD, POLL_TIMEOUT);
2744         if (ret)
2745                 pci_warn(pdev, "failed to finish MSI operation!\n");
2746 }
2747
2748 static int qm_set_msi_v3(struct hisi_qm *qm, bool set)
2749 {
2750         struct pci_dev *pdev = qm->pdev;
2751         int ret = -ETIMEDOUT;
2752         u32 cmd, i;
2753
2754         pci_read_config_dword(pdev, pdev->msi_cap, &cmd);
2755         if (set)
2756                 cmd |= QM_MSI_CAP_ENABLE;
2757         else
2758                 cmd &= ~QM_MSI_CAP_ENABLE;
2759
2760         pci_write_config_dword(pdev, pdev->msi_cap, cmd);
2761         if (set) {
2762                 for (i = 0; i < MAX_WAIT_COUNTS; i++) {
2763                         pci_read_config_dword(pdev, pdev->msi_cap, &cmd);
2764                         if (cmd & QM_MSI_CAP_ENABLE)
2765                                 return 0;
2766
2767                         udelay(1);
2768                 }
2769         } else {
2770                 udelay(WAIT_PERIOD_US_MIN);
2771                 qm_wait_msi_finish(qm);
2772                 ret = 0;
2773         }
2774
2775         return ret;
2776 }
2777
2778 static const struct hisi_qm_hw_ops qm_hw_ops_v1 = {
2779         .qm_db = qm_db_v1,
2780         .hw_error_init = qm_hw_error_init_v1,
2781         .set_msi = qm_set_msi,
2782 };
2783
2784 static const struct hisi_qm_hw_ops qm_hw_ops_v2 = {
2785         .get_vft = qm_get_vft_v2,
2786         .qm_db = qm_db_v2,
2787         .hw_error_init = qm_hw_error_init_v2,
2788         .hw_error_uninit = qm_hw_error_uninit_v2,
2789         .hw_error_handle = qm_hw_error_handle_v2,
2790         .set_msi = qm_set_msi,
2791 };
2792
2793 static const struct hisi_qm_hw_ops qm_hw_ops_v3 = {
2794         .get_vft = qm_get_vft_v2,
2795         .qm_db = qm_db_v2,
2796         .hw_error_init = qm_hw_error_init_v3,
2797         .hw_error_uninit = qm_hw_error_uninit_v3,
2798         .hw_error_handle = qm_hw_error_handle_v2,
2799         .set_msi = qm_set_msi_v3,
2800 };
2801
2802 static void *qm_get_avail_sqe(struct hisi_qp *qp)
2803 {
2804         struct hisi_qp_status *qp_status = &qp->qp_status;
2805         u16 sq_tail = qp_status->sq_tail;
2806
2807         if (unlikely(atomic_read(&qp->qp_status.used) == qp->sq_depth - 1))
2808                 return NULL;
2809
2810         return qp->sqe + sq_tail * qp->qm->sqe_size;
2811 }
2812
2813 static void hisi_qm_unset_hw_reset(struct hisi_qp *qp)
2814 {
2815         u64 *addr;
2816
2817         /* Use last 64 bits of DUS to reset status. */
2818         addr = (u64 *)(qp->qdma.va + qp->qdma.size) - QM_RESET_STOP_TX_OFFSET;
2819         *addr = 0;
2820 }
2821
2822 static struct hisi_qp *qm_create_qp_nolock(struct hisi_qm *qm, u8 alg_type)
2823 {
2824         struct device *dev = &qm->pdev->dev;
2825         struct hisi_qp *qp;
2826         int qp_id;
2827
2828         if (!qm_qp_avail_state(qm, NULL, QP_INIT))
2829                 return ERR_PTR(-EPERM);
2830
2831         if (qm->qp_in_used == qm->qp_num) {
2832                 dev_info_ratelimited(dev, "All %u queues of QM are busy!\n",
2833                                      qm->qp_num);
2834                 atomic64_inc(&qm->debug.dfx.create_qp_err_cnt);
2835                 return ERR_PTR(-EBUSY);
2836         }
2837
2838         qp_id = idr_alloc_cyclic(&qm->qp_idr, NULL, 0, qm->qp_num, GFP_ATOMIC);
2839         if (qp_id < 0) {
2840                 dev_info_ratelimited(dev, "All %u queues of QM are busy!\n",
2841                                     qm->qp_num);
2842                 atomic64_inc(&qm->debug.dfx.create_qp_err_cnt);
2843                 return ERR_PTR(-EBUSY);
2844         }
2845
2846         qp = &qm->qp_array[qp_id];
2847         hisi_qm_unset_hw_reset(qp);
2848         memset(qp->cqe, 0, sizeof(struct qm_cqe) * qp->cq_depth);
2849
2850         qp->event_cb = NULL;
2851         qp->req_cb = NULL;
2852         qp->qp_id = qp_id;
2853         qp->alg_type = alg_type;
2854         qp->is_in_kernel = true;
2855         qm->qp_in_used++;
2856         atomic_set(&qp->qp_status.flags, QP_INIT);
2857
2858         return qp;
2859 }
2860
2861 /**
2862  * hisi_qm_create_qp() - Create a queue pair from qm.
2863  * @qm: The qm we create a qp from.
2864  * @alg_type: Accelerator specific algorithm type in sqc.
2865  *
2866  * return created qp, -EBUSY if all qps in qm allocated, -ENOMEM if allocating
2867  * qp memory fails.
2868  */
2869 static struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type)
2870 {
2871         struct hisi_qp *qp;
2872         int ret;
2873
2874         ret = qm_pm_get_sync(qm);
2875         if (ret)
2876                 return ERR_PTR(ret);
2877
2878         down_write(&qm->qps_lock);
2879         qp = qm_create_qp_nolock(qm, alg_type);
2880         up_write(&qm->qps_lock);
2881
2882         if (IS_ERR(qp))
2883                 qm_pm_put_sync(qm);
2884
2885         return qp;
2886 }
2887
2888 /**
2889  * hisi_qm_release_qp() - Release a qp back to its qm.
2890  * @qp: The qp we want to release.
2891  *
2892  * This function releases the resource of a qp.
2893  */
2894 static void hisi_qm_release_qp(struct hisi_qp *qp)
2895 {
2896         struct hisi_qm *qm = qp->qm;
2897
2898         down_write(&qm->qps_lock);
2899
2900         if (!qm_qp_avail_state(qm, qp, QP_CLOSE)) {
2901                 up_write(&qm->qps_lock);
2902                 return;
2903         }
2904
2905         qm->qp_in_used--;
2906         idr_remove(&qm->qp_idr, qp->qp_id);
2907
2908         up_write(&qm->qps_lock);
2909
2910         qm_pm_put_sync(qm);
2911 }
2912
2913 static int qm_sq_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid)
2914 {
2915         struct hisi_qm *qm = qp->qm;
2916         struct device *dev = &qm->pdev->dev;
2917         enum qm_hw_ver ver = qm->ver;
2918         struct qm_sqc *sqc;
2919         dma_addr_t sqc_dma;
2920         int ret;
2921
2922         sqc = kzalloc(sizeof(struct qm_sqc), GFP_KERNEL);
2923         if (!sqc)
2924                 return -ENOMEM;
2925
2926         INIT_QC_COMMON(sqc, qp->sqe_dma, pasid);
2927         if (ver == QM_HW_V1) {
2928                 sqc->dw3 = cpu_to_le32(QM_MK_SQC_DW3_V1(0, 0, 0, qm->sqe_size));
2929                 sqc->w8 = cpu_to_le16(qp->sq_depth - 1);
2930         } else {
2931                 sqc->dw3 = cpu_to_le32(QM_MK_SQC_DW3_V2(qm->sqe_size, qp->sq_depth));
2932                 sqc->w8 = 0; /* rand_qc */
2933         }
2934         sqc->cq_num = cpu_to_le16(qp_id);
2935         sqc->w13 = cpu_to_le16(QM_MK_SQC_W13(0, 1, qp->alg_type));
2936
2937         if (ver >= QM_HW_V3 && qm->use_sva && !qp->is_in_kernel)
2938                 sqc->w11 = cpu_to_le16(QM_QC_PASID_ENABLE <<
2939                                        QM_QC_PASID_ENABLE_SHIFT);
2940
2941         sqc_dma = dma_map_single(dev, sqc, sizeof(struct qm_sqc),
2942                                  DMA_TO_DEVICE);
2943         if (dma_mapping_error(dev, sqc_dma)) {
2944                 kfree(sqc);
2945                 return -ENOMEM;
2946         }
2947
2948         ret = hisi_qm_mb(qm, QM_MB_CMD_SQC, sqc_dma, qp_id, 0);
2949         dma_unmap_single(dev, sqc_dma, sizeof(struct qm_sqc), DMA_TO_DEVICE);
2950         kfree(sqc);
2951
2952         return ret;
2953 }
2954
2955 static int qm_cq_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid)
2956 {
2957         struct hisi_qm *qm = qp->qm;
2958         struct device *dev = &qm->pdev->dev;
2959         enum qm_hw_ver ver = qm->ver;
2960         struct qm_cqc *cqc;
2961         dma_addr_t cqc_dma;
2962         int ret;
2963
2964         cqc = kzalloc(sizeof(struct qm_cqc), GFP_KERNEL);
2965         if (!cqc)
2966                 return -ENOMEM;
2967
2968         INIT_QC_COMMON(cqc, qp->cqe_dma, pasid);
2969         if (ver == QM_HW_V1) {
2970                 cqc->dw3 = cpu_to_le32(QM_MK_CQC_DW3_V1(0, 0, 0,
2971                                                         QM_QC_CQE_SIZE));
2972                 cqc->w8 = cpu_to_le16(qp->cq_depth - 1);
2973         } else {
2974                 cqc->dw3 = cpu_to_le32(QM_MK_CQC_DW3_V2(QM_QC_CQE_SIZE, qp->cq_depth));
2975                 cqc->w8 = 0; /* rand_qc */
2976         }
2977         cqc->dw6 = cpu_to_le32(1 << QM_CQ_PHASE_SHIFT | 1 << QM_CQ_FLAG_SHIFT);
2978
2979         if (ver >= QM_HW_V3 && qm->use_sva && !qp->is_in_kernel)
2980                 cqc->w11 = cpu_to_le16(QM_QC_PASID_ENABLE);
2981
2982         cqc_dma = dma_map_single(dev, cqc, sizeof(struct qm_cqc),
2983                                  DMA_TO_DEVICE);
2984         if (dma_mapping_error(dev, cqc_dma)) {
2985                 kfree(cqc);
2986                 return -ENOMEM;
2987         }
2988
2989         ret = hisi_qm_mb(qm, QM_MB_CMD_CQC, cqc_dma, qp_id, 0);
2990         dma_unmap_single(dev, cqc_dma, sizeof(struct qm_cqc), DMA_TO_DEVICE);
2991         kfree(cqc);
2992
2993         return ret;
2994 }
2995
2996 static int qm_qp_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid)
2997 {
2998         int ret;
2999
3000         qm_init_qp_status(qp);
3001
3002         ret = qm_sq_ctx_cfg(qp, qp_id, pasid);
3003         if (ret)
3004                 return ret;
3005
3006         return qm_cq_ctx_cfg(qp, qp_id, pasid);
3007 }
3008
3009 static int qm_start_qp_nolock(struct hisi_qp *qp, unsigned long arg)
3010 {
3011         struct hisi_qm *qm = qp->qm;
3012         struct device *dev = &qm->pdev->dev;
3013         int qp_id = qp->qp_id;
3014         u32 pasid = arg;
3015         int ret;
3016
3017         if (!qm_qp_avail_state(qm, qp, QP_START))
3018                 return -EPERM;
3019
3020         ret = qm_qp_ctx_cfg(qp, qp_id, pasid);
3021         if (ret)
3022                 return ret;
3023
3024         atomic_set(&qp->qp_status.flags, QP_START);
3025         dev_dbg(dev, "queue %d started\n", qp_id);
3026
3027         return 0;
3028 }
3029
3030 /**
3031  * hisi_qm_start_qp() - Start a qp into running.
3032  * @qp: The qp we want to start to run.
3033  * @arg: Accelerator specific argument.
3034  *
3035  * After this function, qp can receive request from user. Return 0 if
3036  * successful, Return -EBUSY if failed.
3037  */
3038 int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg)
3039 {
3040         struct hisi_qm *qm = qp->qm;
3041         int ret;
3042
3043         down_write(&qm->qps_lock);
3044         ret = qm_start_qp_nolock(qp, arg);
3045         up_write(&qm->qps_lock);
3046
3047         return ret;
3048 }
3049 EXPORT_SYMBOL_GPL(hisi_qm_start_qp);
3050
3051 /**
3052  * qp_stop_fail_cb() - call request cb.
3053  * @qp: stopped failed qp.
3054  *
3055  * Callback function should be called whether task completed or not.
3056  */
3057 static void qp_stop_fail_cb(struct hisi_qp *qp)
3058 {
3059         int qp_used = atomic_read(&qp->qp_status.used);
3060         u16 cur_tail = qp->qp_status.sq_tail;
3061         u16 sq_depth = qp->sq_depth;
3062         u16 cur_head = (cur_tail + sq_depth - qp_used) % sq_depth;
3063         struct hisi_qm *qm = qp->qm;
3064         u16 pos;
3065         int i;
3066
3067         for (i = 0; i < qp_used; i++) {
3068                 pos = (i + cur_head) % sq_depth;
3069                 qp->req_cb(qp, qp->sqe + (u32)(qm->sqe_size * pos));
3070                 atomic_dec(&qp->qp_status.used);
3071         }
3072 }
3073
3074 /**
3075  * qm_drain_qp() - Drain a qp.
3076  * @qp: The qp we want to drain.
3077  *
3078  * Determine whether the queue is cleared by judging the tail pointers of
3079  * sq and cq.
3080  */
3081 static int qm_drain_qp(struct hisi_qp *qp)
3082 {
3083         size_t size = sizeof(struct qm_sqc) + sizeof(struct qm_cqc);
3084         struct hisi_qm *qm = qp->qm;
3085         struct device *dev = &qm->pdev->dev;
3086         struct qm_sqc *sqc;
3087         struct qm_cqc *cqc;
3088         dma_addr_t dma_addr;
3089         int ret = 0, i = 0;
3090         void *addr;
3091
3092         /* No need to judge if master OOO is blocked. */
3093         if (qm_check_dev_error(qm))
3094                 return 0;
3095
3096         /* Kunpeng930 supports drain qp by device */
3097         if (test_bit(QM_SUPPORT_STOP_QP, &qm->caps)) {
3098                 ret = qm_stop_qp(qp);
3099                 if (ret)
3100                         dev_err(dev, "Failed to stop qp(%u)!\n", qp->qp_id);
3101                 return ret;
3102         }
3103
3104         addr = qm_ctx_alloc(qm, size, &dma_addr);
3105         if (IS_ERR(addr)) {
3106                 dev_err(dev, "Failed to alloc ctx for sqc and cqc!\n");
3107                 return -ENOMEM;
3108         }
3109
3110         while (++i) {
3111                 ret = qm_dump_sqc_raw(qm, dma_addr, qp->qp_id);
3112                 if (ret) {
3113                         dev_err_ratelimited(dev, "Failed to dump sqc!\n");
3114                         break;
3115                 }
3116                 sqc = addr;
3117
3118                 ret = qm_dump_cqc_raw(qm, (dma_addr + sizeof(struct qm_sqc)),
3119                                       qp->qp_id);
3120                 if (ret) {
3121                         dev_err_ratelimited(dev, "Failed to dump cqc!\n");
3122                         break;
3123                 }
3124                 cqc = addr + sizeof(struct qm_sqc);
3125
3126                 if ((sqc->tail == cqc->tail) &&
3127                     (QM_SQ_TAIL_IDX(sqc) == QM_CQ_TAIL_IDX(cqc)))
3128                         break;
3129
3130                 if (i == MAX_WAIT_COUNTS) {
3131                         dev_err(dev, "Fail to empty queue %u!\n", qp->qp_id);
3132                         ret = -EBUSY;
3133                         break;
3134                 }
3135
3136                 usleep_range(WAIT_PERIOD_US_MIN, WAIT_PERIOD_US_MAX);
3137         }
3138
3139         qm_ctx_free(qm, size, addr, &dma_addr);
3140
3141         return ret;
3142 }
3143
3144 static int qm_stop_qp_nolock(struct hisi_qp *qp)
3145 {
3146         struct device *dev = &qp->qm->pdev->dev;
3147         int ret;
3148
3149         /*
3150          * It is allowed to stop and release qp when reset, If the qp is
3151          * stopped when reset but still want to be released then, the
3152          * is_resetting flag should be set negative so that this qp will not
3153          * be restarted after reset.
3154          */
3155         if (atomic_read(&qp->qp_status.flags) == QP_STOP) {
3156                 qp->is_resetting = false;
3157                 return 0;
3158         }
3159
3160         if (!qm_qp_avail_state(qp->qm, qp, QP_STOP))
3161                 return -EPERM;
3162
3163         atomic_set(&qp->qp_status.flags, QP_STOP);
3164
3165         ret = qm_drain_qp(qp);
3166         if (ret)
3167                 dev_err(dev, "Failed to drain out data for stopping!\n");
3168
3169
3170         flush_workqueue(qp->qm->wq);
3171         if (unlikely(qp->is_resetting && atomic_read(&qp->qp_status.used)))
3172                 qp_stop_fail_cb(qp);
3173
3174         dev_dbg(dev, "stop queue %u!", qp->qp_id);
3175
3176         return 0;
3177 }
3178
3179 /**
3180  * hisi_qm_stop_qp() - Stop a qp in qm.
3181  * @qp: The qp we want to stop.
3182  *
3183  * This function is reverse of hisi_qm_start_qp. Return 0 if successful.
3184  */
3185 int hisi_qm_stop_qp(struct hisi_qp *qp)
3186 {
3187         int ret;
3188
3189         down_write(&qp->qm->qps_lock);
3190         ret = qm_stop_qp_nolock(qp);
3191         up_write(&qp->qm->qps_lock);
3192
3193         return ret;
3194 }
3195 EXPORT_SYMBOL_GPL(hisi_qm_stop_qp);
3196
3197 /**
3198  * hisi_qp_send() - Queue up a task in the hardware queue.
3199  * @qp: The qp in which to put the message.
3200  * @msg: The message.
3201  *
3202  * This function will return -EBUSY if qp is currently full, and -EAGAIN
3203  * if qp related qm is resetting.
3204  *
3205  * Note: This function may run with qm_irq_thread and ACC reset at same time.
3206  *       It has no race with qm_irq_thread. However, during hisi_qp_send, ACC
3207  *       reset may happen, we have no lock here considering performance. This
3208  *       causes current qm_db sending fail or can not receive sended sqe. QM
3209  *       sync/async receive function should handle the error sqe. ACC reset
3210  *       done function should clear used sqe to 0.
3211  */
3212 int hisi_qp_send(struct hisi_qp *qp, const void *msg)
3213 {
3214         struct hisi_qp_status *qp_status = &qp->qp_status;
3215         u16 sq_tail = qp_status->sq_tail;
3216         u16 sq_tail_next = (sq_tail + 1) % qp->sq_depth;
3217         void *sqe = qm_get_avail_sqe(qp);
3218
3219         if (unlikely(atomic_read(&qp->qp_status.flags) == QP_STOP ||
3220                      atomic_read(&qp->qm->status.flags) == QM_STOP ||
3221                      qp->is_resetting)) {
3222                 dev_info_ratelimited(&qp->qm->pdev->dev, "QP is stopped or resetting\n");
3223                 return -EAGAIN;
3224         }
3225
3226         if (!sqe)
3227                 return -EBUSY;
3228
3229         memcpy(sqe, msg, qp->qm->sqe_size);
3230
3231         qm_db(qp->qm, qp->qp_id, QM_DOORBELL_CMD_SQ, sq_tail_next, 0);
3232         atomic_inc(&qp->qp_status.used);
3233         qp_status->sq_tail = sq_tail_next;
3234
3235         return 0;
3236 }
3237 EXPORT_SYMBOL_GPL(hisi_qp_send);
3238
3239 static void hisi_qm_cache_wb(struct hisi_qm *qm)
3240 {
3241         unsigned int val;
3242
3243         if (qm->ver == QM_HW_V1)
3244                 return;
3245
3246         writel(0x1, qm->io_base + QM_CACHE_WB_START);
3247         if (readl_relaxed_poll_timeout(qm->io_base + QM_CACHE_WB_DONE,
3248                                        val, val & BIT(0), POLL_PERIOD,
3249                                        POLL_TIMEOUT))
3250                 dev_err(&qm->pdev->dev, "QM writeback sqc cache fail!\n");
3251 }
3252
3253 static void qm_qp_event_notifier(struct hisi_qp *qp)
3254 {
3255         wake_up_interruptible(&qp->uacce_q->wait);
3256 }
3257
3258  /* This function returns free number of qp in qm. */
3259 static int hisi_qm_get_available_instances(struct uacce_device *uacce)
3260 {
3261         struct hisi_qm *qm = uacce->priv;
3262         int ret;
3263
3264         down_read(&qm->qps_lock);
3265         ret = qm->qp_num - qm->qp_in_used;
3266         up_read(&qm->qps_lock);
3267
3268         return ret;
3269 }
3270
3271 static void hisi_qm_set_hw_reset(struct hisi_qm *qm, int offset)
3272 {
3273         int i;
3274
3275         for (i = 0; i < qm->qp_num; i++)
3276                 qm_set_qp_disable(&qm->qp_array[i], offset);
3277 }
3278
3279 static int hisi_qm_uacce_get_queue(struct uacce_device *uacce,
3280                                    unsigned long arg,
3281                                    struct uacce_queue *q)
3282 {
3283         struct hisi_qm *qm = uacce->priv;
3284         struct hisi_qp *qp;
3285         u8 alg_type = 0;
3286
3287         qp = hisi_qm_create_qp(qm, alg_type);
3288         if (IS_ERR(qp))
3289                 return PTR_ERR(qp);
3290
3291         q->priv = qp;
3292         q->uacce = uacce;
3293         qp->uacce_q = q;
3294         qp->event_cb = qm_qp_event_notifier;
3295         qp->pasid = arg;
3296         qp->is_in_kernel = false;
3297
3298         return 0;
3299 }
3300
3301 static void hisi_qm_uacce_put_queue(struct uacce_queue *q)
3302 {
3303         struct hisi_qp *qp = q->priv;
3304
3305         hisi_qm_release_qp(qp);
3306 }
3307
3308 /* map sq/cq/doorbell to user space */
3309 static int hisi_qm_uacce_mmap(struct uacce_queue *q,
3310                               struct vm_area_struct *vma,
3311                               struct uacce_qfile_region *qfr)
3312 {
3313         struct hisi_qp *qp = q->priv;
3314         struct hisi_qm *qm = qp->qm;
3315         resource_size_t phys_base = qm->db_phys_base +
3316                                     qp->qp_id * qm->db_interval;
3317         size_t sz = vma->vm_end - vma->vm_start;
3318         struct pci_dev *pdev = qm->pdev;
3319         struct device *dev = &pdev->dev;
3320         unsigned long vm_pgoff;
3321         int ret;
3322
3323         switch (qfr->type) {
3324         case UACCE_QFRT_MMIO:
3325                 if (qm->ver == QM_HW_V1) {
3326                         if (sz > PAGE_SIZE * QM_DOORBELL_PAGE_NR)
3327                                 return -EINVAL;
3328                 } else if (!test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps)) {
3329                         if (sz > PAGE_SIZE * (QM_DOORBELL_PAGE_NR +
3330                             QM_DOORBELL_SQ_CQ_BASE_V2 / PAGE_SIZE))
3331                                 return -EINVAL;
3332                 } else {
3333                         if (sz > qm->db_interval)
3334                                 return -EINVAL;
3335                 }
3336
3337                 vma->vm_flags |= VM_IO;
3338
3339                 return remap_pfn_range(vma, vma->vm_start,
3340                                        phys_base >> PAGE_SHIFT,
3341                                        sz, pgprot_noncached(vma->vm_page_prot));
3342         case UACCE_QFRT_DUS:
3343                 if (sz != qp->qdma.size)
3344                         return -EINVAL;
3345
3346                 /*
3347                  * dma_mmap_coherent() requires vm_pgoff as 0
3348                  * restore vm_pfoff to initial value for mmap()
3349                  */
3350                 vm_pgoff = vma->vm_pgoff;
3351                 vma->vm_pgoff = 0;
3352                 ret = dma_mmap_coherent(dev, vma, qp->qdma.va,
3353                                         qp->qdma.dma, sz);
3354                 vma->vm_pgoff = vm_pgoff;
3355                 return ret;
3356
3357         default:
3358                 return -EINVAL;
3359         }
3360 }
3361
3362 static int hisi_qm_uacce_start_queue(struct uacce_queue *q)
3363 {
3364         struct hisi_qp *qp = q->priv;
3365
3366         return hisi_qm_start_qp(qp, qp->pasid);
3367 }
3368
3369 static void hisi_qm_uacce_stop_queue(struct uacce_queue *q)
3370 {
3371         hisi_qm_stop_qp(q->priv);
3372 }
3373
3374 static int hisi_qm_is_q_updated(struct uacce_queue *q)
3375 {
3376         struct hisi_qp *qp = q->priv;
3377         struct qm_cqe *cqe = qp->cqe + qp->qp_status.cq_head;
3378         int updated = 0;
3379
3380         while (QM_CQE_PHASE(cqe) == qp->qp_status.cqc_phase) {
3381                 /* make sure to read data from memory */
3382                 dma_rmb();
3383                 qm_cq_head_update(qp);
3384                 cqe = qp->cqe + qp->qp_status.cq_head;
3385                 updated = 1;
3386         }
3387
3388         return updated;
3389 }
3390
3391 static void qm_set_sqctype(struct uacce_queue *q, u16 type)
3392 {
3393         struct hisi_qm *qm = q->uacce->priv;
3394         struct hisi_qp *qp = q->priv;
3395
3396         down_write(&qm->qps_lock);
3397         qp->alg_type = type;
3398         up_write(&qm->qps_lock);
3399 }
3400
3401 static long hisi_qm_uacce_ioctl(struct uacce_queue *q, unsigned int cmd,
3402                                 unsigned long arg)
3403 {
3404         struct hisi_qp *qp = q->priv;
3405         struct hisi_qp_info qp_info;
3406         struct hisi_qp_ctx qp_ctx;
3407
3408         if (cmd == UACCE_CMD_QM_SET_QP_CTX) {
3409                 if (copy_from_user(&qp_ctx, (void __user *)arg,
3410                                    sizeof(struct hisi_qp_ctx)))
3411                         return -EFAULT;
3412
3413                 if (qp_ctx.qc_type != 0 && qp_ctx.qc_type != 1)
3414                         return -EINVAL;
3415
3416                 qm_set_sqctype(q, qp_ctx.qc_type);
3417                 qp_ctx.id = qp->qp_id;
3418
3419                 if (copy_to_user((void __user *)arg, &qp_ctx,
3420                                  sizeof(struct hisi_qp_ctx)))
3421                         return -EFAULT;
3422
3423                 return 0;
3424         } else if (cmd == UACCE_CMD_QM_SET_QP_INFO) {
3425                 if (copy_from_user(&qp_info, (void __user *)arg,
3426                                    sizeof(struct hisi_qp_info)))
3427                         return -EFAULT;
3428
3429                 qp_info.sqe_size = qp->qm->sqe_size;
3430                 qp_info.sq_depth = qp->sq_depth;
3431                 qp_info.cq_depth = qp->cq_depth;
3432
3433                 if (copy_to_user((void __user *)arg, &qp_info,
3434                                   sizeof(struct hisi_qp_info)))
3435                         return -EFAULT;
3436
3437                 return 0;
3438         }
3439
3440         return -EINVAL;
3441 }
3442
3443 static const struct uacce_ops uacce_qm_ops = {
3444         .get_available_instances = hisi_qm_get_available_instances,
3445         .get_queue = hisi_qm_uacce_get_queue,
3446         .put_queue = hisi_qm_uacce_put_queue,
3447         .start_queue = hisi_qm_uacce_start_queue,
3448         .stop_queue = hisi_qm_uacce_stop_queue,
3449         .mmap = hisi_qm_uacce_mmap,
3450         .ioctl = hisi_qm_uacce_ioctl,
3451         .is_q_updated = hisi_qm_is_q_updated,
3452 };
3453
3454 static int qm_alloc_uacce(struct hisi_qm *qm)
3455 {
3456         struct pci_dev *pdev = qm->pdev;
3457         struct uacce_device *uacce;
3458         unsigned long mmio_page_nr;
3459         unsigned long dus_page_nr;
3460         u16 sq_depth, cq_depth;
3461         struct uacce_interface interface = {
3462                 .flags = UACCE_DEV_SVA,
3463                 .ops = &uacce_qm_ops,
3464         };
3465         int ret;
3466
3467         ret = strscpy(interface.name, dev_driver_string(&pdev->dev),
3468                       sizeof(interface.name));
3469         if (ret < 0)
3470                 return -ENAMETOOLONG;
3471
3472         uacce = uacce_alloc(&pdev->dev, &interface);
3473         if (IS_ERR(uacce))
3474                 return PTR_ERR(uacce);
3475
3476         if (uacce->flags & UACCE_DEV_SVA) {
3477                 qm->use_sva = true;
3478         } else {
3479                 /* only consider sva case */
3480                 uacce_remove(uacce);
3481                 qm->uacce = NULL;
3482                 return -EINVAL;
3483         }
3484
3485         uacce->is_vf = pdev->is_virtfn;
3486         uacce->priv = qm;
3487
3488         if (qm->ver == QM_HW_V1)
3489                 uacce->api_ver = HISI_QM_API_VER_BASE;
3490         else if (qm->ver == QM_HW_V2)
3491                 uacce->api_ver = HISI_QM_API_VER2_BASE;
3492         else
3493                 uacce->api_ver = HISI_QM_API_VER3_BASE;
3494
3495         if (qm->ver == QM_HW_V1)
3496                 mmio_page_nr = QM_DOORBELL_PAGE_NR;
3497         else if (!test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps))
3498                 mmio_page_nr = QM_DOORBELL_PAGE_NR +
3499                         QM_DOORBELL_SQ_CQ_BASE_V2 / PAGE_SIZE;
3500         else
3501                 mmio_page_nr = qm->db_interval / PAGE_SIZE;
3502
3503         qm_get_xqc_depth(qm, &sq_depth, &cq_depth, QM_QP_DEPTH_CAP);
3504
3505         /* Add one more page for device or qp status */
3506         dus_page_nr = (PAGE_SIZE - 1 + qm->sqe_size * sq_depth +
3507                        sizeof(struct qm_cqe) * cq_depth  + PAGE_SIZE) >>
3508                                          PAGE_SHIFT;
3509
3510         uacce->qf_pg_num[UACCE_QFRT_MMIO] = mmio_page_nr;
3511         uacce->qf_pg_num[UACCE_QFRT_DUS]  = dus_page_nr;
3512
3513         qm->uacce = uacce;
3514
3515         return 0;
3516 }
3517
3518 /**
3519  * qm_frozen() - Try to froze QM to cut continuous queue request. If
3520  * there is user on the QM, return failure without doing anything.
3521  * @qm: The qm needed to be fronzen.
3522  *
3523  * This function frozes QM, then we can do SRIOV disabling.
3524  */
3525 static int qm_frozen(struct hisi_qm *qm)
3526 {
3527         if (test_bit(QM_DRIVER_REMOVING, &qm->misc_ctl))
3528                 return 0;
3529
3530         down_write(&qm->qps_lock);
3531
3532         if (!qm->qp_in_used) {
3533                 qm->qp_in_used = qm->qp_num;
3534                 up_write(&qm->qps_lock);
3535                 set_bit(QM_DRIVER_REMOVING, &qm->misc_ctl);
3536                 return 0;
3537         }
3538
3539         up_write(&qm->qps_lock);
3540
3541         return -EBUSY;
3542 }
3543
3544 static int qm_try_frozen_vfs(struct pci_dev *pdev,
3545                              struct hisi_qm_list *qm_list)
3546 {
3547         struct hisi_qm *qm, *vf_qm;
3548         struct pci_dev *dev;
3549         int ret = 0;
3550
3551         if (!qm_list || !pdev)
3552                 return -EINVAL;
3553
3554         /* Try to frozen all the VFs as disable SRIOV */
3555         mutex_lock(&qm_list->lock);
3556         list_for_each_entry(qm, &qm_list->list, list) {
3557                 dev = qm->pdev;
3558                 if (dev == pdev)
3559                         continue;
3560                 if (pci_physfn(dev) == pdev) {
3561                         vf_qm = pci_get_drvdata(dev);
3562                         ret = qm_frozen(vf_qm);
3563                         if (ret)
3564                                 goto frozen_fail;
3565                 }
3566         }
3567
3568 frozen_fail:
3569         mutex_unlock(&qm_list->lock);
3570
3571         return ret;
3572 }
3573
3574 /**
3575  * hisi_qm_wait_task_finish() - Wait until the task is finished
3576  * when removing the driver.
3577  * @qm: The qm needed to wait for the task to finish.
3578  * @qm_list: The list of all available devices.
3579  */
3580 void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
3581 {
3582         while (qm_frozen(qm) ||
3583                ((qm->fun_type == QM_HW_PF) &&
3584                qm_try_frozen_vfs(qm->pdev, qm_list))) {
3585                 msleep(WAIT_PERIOD);
3586         }
3587
3588         while (test_bit(QM_RST_SCHED, &qm->misc_ctl) ||
3589                test_bit(QM_RESETTING, &qm->misc_ctl))
3590                 msleep(WAIT_PERIOD);
3591
3592         udelay(REMOVE_WAIT_DELAY);
3593 }
3594 EXPORT_SYMBOL_GPL(hisi_qm_wait_task_finish);
3595
3596 static void hisi_qp_memory_uninit(struct hisi_qm *qm, int num)
3597 {
3598         struct device *dev = &qm->pdev->dev;
3599         struct qm_dma *qdma;
3600         int i;
3601
3602         for (i = num - 1; i >= 0; i--) {
3603                 qdma = &qm->qp_array[i].qdma;
3604                 dma_free_coherent(dev, qdma->size, qdma->va, qdma->dma);
3605                 kfree(qm->poll_data[i].qp_finish_id);
3606         }
3607
3608         kfree(qm->poll_data);
3609         kfree(qm->qp_array);
3610 }
3611
3612 static int hisi_qp_memory_init(struct hisi_qm *qm, size_t dma_size, int id,
3613                                u16 sq_depth, u16 cq_depth)
3614 {
3615         struct device *dev = &qm->pdev->dev;
3616         size_t off = qm->sqe_size * sq_depth;
3617         struct hisi_qp *qp;
3618         int ret = -ENOMEM;
3619
3620         qm->poll_data[id].qp_finish_id = kcalloc(qm->qp_num, sizeof(u16),
3621                                                  GFP_KERNEL);
3622         if (!qm->poll_data[id].qp_finish_id)
3623                 return -ENOMEM;
3624
3625         qp = &qm->qp_array[id];
3626         qp->qdma.va = dma_alloc_coherent(dev, dma_size, &qp->qdma.dma,
3627                                          GFP_KERNEL);
3628         if (!qp->qdma.va)
3629                 goto err_free_qp_finish_id;
3630
3631         qp->sqe = qp->qdma.va;
3632         qp->sqe_dma = qp->qdma.dma;
3633         qp->cqe = qp->qdma.va + off;
3634         qp->cqe_dma = qp->qdma.dma + off;
3635         qp->qdma.size = dma_size;
3636         qp->sq_depth = sq_depth;
3637         qp->cq_depth = cq_depth;
3638         qp->qm = qm;
3639         qp->qp_id = id;
3640
3641         return 0;
3642
3643 err_free_qp_finish_id:
3644         kfree(qm->poll_data[id].qp_finish_id);
3645         return ret;
3646 }
3647
3648 static void hisi_qm_pre_init(struct hisi_qm *qm)
3649 {
3650         struct pci_dev *pdev = qm->pdev;
3651
3652         if (qm->ver == QM_HW_V1)
3653                 qm->ops = &qm_hw_ops_v1;
3654         else if (qm->ver == QM_HW_V2)
3655                 qm->ops = &qm_hw_ops_v2;
3656         else
3657                 qm->ops = &qm_hw_ops_v3;
3658
3659         pci_set_drvdata(pdev, qm);
3660         mutex_init(&qm->mailbox_lock);
3661         init_rwsem(&qm->qps_lock);
3662         qm->qp_in_used = 0;
3663         qm->misc_ctl = false;
3664         if (test_bit(QM_SUPPORT_RPM, &qm->caps)) {
3665                 if (!acpi_device_power_manageable(ACPI_COMPANION(&pdev->dev)))
3666                         dev_info(&pdev->dev, "_PS0 and _PR0 are not defined");
3667         }
3668 }
3669
3670 static void qm_cmd_uninit(struct hisi_qm *qm)
3671 {
3672         u32 val;
3673
3674         if (!test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps))
3675                 return;
3676
3677         val = readl(qm->io_base + QM_IFC_INT_MASK);
3678         val |= QM_IFC_INT_DISABLE;
3679         writel(val, qm->io_base + QM_IFC_INT_MASK);
3680 }
3681
3682 static void qm_cmd_init(struct hisi_qm *qm)
3683 {
3684         u32 val;
3685
3686         if (!test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps))
3687                 return;
3688
3689         /* Clear communication interrupt source */
3690         qm_clear_cmd_interrupt(qm, QM_IFC_INT_SOURCE_CLR);
3691
3692         /* Enable pf to vf communication reg. */
3693         val = readl(qm->io_base + QM_IFC_INT_MASK);
3694         val &= ~QM_IFC_INT_DISABLE;
3695         writel(val, qm->io_base + QM_IFC_INT_MASK);
3696 }
3697
3698 static void qm_put_pci_res(struct hisi_qm *qm)
3699 {
3700         struct pci_dev *pdev = qm->pdev;
3701
3702         if (test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps))
3703                 iounmap(qm->db_io_base);
3704
3705         iounmap(qm->io_base);
3706         pci_release_mem_regions(pdev);
3707 }
3708
3709 static void hisi_qm_pci_uninit(struct hisi_qm *qm)
3710 {
3711         struct pci_dev *pdev = qm->pdev;
3712
3713         pci_free_irq_vectors(pdev);
3714         qm_put_pci_res(qm);
3715         pci_disable_device(pdev);
3716 }
3717
3718 static void hisi_qm_set_state(struct hisi_qm *qm, u8 state)
3719 {
3720         if (qm->ver > QM_HW_V2 && qm->fun_type == QM_HW_VF)
3721                 writel(state, qm->io_base + QM_VF_STATE);
3722 }
3723
3724 static void qm_last_regs_uninit(struct hisi_qm *qm)
3725 {
3726         struct qm_debug *debug = &qm->debug;
3727
3728         if (qm->fun_type == QM_HW_VF || !debug->qm_last_words)
3729                 return;
3730
3731         kfree(debug->qm_last_words);
3732         debug->qm_last_words = NULL;
3733 }
3734
3735 static void hisi_qm_unint_work(struct hisi_qm *qm)
3736 {
3737         destroy_workqueue(qm->wq);
3738 }
3739
3740 static void hisi_qm_memory_uninit(struct hisi_qm *qm)
3741 {
3742         struct device *dev = &qm->pdev->dev;
3743
3744         hisi_qp_memory_uninit(qm, qm->qp_num);
3745         if (qm->qdma.va) {
3746                 hisi_qm_cache_wb(qm);
3747                 dma_free_coherent(dev, qm->qdma.size,
3748                                   qm->qdma.va, qm->qdma.dma);
3749         }
3750
3751         idr_destroy(&qm->qp_idr);
3752
3753         if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps))
3754                 kfree(qm->factor);
3755 }
3756
3757 /**
3758  * hisi_qm_uninit() - Uninitialize qm.
3759  * @qm: The qm needed uninit.
3760  *
3761  * This function uninits qm related device resources.
3762  */
3763 void hisi_qm_uninit(struct hisi_qm *qm)
3764 {
3765         qm_last_regs_uninit(qm);
3766
3767         qm_cmd_uninit(qm);
3768         hisi_qm_unint_work(qm);
3769         down_write(&qm->qps_lock);
3770
3771         if (!qm_avail_state(qm, QM_CLOSE)) {
3772                 up_write(&qm->qps_lock);
3773                 return;
3774         }
3775
3776         hisi_qm_memory_uninit(qm);
3777         hisi_qm_set_state(qm, QM_NOT_READY);
3778         up_write(&qm->qps_lock);
3779
3780         qm_irqs_unregister(qm);
3781         hisi_qm_pci_uninit(qm);
3782         if (qm->use_sva) {
3783                 uacce_remove(qm->uacce);
3784                 qm->uacce = NULL;
3785         }
3786 }
3787 EXPORT_SYMBOL_GPL(hisi_qm_uninit);
3788
3789 /**
3790  * hisi_qm_get_vft() - Get vft from a qm.
3791  * @qm: The qm we want to get its vft.
3792  * @base: The base number of queue in vft.
3793  * @number: The number of queues in vft.
3794  *
3795  * We can allocate multiple queues to a qm by configuring virtual function
3796  * table. We get related configures by this function. Normally, we call this
3797  * function in VF driver to get the queue information.
3798  *
3799  * qm hw v1 does not support this interface.
3800  */
3801 static int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number)
3802 {
3803         if (!base || !number)
3804                 return -EINVAL;
3805
3806         if (!qm->ops->get_vft) {
3807                 dev_err(&qm->pdev->dev, "Don't support vft read!\n");
3808                 return -EINVAL;
3809         }
3810
3811         return qm->ops->get_vft(qm, base, number);
3812 }
3813
3814 /**
3815  * hisi_qm_set_vft() - Set vft to a qm.
3816  * @qm: The qm we want to set its vft.
3817  * @fun_num: The function number.
3818  * @base: The base number of queue in vft.
3819  * @number: The number of queues in vft.
3820  *
3821  * This function is alway called in PF driver, it is used to assign queues
3822  * among PF and VFs.
3823  *
3824  * Assign queues A~B to PF: hisi_qm_set_vft(qm, 0, A, B - A + 1)
3825  * Assign queues A~B to VF: hisi_qm_set_vft(qm, 2, A, B - A + 1)
3826  * (VF function number 0x2)
3827  */
3828 static int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base,
3829                     u32 number)
3830 {
3831         u32 max_q_num = qm->ctrl_qp_num;
3832
3833         if (base >= max_q_num || number > max_q_num ||
3834             (base + number) > max_q_num)
3835                 return -EINVAL;
3836
3837         return qm_set_sqc_cqc_vft(qm, fun_num, base, number);
3838 }
3839
3840 static void qm_init_eq_aeq_status(struct hisi_qm *qm)
3841 {
3842         struct hisi_qm_status *status = &qm->status;
3843
3844         status->eq_head = 0;
3845         status->aeq_head = 0;
3846         status->eqc_phase = true;
3847         status->aeqc_phase = true;
3848 }
3849
3850 static void qm_enable_eq_aeq_interrupts(struct hisi_qm *qm)
3851 {
3852         /* Clear eq/aeq interrupt source */
3853         qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0);
3854         qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
3855
3856         writel(0x0, qm->io_base + QM_VF_EQ_INT_MASK);
3857         writel(0x0, qm->io_base + QM_VF_AEQ_INT_MASK);
3858 }
3859
3860 static void qm_disable_eq_aeq_interrupts(struct hisi_qm *qm)
3861 {
3862         writel(0x1, qm->io_base + QM_VF_EQ_INT_MASK);
3863         writel(0x1, qm->io_base + QM_VF_AEQ_INT_MASK);
3864 }
3865
3866 static int qm_eq_ctx_cfg(struct hisi_qm *qm)
3867 {
3868         struct device *dev = &qm->pdev->dev;
3869         struct qm_eqc *eqc;
3870         dma_addr_t eqc_dma;
3871         int ret;
3872
3873         eqc = kzalloc(sizeof(struct qm_eqc), GFP_KERNEL);
3874         if (!eqc)
3875                 return -ENOMEM;
3876
3877         eqc->base_l = cpu_to_le32(lower_32_bits(qm->eqe_dma));
3878         eqc->base_h = cpu_to_le32(upper_32_bits(qm->eqe_dma));
3879         if (qm->ver == QM_HW_V1)
3880                 eqc->dw3 = cpu_to_le32(QM_EQE_AEQE_SIZE);
3881         eqc->dw6 = cpu_to_le32(((u32)qm->eq_depth - 1) | (1 << QM_EQC_PHASE_SHIFT));
3882
3883         eqc_dma = dma_map_single(dev, eqc, sizeof(struct qm_eqc),
3884                                  DMA_TO_DEVICE);
3885         if (dma_mapping_error(dev, eqc_dma)) {
3886                 kfree(eqc);
3887                 return -ENOMEM;
3888         }
3889
3890         ret = hisi_qm_mb(qm, QM_MB_CMD_EQC, eqc_dma, 0, 0);
3891         dma_unmap_single(dev, eqc_dma, sizeof(struct qm_eqc), DMA_TO_DEVICE);
3892         kfree(eqc);
3893
3894         return ret;
3895 }
3896
3897 static int qm_aeq_ctx_cfg(struct hisi_qm *qm)
3898 {
3899         struct device *dev = &qm->pdev->dev;
3900         struct qm_aeqc *aeqc;
3901         dma_addr_t aeqc_dma;
3902         int ret;
3903
3904         aeqc = kzalloc(sizeof(struct qm_aeqc), GFP_KERNEL);
3905         if (!aeqc)
3906                 return -ENOMEM;
3907
3908         aeqc->base_l = cpu_to_le32(lower_32_bits(qm->aeqe_dma));
3909         aeqc->base_h = cpu_to_le32(upper_32_bits(qm->aeqe_dma));
3910         aeqc->dw6 = cpu_to_le32(((u32)qm->aeq_depth - 1) | (1 << QM_EQC_PHASE_SHIFT));
3911
3912         aeqc_dma = dma_map_single(dev, aeqc, sizeof(struct qm_aeqc),
3913                                   DMA_TO_DEVICE);
3914         if (dma_mapping_error(dev, aeqc_dma)) {
3915                 kfree(aeqc);
3916                 return -ENOMEM;
3917         }
3918
3919         ret = hisi_qm_mb(qm, QM_MB_CMD_AEQC, aeqc_dma, 0, 0);
3920         dma_unmap_single(dev, aeqc_dma, sizeof(struct qm_aeqc), DMA_TO_DEVICE);
3921         kfree(aeqc);
3922
3923         return ret;
3924 }
3925
3926 static int qm_eq_aeq_ctx_cfg(struct hisi_qm *qm)
3927 {
3928         struct device *dev = &qm->pdev->dev;
3929         int ret;
3930
3931         qm_init_eq_aeq_status(qm);
3932
3933         ret = qm_eq_ctx_cfg(qm);
3934         if (ret) {
3935                 dev_err(dev, "Set eqc failed!\n");
3936                 return ret;
3937         }
3938
3939         return qm_aeq_ctx_cfg(qm);
3940 }
3941
3942 static int __hisi_qm_start(struct hisi_qm *qm)
3943 {
3944         int ret;
3945
3946         WARN_ON(!qm->qdma.va);
3947
3948         if (qm->fun_type == QM_HW_PF) {
3949                 ret = hisi_qm_set_vft(qm, 0, qm->qp_base, qm->qp_num);
3950                 if (ret)
3951                         return ret;
3952         }
3953
3954         ret = qm_eq_aeq_ctx_cfg(qm);
3955         if (ret)
3956                 return ret;
3957
3958         ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0);
3959         if (ret)
3960                 return ret;
3961
3962         ret = hisi_qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0);
3963         if (ret)
3964                 return ret;
3965
3966         qm_init_prefetch(qm);
3967         qm_enable_eq_aeq_interrupts(qm);
3968
3969         return 0;
3970 }
3971
3972 /**
3973  * hisi_qm_start() - start qm
3974  * @qm: The qm to be started.
3975  *
3976  * This function starts a qm, then we can allocate qp from this qm.
3977  */
3978 int hisi_qm_start(struct hisi_qm *qm)
3979 {
3980         struct device *dev = &qm->pdev->dev;
3981         int ret = 0;
3982
3983         down_write(&qm->qps_lock);
3984
3985         if (!qm_avail_state(qm, QM_START)) {
3986                 up_write(&qm->qps_lock);
3987                 return -EPERM;
3988         }
3989
3990         dev_dbg(dev, "qm start with %u queue pairs\n", qm->qp_num);
3991
3992         if (!qm->qp_num) {
3993                 dev_err(dev, "qp_num should not be 0\n");
3994                 ret = -EINVAL;
3995                 goto err_unlock;
3996         }
3997
3998         ret = __hisi_qm_start(qm);
3999         if (!ret)
4000                 atomic_set(&qm->status.flags, QM_START);
4001
4002         hisi_qm_set_state(qm, QM_READY);
4003 err_unlock:
4004         up_write(&qm->qps_lock);
4005         return ret;
4006 }
4007 EXPORT_SYMBOL_GPL(hisi_qm_start);
4008
4009 static int qm_restart(struct hisi_qm *qm)
4010 {
4011         struct device *dev = &qm->pdev->dev;
4012         struct hisi_qp *qp;
4013         int ret, i;
4014
4015         ret = hisi_qm_start(qm);
4016         if (ret < 0)
4017                 return ret;
4018
4019         down_write(&qm->qps_lock);
4020         for (i = 0; i < qm->qp_num; i++) {
4021                 qp = &qm->qp_array[i];
4022                 if (atomic_read(&qp->qp_status.flags) == QP_STOP &&
4023                     qp->is_resetting == true) {
4024                         ret = qm_start_qp_nolock(qp, 0);
4025                         if (ret < 0) {
4026                                 dev_err(dev, "Failed to start qp%d!\n", i);
4027
4028                                 up_write(&qm->qps_lock);
4029                                 return ret;
4030                         }
4031                         qp->is_resetting = false;
4032                 }
4033         }
4034         up_write(&qm->qps_lock);
4035
4036         return 0;
4037 }
4038
4039 /* Stop started qps in reset flow */
4040 static int qm_stop_started_qp(struct hisi_qm *qm)
4041 {
4042         struct device *dev = &qm->pdev->dev;
4043         struct hisi_qp *qp;
4044         int i, ret;
4045
4046         for (i = 0; i < qm->qp_num; i++) {
4047                 qp = &qm->qp_array[i];
4048                 if (qp && atomic_read(&qp->qp_status.flags) == QP_START) {
4049                         qp->is_resetting = true;
4050                         ret = qm_stop_qp_nolock(qp);
4051                         if (ret < 0) {
4052                                 dev_err(dev, "Failed to stop qp%d!\n", i);
4053                                 return ret;
4054                         }
4055                 }
4056         }
4057
4058         return 0;
4059 }
4060
4061
4062 /**
4063  * qm_clear_queues() - Clear all queues memory in a qm.
4064  * @qm: The qm in which the queues will be cleared.
4065  *
4066  * This function clears all queues memory in a qm. Reset of accelerator can
4067  * use this to clear queues.
4068  */
4069 static void qm_clear_queues(struct hisi_qm *qm)
4070 {
4071         struct hisi_qp *qp;
4072         int i;
4073
4074         for (i = 0; i < qm->qp_num; i++) {
4075                 qp = &qm->qp_array[i];
4076                 if (qp->is_in_kernel && qp->is_resetting)
4077                         memset(qp->qdma.va, 0, qp->qdma.size);
4078         }
4079
4080         memset(qm->qdma.va, 0, qm->qdma.size);
4081 }
4082
4083 /**
4084  * hisi_qm_stop() - Stop a qm.
4085  * @qm: The qm which will be stopped.
4086  * @r: The reason to stop qm.
4087  *
4088  * This function stops qm and its qps, then qm can not accept request.
4089  * Related resources are not released at this state, we can use hisi_qm_start
4090  * to let qm start again.
4091  */
4092 int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r)
4093 {
4094         struct device *dev = &qm->pdev->dev;
4095         int ret = 0;
4096
4097         down_write(&qm->qps_lock);
4098
4099         qm->status.stop_reason = r;
4100         if (!qm_avail_state(qm, QM_STOP)) {
4101                 ret = -EPERM;
4102                 goto err_unlock;
4103         }
4104
4105         if (qm->status.stop_reason == QM_SOFT_RESET ||
4106             qm->status.stop_reason == QM_FLR) {
4107                 hisi_qm_set_hw_reset(qm, QM_RESET_STOP_TX_OFFSET);
4108                 ret = qm_stop_started_qp(qm);
4109                 if (ret < 0) {
4110                         dev_err(dev, "Failed to stop started qp!\n");
4111                         goto err_unlock;
4112                 }
4113                 hisi_qm_set_hw_reset(qm, QM_RESET_STOP_RX_OFFSET);
4114         }
4115
4116         qm_disable_eq_aeq_interrupts(qm);
4117         if (qm->fun_type == QM_HW_PF) {
4118                 ret = hisi_qm_set_vft(qm, 0, 0, 0);
4119                 if (ret < 0) {
4120                         dev_err(dev, "Failed to set vft!\n");
4121                         ret = -EBUSY;
4122                         goto err_unlock;
4123                 }
4124         }
4125
4126         qm_clear_queues(qm);
4127         atomic_set(&qm->status.flags, QM_STOP);
4128
4129 err_unlock:
4130         up_write(&qm->qps_lock);
4131         return ret;
4132 }
4133 EXPORT_SYMBOL_GPL(hisi_qm_stop);
4134
4135 static ssize_t qm_status_read(struct file *filp, char __user *buffer,
4136                               size_t count, loff_t *pos)
4137 {
4138         struct hisi_qm *qm = filp->private_data;
4139         char buf[QM_DBG_READ_LEN];
4140         int val, len;
4141
4142         val = atomic_read(&qm->status.flags);
4143         len = scnprintf(buf, QM_DBG_READ_LEN, "%s\n", qm_s[val]);
4144
4145         return simple_read_from_buffer(buffer, count, pos, buf, len);
4146 }
4147
4148 static const struct file_operations qm_status_fops = {
4149         .owner = THIS_MODULE,
4150         .open = simple_open,
4151         .read = qm_status_read,
4152 };
4153
4154 static int qm_debugfs_atomic64_set(void *data, u64 val)
4155 {
4156         if (val)
4157                 return -EINVAL;
4158
4159         atomic64_set((atomic64_t *)data, 0);
4160
4161         return 0;
4162 }
4163
4164 static int qm_debugfs_atomic64_get(void *data, u64 *val)
4165 {
4166         *val = atomic64_read((atomic64_t *)data);
4167
4168         return 0;
4169 }
4170
4171 DEFINE_DEBUGFS_ATTRIBUTE(qm_atomic64_ops, qm_debugfs_atomic64_get,
4172                          qm_debugfs_atomic64_set, "%llu\n");
4173
4174 static void qm_hw_error_init(struct hisi_qm *qm)
4175 {
4176         if (!qm->ops->hw_error_init) {
4177                 dev_err(&qm->pdev->dev, "QM doesn't support hw error handling!\n");
4178                 return;
4179         }
4180
4181         qm->ops->hw_error_init(qm);
4182 }
4183
4184 static void qm_hw_error_uninit(struct hisi_qm *qm)
4185 {
4186         if (!qm->ops->hw_error_uninit) {
4187                 dev_err(&qm->pdev->dev, "Unexpected QM hw error uninit!\n");
4188                 return;
4189         }
4190
4191         qm->ops->hw_error_uninit(qm);
4192 }
4193
4194 static enum acc_err_result qm_hw_error_handle(struct hisi_qm *qm)
4195 {
4196         if (!qm->ops->hw_error_handle) {
4197                 dev_err(&qm->pdev->dev, "QM doesn't support hw error report!\n");
4198                 return ACC_ERR_NONE;
4199         }
4200
4201         return qm->ops->hw_error_handle(qm);
4202 }
4203
4204 /**
4205  * hisi_qm_dev_err_init() - Initialize device error configuration.
4206  * @qm: The qm for which we want to do error initialization.
4207  *
4208  * Initialize QM and device error related configuration.
4209  */
4210 void hisi_qm_dev_err_init(struct hisi_qm *qm)
4211 {
4212         if (qm->fun_type == QM_HW_VF)
4213                 return;
4214
4215         qm_hw_error_init(qm);
4216
4217         if (!qm->err_ini->hw_err_enable) {
4218                 dev_err(&qm->pdev->dev, "Device doesn't support hw error init!\n");
4219                 return;
4220         }
4221         qm->err_ini->hw_err_enable(qm);
4222 }
4223 EXPORT_SYMBOL_GPL(hisi_qm_dev_err_init);
4224
4225 /**
4226  * hisi_qm_dev_err_uninit() - Uninitialize device error configuration.
4227  * @qm: The qm for which we want to do error uninitialization.
4228  *
4229  * Uninitialize QM and device error related configuration.
4230  */
4231 void hisi_qm_dev_err_uninit(struct hisi_qm *qm)
4232 {
4233         if (qm->fun_type == QM_HW_VF)
4234                 return;
4235
4236         qm_hw_error_uninit(qm);
4237
4238         if (!qm->err_ini->hw_err_disable) {
4239                 dev_err(&qm->pdev->dev, "Unexpected device hw error uninit!\n");
4240                 return;
4241         }
4242         qm->err_ini->hw_err_disable(qm);
4243 }
4244 EXPORT_SYMBOL_GPL(hisi_qm_dev_err_uninit);
4245
4246 /**
4247  * hisi_qm_free_qps() - free multiple queue pairs.
4248  * @qps: The queue pairs need to be freed.
4249  * @qp_num: The num of queue pairs.
4250  */
4251 void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num)
4252 {
4253         int i;
4254
4255         if (!qps || qp_num <= 0)
4256                 return;
4257
4258         for (i = qp_num - 1; i >= 0; i--)
4259                 hisi_qm_release_qp(qps[i]);
4260 }
4261 EXPORT_SYMBOL_GPL(hisi_qm_free_qps);
4262
4263 static void free_list(struct list_head *head)
4264 {
4265         struct hisi_qm_resource *res, *tmp;
4266
4267         list_for_each_entry_safe(res, tmp, head, list) {
4268                 list_del(&res->list);
4269                 kfree(res);
4270         }
4271 }
4272
4273 static int hisi_qm_sort_devices(int node, struct list_head *head,
4274                                 struct hisi_qm_list *qm_list)
4275 {
4276         struct hisi_qm_resource *res, *tmp;
4277         struct hisi_qm *qm;
4278         struct list_head *n;
4279         struct device *dev;
4280         int dev_node = 0;
4281
4282         list_for_each_entry(qm, &qm_list->list, list) {
4283                 dev = &qm->pdev->dev;
4284
4285                 if (IS_ENABLED(CONFIG_NUMA)) {
4286                         dev_node = dev_to_node(dev);
4287                         if (dev_node < 0)
4288                                 dev_node = 0;
4289                 }
4290
4291                 res = kzalloc(sizeof(*res), GFP_KERNEL);
4292                 if (!res)
4293                         return -ENOMEM;
4294
4295                 res->qm = qm;
4296                 res->distance = node_distance(dev_node, node);
4297                 n = head;
4298                 list_for_each_entry(tmp, head, list) {
4299                         if (res->distance < tmp->distance) {
4300                                 n = &tmp->list;
4301                                 break;
4302                         }
4303                 }
4304                 list_add_tail(&res->list, n);
4305         }
4306
4307         return 0;
4308 }
4309
4310 /**
4311  * hisi_qm_alloc_qps_node() - Create multiple queue pairs.
4312  * @qm_list: The list of all available devices.
4313  * @qp_num: The number of queue pairs need created.
4314  * @alg_type: The algorithm type.
4315  * @node: The numa node.
4316  * @qps: The queue pairs need created.
4317  *
4318  * This function will sort all available device according to numa distance.
4319  * Then try to create all queue pairs from one device, if all devices do
4320  * not meet the requirements will return error.
4321  */
4322 int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
4323                            u8 alg_type, int node, struct hisi_qp **qps)
4324 {
4325         struct hisi_qm_resource *tmp;
4326         int ret = -ENODEV;
4327         LIST_HEAD(head);
4328         int i;
4329
4330         if (!qps || !qm_list || qp_num <= 0)
4331                 return -EINVAL;
4332
4333         mutex_lock(&qm_list->lock);
4334         if (hisi_qm_sort_devices(node, &head, qm_list)) {
4335                 mutex_unlock(&qm_list->lock);
4336                 goto err;
4337         }
4338
4339         list_for_each_entry(tmp, &head, list) {
4340                 for (i = 0; i < qp_num; i++) {
4341                         qps[i] = hisi_qm_create_qp(tmp->qm, alg_type);
4342                         if (IS_ERR(qps[i])) {
4343                                 hisi_qm_free_qps(qps, i);
4344                                 break;
4345                         }
4346                 }
4347
4348                 if (i == qp_num) {
4349                         ret = 0;
4350                         break;
4351                 }
4352         }
4353
4354         mutex_unlock(&qm_list->lock);
4355         if (ret)
4356                 pr_info("Failed to create qps, node[%d], alg[%u], qp[%d]!\n",
4357                         node, alg_type, qp_num);
4358
4359 err:
4360         free_list(&head);
4361         return ret;
4362 }
4363 EXPORT_SYMBOL_GPL(hisi_qm_alloc_qps_node);
4364
4365 static int qm_vf_q_assign(struct hisi_qm *qm, u32 num_vfs)
4366 {
4367         u32 remain_q_num, vfs_q_num, act_q_num, q_num, i, j;
4368         u32 max_qp_num = qm->max_qp_num;
4369         u32 q_base = qm->qp_num;
4370         int ret;
4371
4372         if (!num_vfs)
4373                 return -EINVAL;
4374
4375         vfs_q_num = qm->ctrl_qp_num - qm->qp_num;
4376
4377         /* If vfs_q_num is less than num_vfs, return error. */
4378         if (vfs_q_num < num_vfs)
4379                 return -EINVAL;
4380
4381         q_num = vfs_q_num / num_vfs;
4382         remain_q_num = vfs_q_num % num_vfs;
4383
4384         for (i = num_vfs; i > 0; i--) {
4385                 /*
4386                  * if q_num + remain_q_num > max_qp_num in last vf, divide the
4387                  * remaining queues equally.
4388                  */
4389                 if (i == num_vfs && q_num + remain_q_num <= max_qp_num) {
4390                         act_q_num = q_num + remain_q_num;
4391                         remain_q_num = 0;
4392                 } else if (remain_q_num > 0) {
4393                         act_q_num = q_num + 1;
4394                         remain_q_num--;
4395                 } else {
4396                         act_q_num = q_num;
4397                 }
4398
4399                 act_q_num = min_t(int, act_q_num, max_qp_num);
4400                 ret = hisi_qm_set_vft(qm, i, q_base, act_q_num);
4401                 if (ret) {
4402                         for (j = num_vfs; j > i; j--)
4403                                 hisi_qm_set_vft(qm, j, 0, 0);
4404                         return ret;
4405                 }
4406                 q_base += act_q_num;
4407         }
4408
4409         return 0;
4410 }
4411
4412 static int qm_clear_vft_config(struct hisi_qm *qm)
4413 {
4414         int ret;
4415         u32 i;
4416
4417         for (i = 1; i <= qm->vfs_num; i++) {
4418                 ret = hisi_qm_set_vft(qm, i, 0, 0);
4419                 if (ret)
4420                         return ret;
4421         }
4422         qm->vfs_num = 0;
4423
4424         return 0;
4425 }
4426
4427 static int qm_func_shaper_enable(struct hisi_qm *qm, u32 fun_index, u32 qos)
4428 {
4429         struct device *dev = &qm->pdev->dev;
4430         u32 ir = qos * QM_QOS_RATE;
4431         int ret, total_vfs, i;
4432
4433         total_vfs = pci_sriov_get_totalvfs(qm->pdev);
4434         if (fun_index > total_vfs)
4435                 return -EINVAL;
4436
4437         qm->factor[fun_index].func_qos = qos;
4438
4439         ret = qm_get_shaper_para(ir, &qm->factor[fun_index]);
4440         if (ret) {
4441                 dev_err(dev, "failed to calculate shaper parameter!\n");
4442                 return -EINVAL;
4443         }
4444
4445         for (i = ALG_TYPE_0; i <= ALG_TYPE_1; i++) {
4446                 /* The base number of queue reuse for different alg type */
4447                 ret = qm_set_vft_common(qm, SHAPER_VFT, fun_index, i, 1);
4448                 if (ret) {
4449                         dev_err(dev, "type: %d, failed to set shaper vft!\n", i);
4450                         return -EINVAL;
4451                 }
4452         }
4453
4454         return 0;
4455 }
4456
4457 static u32 qm_get_shaper_vft_qos(struct hisi_qm *qm, u32 fun_index)
4458 {
4459         u64 cir_u = 0, cir_b = 0, cir_s = 0;
4460         u64 shaper_vft, ir_calc, ir;
4461         unsigned int val;
4462         u32 error_rate;
4463         int ret;
4464
4465         ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
4466                                          val & BIT(0), POLL_PERIOD,
4467                                          POLL_TIMEOUT);
4468         if (ret)
4469                 return 0;
4470
4471         writel(0x1, qm->io_base + QM_VFT_CFG_OP_WR);
4472         writel(SHAPER_VFT, qm->io_base + QM_VFT_CFG_TYPE);
4473         writel(fun_index, qm->io_base + QM_VFT_CFG);
4474
4475         writel(0x0, qm->io_base + QM_VFT_CFG_RDY);
4476         writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);
4477
4478         ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
4479                                          val & BIT(0), POLL_PERIOD,
4480                                          POLL_TIMEOUT);
4481         if (ret)
4482                 return 0;
4483
4484         shaper_vft = readl(qm->io_base + QM_VFT_CFG_DATA_L) |
4485                   ((u64)readl(qm->io_base + QM_VFT_CFG_DATA_H) << 32);
4486
4487         cir_b = shaper_vft & QM_SHAPER_CIR_B_MASK;
4488         cir_u = shaper_vft & QM_SHAPER_CIR_U_MASK;
4489         cir_u = cir_u >> QM_SHAPER_FACTOR_CIR_U_SHIFT;
4490
4491         cir_s = shaper_vft & QM_SHAPER_CIR_S_MASK;
4492         cir_s = cir_s >> QM_SHAPER_FACTOR_CIR_S_SHIFT;
4493
4494         ir_calc = acc_shaper_para_calc(cir_b, cir_u, cir_s);
4495
4496         ir = qm->factor[fun_index].func_qos * QM_QOS_RATE;
4497
4498         error_rate = QM_QOS_EXPAND_RATE * (u32)abs(ir_calc - ir) / ir;
4499         if (error_rate > QM_QOS_MIN_ERROR_RATE) {
4500                 pci_err(qm->pdev, "error_rate: %u, get function qos is error!\n", error_rate);
4501                 return 0;
4502         }
4503
4504         return ir;
4505 }
4506
4507 static void qm_vf_get_qos(struct hisi_qm *qm, u32 fun_num)
4508 {
4509         struct device *dev = &qm->pdev->dev;
4510         u64 mb_cmd;
4511         u32 qos;
4512         int ret;
4513
4514         qos = qm_get_shaper_vft_qos(qm, fun_num);
4515         if (!qos) {
4516                 dev_err(dev, "function(%u) failed to get qos by PF!\n", fun_num);
4517                 return;
4518         }
4519
4520         mb_cmd = QM_PF_SET_QOS | (u64)qos << QM_MB_CMD_DATA_SHIFT;
4521         ret = qm_ping_single_vf(qm, mb_cmd, fun_num);
4522         if (ret)
4523                 dev_err(dev, "failed to send cmd to VF(%u)!\n", fun_num);
4524 }
4525
4526 static int qm_vf_read_qos(struct hisi_qm *qm)
4527 {
4528         int cnt = 0;
4529         int ret = -EINVAL;
4530
4531         /* reset mailbox qos val */
4532         qm->mb_qos = 0;
4533
4534         /* vf ping pf to get function qos */
4535         ret = qm_ping_pf(qm, QM_VF_GET_QOS);
4536         if (ret) {
4537                 pci_err(qm->pdev, "failed to send cmd to PF to get qos!\n");
4538                 return ret;
4539         }
4540
4541         while (true) {
4542                 msleep(QM_WAIT_DST_ACK);
4543                 if (qm->mb_qos)
4544                         break;
4545
4546                 if (++cnt > QM_MAX_VF_WAIT_COUNT) {
4547                         pci_err(qm->pdev, "PF ping VF timeout!\n");
4548                         return  -ETIMEDOUT;
4549                 }
4550         }
4551
4552         return ret;
4553 }
4554
4555 static ssize_t qm_algqos_read(struct file *filp, char __user *buf,
4556                                size_t count, loff_t *pos)
4557 {
4558         struct hisi_qm *qm = filp->private_data;
4559         char tbuf[QM_DBG_READ_LEN];
4560         u32 qos_val, ir;
4561         int ret;
4562
4563         ret = hisi_qm_get_dfx_access(qm);
4564         if (ret)
4565                 return ret;
4566
4567         /* Mailbox and reset cannot be operated at the same time */
4568         if (test_and_set_bit(QM_RESETTING, &qm->misc_ctl)) {
4569                 pci_err(qm->pdev, "dev resetting, read alg qos failed!\n");
4570                 ret = -EAGAIN;
4571                 goto err_put_dfx_access;
4572         }
4573
4574         if (qm->fun_type == QM_HW_PF) {
4575                 ir = qm_get_shaper_vft_qos(qm, 0);
4576         } else {
4577                 ret = qm_vf_read_qos(qm);
4578                 if (ret)
4579                         goto err_get_status;
4580                 ir = qm->mb_qos;
4581         }
4582
4583         qos_val = ir / QM_QOS_RATE;
4584         ret = scnprintf(tbuf, QM_DBG_READ_LEN, "%u\n", qos_val);
4585
4586         ret =  simple_read_from_buffer(buf, count, pos, tbuf, ret);
4587
4588 err_get_status:
4589         clear_bit(QM_RESETTING, &qm->misc_ctl);
4590 err_put_dfx_access:
4591         hisi_qm_put_dfx_access(qm);
4592         return ret;
4593 }
4594
4595 static ssize_t qm_qos_value_init(const char *buf, unsigned long *val)
4596 {
4597         int buflen = strlen(buf);
4598         int ret, i;
4599
4600         for (i = 0; i < buflen; i++) {
4601                 if (!isdigit(buf[i]))
4602                         return -EINVAL;
4603         }
4604
4605         ret = sscanf(buf, "%lu", val);
4606         if (ret != QM_QOS_VAL_NUM)
4607                 return -EINVAL;
4608
4609         return 0;
4610 }
4611
4612 static ssize_t qm_get_qos_value(struct hisi_qm *qm, const char *buf,
4613                                unsigned long *val,
4614                                unsigned int *fun_index)
4615 {
4616         char tbuf_bdf[QM_DBG_READ_LEN] = {0};
4617         char val_buf[QM_QOS_VAL_MAX_LEN] = {0};
4618         u32 tmp1, device, function;
4619         int ret, bus;
4620
4621         ret = sscanf(buf, "%s %s", tbuf_bdf, val_buf);
4622         if (ret != QM_QOS_PARAM_NUM)
4623                 return -EINVAL;
4624
4625         ret = qm_qos_value_init(val_buf, val);
4626         if (ret || *val == 0 || *val > QM_QOS_MAX_VAL) {
4627                 pci_err(qm->pdev, "input qos value is error, please set 1~1000!\n");
4628                 return -EINVAL;
4629         }
4630
4631         ret = sscanf(tbuf_bdf, "%u:%x:%u.%u", &tmp1, &bus, &device, &function);
4632         if (ret != QM_QOS_BDF_PARAM_NUM) {
4633                 pci_err(qm->pdev, "input pci bdf value is error!\n");
4634                 return -EINVAL;
4635         }
4636
4637         *fun_index = PCI_DEVFN(device, function);
4638
4639         return 0;
4640 }
4641
4642 static ssize_t qm_algqos_write(struct file *filp, const char __user *buf,
4643                                size_t count, loff_t *pos)
4644 {
4645         struct hisi_qm *qm = filp->private_data;
4646         char tbuf[QM_DBG_READ_LEN];
4647         unsigned int fun_index;
4648         unsigned long val;
4649         int len, ret;
4650
4651         if (qm->fun_type == QM_HW_VF)
4652                 return -EINVAL;
4653
4654         if (*pos != 0)
4655                 return 0;
4656
4657         if (count >= QM_DBG_READ_LEN)
4658                 return -ENOSPC;
4659
4660         len = simple_write_to_buffer(tbuf, QM_DBG_READ_LEN - 1, pos, buf, count);
4661         if (len < 0)
4662                 return len;
4663
4664         tbuf[len] = '\0';
4665         ret = qm_get_qos_value(qm, tbuf, &val, &fun_index);
4666         if (ret)
4667                 return ret;
4668
4669         /* Mailbox and reset cannot be operated at the same time */
4670         if (test_and_set_bit(QM_RESETTING, &qm->misc_ctl)) {
4671                 pci_err(qm->pdev, "dev resetting, write alg qos failed!\n");
4672                 return -EAGAIN;
4673         }
4674
4675         ret = qm_pm_get_sync(qm);
4676         if (ret) {
4677                 ret = -EINVAL;
4678                 goto err_get_status;
4679         }
4680
4681         ret = qm_func_shaper_enable(qm, fun_index, val);
4682         if (ret) {
4683                 pci_err(qm->pdev, "failed to enable function shaper!\n");
4684                 ret = -EINVAL;
4685                 goto err_put_sync;
4686         }
4687
4688         pci_info(qm->pdev, "the qos value of function%u is set to %lu.\n",
4689                  fun_index, val);
4690         ret = count;
4691
4692 err_put_sync:
4693         qm_pm_put_sync(qm);
4694 err_get_status:
4695         clear_bit(QM_RESETTING, &qm->misc_ctl);
4696         return ret;
4697 }
4698
4699 static const struct file_operations qm_algqos_fops = {
4700         .owner = THIS_MODULE,
4701         .open = simple_open,
4702         .read = qm_algqos_read,
4703         .write = qm_algqos_write,
4704 };
4705
4706 /**
4707  * hisi_qm_set_algqos_init() - Initialize function qos debugfs files.
4708  * @qm: The qm for which we want to add debugfs files.
4709  *
4710  * Create function qos debugfs files, VF ping PF to get function qos.
4711  */
4712 static void hisi_qm_set_algqos_init(struct hisi_qm *qm)
4713 {
4714         if (qm->fun_type == QM_HW_PF)
4715                 debugfs_create_file("alg_qos", 0644, qm->debug.debug_root,
4716                                     qm, &qm_algqos_fops);
4717         else if (test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps))
4718                 debugfs_create_file("alg_qos", 0444, qm->debug.debug_root,
4719                                     qm, &qm_algqos_fops);
4720 }
4721
4722 /**
4723  * hisi_qm_debug_init() - Initialize qm related debugfs files.
4724  * @qm: The qm for which we want to add debugfs files.
4725  *
4726  * Create qm related debugfs files.
4727  */
4728 void hisi_qm_debug_init(struct hisi_qm *qm)
4729 {
4730         struct dfx_diff_registers *qm_regs = qm->debug.qm_diff_regs;
4731         struct qm_dfx *dfx = &qm->debug.dfx;
4732         struct dentry *qm_d;
4733         void *data;
4734         int i;
4735
4736         qm_d = debugfs_create_dir("qm", qm->debug.debug_root);
4737         qm->debug.qm_d = qm_d;
4738
4739         /* only show this in PF */
4740         if (qm->fun_type == QM_HW_PF) {
4741                 qm_create_debugfs_file(qm, qm->debug.debug_root, CURRENT_QM);
4742                 for (i = CURRENT_Q; i < DEBUG_FILE_NUM; i++)
4743                         qm_create_debugfs_file(qm, qm->debug.qm_d, i);
4744         }
4745
4746         if (qm_regs)
4747                 debugfs_create_file("diff_regs", 0444, qm->debug.qm_d,
4748                                         qm, &qm_diff_regs_fops);
4749
4750         debugfs_create_file("regs", 0444, qm->debug.qm_d, qm, &qm_regs_fops);
4751
4752         debugfs_create_file("cmd", 0600, qm->debug.qm_d, qm, &qm_cmd_fops);
4753
4754         debugfs_create_file("status", 0444, qm->debug.qm_d, qm,
4755                         &qm_status_fops);
4756         for (i = 0; i < ARRAY_SIZE(qm_dfx_files); i++) {
4757                 data = (atomic64_t *)((uintptr_t)dfx + qm_dfx_files[i].offset);
4758                 debugfs_create_file(qm_dfx_files[i].name,
4759                         0644,
4760                         qm_d,
4761                         data,
4762                         &qm_atomic64_ops);
4763         }
4764
4765         if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps))
4766                 hisi_qm_set_algqos_init(qm);
4767 }
4768 EXPORT_SYMBOL_GPL(hisi_qm_debug_init);
4769
4770 /**
4771  * hisi_qm_debug_regs_clear() - clear qm debug related registers.
4772  * @qm: The qm for which we want to clear its debug registers.
4773  */
4774 void hisi_qm_debug_regs_clear(struct hisi_qm *qm)
4775 {
4776         const struct debugfs_reg32 *regs;
4777         int i;
4778
4779         /* clear current_qm */
4780         writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);
4781         writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);
4782
4783         /* clear current_q */
4784         writel(0x0, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
4785         writel(0x0, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
4786
4787         /*
4788          * these registers are reading and clearing, so clear them after
4789          * reading them.
4790          */
4791         writel(0x1, qm->io_base + QM_DFX_CNT_CLR_CE);
4792
4793         regs = qm_dfx_regs;
4794         for (i = 0; i < CNT_CYC_REGS_NUM; i++) {
4795                 readl(qm->io_base + regs->offset);
4796                 regs++;
4797         }
4798
4799         /* clear clear_enable */
4800         writel(0x0, qm->io_base + QM_DFX_CNT_CLR_CE);
4801 }
4802 EXPORT_SYMBOL_GPL(hisi_qm_debug_regs_clear);
4803
4804 static void hisi_qm_init_vf_qos(struct hisi_qm *qm, int total_func)
4805 {
4806         int i;
4807
4808         for (i = 1; i <= total_func; i++)
4809                 qm->factor[i].func_qos = QM_QOS_MAX_VAL;
4810 }
4811
4812 /**
4813  * hisi_qm_sriov_enable() - enable virtual functions
4814  * @pdev: the PCIe device
4815  * @max_vfs: the number of virtual functions to enable
4816  *
4817  * Returns the number of enabled VFs. If there are VFs enabled already or
4818  * max_vfs is more than the total number of device can be enabled, returns
4819  * failure.
4820  */
4821 int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs)
4822 {
4823         struct hisi_qm *qm = pci_get_drvdata(pdev);
4824         int pre_existing_vfs, num_vfs, total_vfs, ret;
4825
4826         ret = qm_pm_get_sync(qm);
4827         if (ret)
4828                 return ret;
4829
4830         total_vfs = pci_sriov_get_totalvfs(pdev);
4831         pre_existing_vfs = pci_num_vf(pdev);
4832         if (pre_existing_vfs) {
4833                 pci_err(pdev, "%d VFs already enabled. Please disable pre-enabled VFs!\n",
4834                         pre_existing_vfs);
4835                 goto err_put_sync;
4836         }
4837
4838         if (max_vfs > total_vfs) {
4839                 pci_err(pdev, "%d VFs is more than total VFs %d!\n", max_vfs, total_vfs);
4840                 ret = -ERANGE;
4841                 goto err_put_sync;
4842         }
4843
4844         num_vfs = max_vfs;
4845
4846         if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps))
4847                 hisi_qm_init_vf_qos(qm, num_vfs);
4848
4849         ret = qm_vf_q_assign(qm, num_vfs);
4850         if (ret) {
4851                 pci_err(pdev, "Can't assign queues for VF!\n");
4852                 goto err_put_sync;
4853         }
4854
4855         qm->vfs_num = num_vfs;
4856
4857         ret = pci_enable_sriov(pdev, num_vfs);
4858         if (ret) {
4859                 pci_err(pdev, "Can't enable VF!\n");
4860                 qm_clear_vft_config(qm);
4861                 goto err_put_sync;
4862         }
4863
4864         pci_info(pdev, "VF enabled, vfs_num(=%d)!\n", num_vfs);
4865
4866         return num_vfs;
4867
4868 err_put_sync:
4869         qm_pm_put_sync(qm);
4870         return ret;
4871 }
4872 EXPORT_SYMBOL_GPL(hisi_qm_sriov_enable);
4873
4874 /**
4875  * hisi_qm_sriov_disable - disable virtual functions
4876  * @pdev: the PCI device.
4877  * @is_frozen: true when all the VFs are frozen.
4878  *
4879  * Return failure if there are VFs assigned already or VF is in used.
4880  */
4881 int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen)
4882 {
4883         struct hisi_qm *qm = pci_get_drvdata(pdev);
4884         int ret;
4885
4886         if (pci_vfs_assigned(pdev)) {
4887                 pci_err(pdev, "Failed to disable VFs as VFs are assigned!\n");
4888                 return -EPERM;
4889         }
4890
4891         /* While VF is in used, SRIOV cannot be disabled. */
4892         if (!is_frozen && qm_try_frozen_vfs(pdev, qm->qm_list)) {
4893                 pci_err(pdev, "Task is using its VF!\n");
4894                 return -EBUSY;
4895         }
4896
4897         pci_disable_sriov(pdev);
4898
4899         ret = qm_clear_vft_config(qm);
4900         if (ret)
4901                 return ret;
4902
4903         qm_pm_put_sync(qm);
4904
4905         return 0;
4906 }
4907 EXPORT_SYMBOL_GPL(hisi_qm_sriov_disable);
4908
4909 /**
4910  * hisi_qm_sriov_configure - configure the number of VFs
4911  * @pdev: The PCI device
4912  * @num_vfs: The number of VFs need enabled
4913  *
4914  * Enable SR-IOV according to num_vfs, 0 means disable.
4915  */
4916 int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs)
4917 {
4918         if (num_vfs == 0)
4919                 return hisi_qm_sriov_disable(pdev, false);
4920         else
4921                 return hisi_qm_sriov_enable(pdev, num_vfs);
4922 }
4923 EXPORT_SYMBOL_GPL(hisi_qm_sriov_configure);
4924
4925 static enum acc_err_result qm_dev_err_handle(struct hisi_qm *qm)
4926 {
4927         u32 err_sts;
4928
4929         if (!qm->err_ini->get_dev_hw_err_status) {
4930                 dev_err(&qm->pdev->dev, "Device doesn't support get hw error status!\n");
4931                 return ACC_ERR_NONE;
4932         }
4933
4934         /* get device hardware error status */
4935         err_sts = qm->err_ini->get_dev_hw_err_status(qm);
4936         if (err_sts) {
4937                 if (err_sts & qm->err_info.ecc_2bits_mask)
4938                         qm->err_status.is_dev_ecc_mbit = true;
4939
4940                 if (qm->err_ini->log_dev_hw_err)
4941                         qm->err_ini->log_dev_hw_err(qm, err_sts);
4942
4943                 if (err_sts & qm->err_info.dev_reset_mask)
4944                         return ACC_ERR_NEED_RESET;
4945
4946                 if (qm->err_ini->clear_dev_hw_err_status)
4947                         qm->err_ini->clear_dev_hw_err_status(qm, err_sts);
4948         }
4949
4950         return ACC_ERR_RECOVERED;
4951 }
4952
4953 static enum acc_err_result qm_process_dev_error(struct hisi_qm *qm)
4954 {
4955         enum acc_err_result qm_ret, dev_ret;
4956
4957         /* log qm error */
4958         qm_ret = qm_hw_error_handle(qm);
4959
4960         /* log device error */
4961         dev_ret = qm_dev_err_handle(qm);
4962
4963         return (qm_ret == ACC_ERR_NEED_RESET ||
4964                 dev_ret == ACC_ERR_NEED_RESET) ?
4965                 ACC_ERR_NEED_RESET : ACC_ERR_RECOVERED;
4966 }
4967
4968 /**
4969  * hisi_qm_dev_err_detected() - Get device and qm error status then log it.
4970  * @pdev: The PCI device which need report error.
4971  * @state: The connectivity between CPU and device.
4972  *
4973  * We register this function into PCIe AER handlers, It will report device or
4974  * qm hardware error status when error occur.
4975  */
4976 pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
4977                                           pci_channel_state_t state)
4978 {
4979         struct hisi_qm *qm = pci_get_drvdata(pdev);
4980         enum acc_err_result ret;
4981
4982         if (pdev->is_virtfn)
4983                 return PCI_ERS_RESULT_NONE;
4984
4985         pci_info(pdev, "PCI error detected, state(=%u)!!\n", state);
4986         if (state == pci_channel_io_perm_failure)
4987                 return PCI_ERS_RESULT_DISCONNECT;
4988
4989         ret = qm_process_dev_error(qm);
4990         if (ret == ACC_ERR_NEED_RESET)
4991                 return PCI_ERS_RESULT_NEED_RESET;
4992
4993         return PCI_ERS_RESULT_RECOVERED;
4994 }
4995 EXPORT_SYMBOL_GPL(hisi_qm_dev_err_detected);
4996
4997 static int qm_check_req_recv(struct hisi_qm *qm)
4998 {
4999         struct pci_dev *pdev = qm->pdev;
5000         int ret;
5001         u32 val;
5002
5003         if (qm->ver >= QM_HW_V3)
5004                 return 0;
5005
5006         writel(ACC_VENDOR_ID_VALUE, qm->io_base + QM_PEH_VENDOR_ID);
5007         ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
5008                                          (val == ACC_VENDOR_ID_VALUE),
5009                                          POLL_PERIOD, POLL_TIMEOUT);
5010         if (ret) {
5011                 dev_err(&pdev->dev, "Fails to read QM reg!\n");
5012                 return ret;
5013         }
5014
5015         writel(PCI_VENDOR_ID_HUAWEI, qm->io_base + QM_PEH_VENDOR_ID);
5016         ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
5017                                          (val == PCI_VENDOR_ID_HUAWEI),
5018                                          POLL_PERIOD, POLL_TIMEOUT);
5019         if (ret)
5020                 dev_err(&pdev->dev, "Fails to read QM reg in the second time!\n");
5021
5022         return ret;
5023 }
5024
5025 static int qm_set_pf_mse(struct hisi_qm *qm, bool set)
5026 {
5027         struct pci_dev *pdev = qm->pdev;
5028         u16 cmd;
5029         int i;
5030
5031         pci_read_config_word(pdev, PCI_COMMAND, &cmd);
5032         if (set)
5033                 cmd |= PCI_COMMAND_MEMORY;
5034         else
5035                 cmd &= ~PCI_COMMAND_MEMORY;
5036
5037         pci_write_config_word(pdev, PCI_COMMAND, cmd);
5038         for (i = 0; i < MAX_WAIT_COUNTS; i++) {
5039                 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
5040                 if (set == ((cmd & PCI_COMMAND_MEMORY) >> 1))
5041                         return 0;
5042
5043                 udelay(1);
5044         }
5045
5046         return -ETIMEDOUT;
5047 }
5048
5049 static int qm_set_vf_mse(struct hisi_qm *qm, bool set)
5050 {
5051         struct pci_dev *pdev = qm->pdev;
5052         u16 sriov_ctrl;
5053         int pos;
5054         int i;
5055
5056         pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
5057         pci_read_config_word(pdev, pos + PCI_SRIOV_CTRL, &sriov_ctrl);
5058         if (set)
5059                 sriov_ctrl |= PCI_SRIOV_CTRL_MSE;
5060         else
5061                 sriov_ctrl &= ~PCI_SRIOV_CTRL_MSE;
5062         pci_write_config_word(pdev, pos + PCI_SRIOV_CTRL, sriov_ctrl);
5063
5064         for (i = 0; i < MAX_WAIT_COUNTS; i++) {
5065                 pci_read_config_word(pdev, pos + PCI_SRIOV_CTRL, &sriov_ctrl);
5066                 if (set == (sriov_ctrl & PCI_SRIOV_CTRL_MSE) >>
5067                     ACC_PEH_SRIOV_CTRL_VF_MSE_SHIFT)
5068                         return 0;
5069
5070                 udelay(1);
5071         }
5072
5073         return -ETIMEDOUT;
5074 }
5075
5076 static int qm_vf_reset_prepare(struct hisi_qm *qm,
5077                                enum qm_stop_reason stop_reason)
5078 {
5079         struct hisi_qm_list *qm_list = qm->qm_list;
5080         struct pci_dev *pdev = qm->pdev;
5081         struct pci_dev *virtfn;
5082         struct hisi_qm *vf_qm;
5083         int ret = 0;
5084
5085         mutex_lock(&qm_list->lock);
5086         list_for_each_entry(vf_qm, &qm_list->list, list) {
5087                 virtfn = vf_qm->pdev;
5088                 if (virtfn == pdev)
5089                         continue;
5090
5091                 if (pci_physfn(virtfn) == pdev) {
5092                         /* save VFs PCIE BAR configuration */
5093                         pci_save_state(virtfn);
5094
5095                         ret = hisi_qm_stop(vf_qm, stop_reason);
5096                         if (ret)
5097                                 goto stop_fail;
5098                 }
5099         }
5100
5101 stop_fail:
5102         mutex_unlock(&qm_list->lock);
5103         return ret;
5104 }
5105
5106 static int qm_try_stop_vfs(struct hisi_qm *qm, u64 cmd,
5107                            enum qm_stop_reason stop_reason)
5108 {
5109         struct pci_dev *pdev = qm->pdev;
5110         int ret;
5111
5112         if (!qm->vfs_num)
5113                 return 0;
5114
5115         /* Kunpeng930 supports to notify VFs to stop before PF reset */
5116         if (test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps)) {
5117                 ret = qm_ping_all_vfs(qm, cmd);
5118                 if (ret)
5119                         pci_err(pdev, "failed to send cmd to all VFs before PF reset!\n");
5120         } else {
5121                 ret = qm_vf_reset_prepare(qm, stop_reason);
5122                 if (ret)
5123                         pci_err(pdev, "failed to prepare reset, ret = %d.\n", ret);
5124         }
5125
5126         return ret;
5127 }
5128
5129 static int qm_controller_reset_prepare(struct hisi_qm *qm)
5130 {
5131         struct pci_dev *pdev = qm->pdev;
5132         int ret;
5133
5134         ret = qm_reset_prepare_ready(qm);
5135         if (ret) {
5136                 pci_err(pdev, "Controller reset not ready!\n");
5137                 return ret;
5138         }
5139
5140         /* PF obtains the information of VF by querying the register. */
5141         qm_cmd_uninit(qm);
5142
5143         /* Whether VFs stop successfully, soft reset will continue. */
5144         ret = qm_try_stop_vfs(qm, QM_PF_SRST_PREPARE, QM_SOFT_RESET);
5145         if (ret)
5146                 pci_err(pdev, "failed to stop vfs by pf in soft reset.\n");
5147
5148         ret = hisi_qm_stop(qm, QM_SOFT_RESET);
5149         if (ret) {
5150                 pci_err(pdev, "Fails to stop QM!\n");
5151                 qm_reset_bit_clear(qm);
5152                 return ret;
5153         }
5154
5155         ret = qm_wait_vf_prepare_finish(qm);
5156         if (ret)
5157                 pci_err(pdev, "failed to stop by vfs in soft reset!\n");
5158
5159         clear_bit(QM_RST_SCHED, &qm->misc_ctl);
5160
5161         return 0;
5162 }
5163
5164 static void qm_dev_ecc_mbit_handle(struct hisi_qm *qm)
5165 {
5166         u32 nfe_enb = 0;
5167
5168         /* Kunpeng930 hardware automatically close master ooo when NFE occurs */
5169         if (qm->ver >= QM_HW_V3)
5170                 return;
5171
5172         if (!qm->err_status.is_dev_ecc_mbit &&
5173             qm->err_status.is_qm_ecc_mbit &&
5174             qm->err_ini->close_axi_master_ooo) {
5175
5176                 qm->err_ini->close_axi_master_ooo(qm);
5177
5178         } else if (qm->err_status.is_dev_ecc_mbit &&
5179                    !qm->err_status.is_qm_ecc_mbit &&
5180                    !qm->err_ini->close_axi_master_ooo) {
5181
5182                 nfe_enb = readl(qm->io_base + QM_RAS_NFE_ENABLE);
5183                 writel(nfe_enb & QM_RAS_NFE_MBIT_DISABLE,
5184                        qm->io_base + QM_RAS_NFE_ENABLE);
5185                 writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SET);
5186         }
5187 }
5188
5189 static int qm_soft_reset(struct hisi_qm *qm)
5190 {
5191         struct pci_dev *pdev = qm->pdev;
5192         int ret;
5193         u32 val;
5194
5195         /* Ensure all doorbells and mailboxes received by QM */
5196         ret = qm_check_req_recv(qm);
5197         if (ret)
5198                 return ret;
5199
5200         if (qm->vfs_num) {
5201                 ret = qm_set_vf_mse(qm, false);
5202                 if (ret) {
5203                         pci_err(pdev, "Fails to disable vf MSE bit.\n");
5204                         return ret;
5205                 }
5206         }
5207
5208         ret = qm->ops->set_msi(qm, false);
5209         if (ret) {
5210                 pci_err(pdev, "Fails to disable PEH MSI bit.\n");
5211                 return ret;
5212         }
5213
5214         qm_dev_ecc_mbit_handle(qm);
5215
5216         /* OOO register set and check */
5217         writel(ACC_MASTER_GLOBAL_CTRL_SHUTDOWN,
5218                qm->io_base + ACC_MASTER_GLOBAL_CTRL);
5219
5220         /* If bus lock, reset chip */
5221         ret = readl_relaxed_poll_timeout(qm->io_base + ACC_MASTER_TRANS_RETURN,
5222                                          val,
5223                                          (val == ACC_MASTER_TRANS_RETURN_RW),
5224                                          POLL_PERIOD, POLL_TIMEOUT);
5225         if (ret) {
5226                 pci_emerg(pdev, "Bus lock! Please reset system.\n");
5227                 return ret;
5228         }
5229
5230         if (qm->err_ini->close_sva_prefetch)
5231                 qm->err_ini->close_sva_prefetch(qm);
5232
5233         ret = qm_set_pf_mse(qm, false);
5234         if (ret) {
5235                 pci_err(pdev, "Fails to disable pf MSE bit.\n");
5236                 return ret;
5237         }
5238
5239         /* The reset related sub-control registers are not in PCI BAR */
5240         if (ACPI_HANDLE(&pdev->dev)) {
5241                 unsigned long long value = 0;
5242                 acpi_status s;
5243
5244                 s = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
5245                                           qm->err_info.acpi_rst,
5246                                           NULL, &value);
5247                 if (ACPI_FAILURE(s)) {
5248                         pci_err(pdev, "NO controller reset method!\n");
5249                         return -EIO;
5250                 }
5251
5252                 if (value) {
5253                         pci_err(pdev, "Reset step %llu failed!\n", value);
5254                         return -EIO;
5255                 }
5256         } else {
5257                 pci_err(pdev, "No reset method!\n");
5258                 return -EINVAL;
5259         }
5260
5261         return 0;
5262 }
5263
5264 static int qm_vf_reset_done(struct hisi_qm *qm)
5265 {
5266         struct hisi_qm_list *qm_list = qm->qm_list;
5267         struct pci_dev *pdev = qm->pdev;
5268         struct pci_dev *virtfn;
5269         struct hisi_qm *vf_qm;
5270         int ret = 0;
5271
5272         mutex_lock(&qm_list->lock);
5273         list_for_each_entry(vf_qm, &qm_list->list, list) {
5274                 virtfn = vf_qm->pdev;
5275                 if (virtfn == pdev)
5276                         continue;
5277
5278                 if (pci_physfn(virtfn) == pdev) {
5279                         /* enable VFs PCIE BAR configuration */
5280                         pci_restore_state(virtfn);
5281
5282                         ret = qm_restart(vf_qm);
5283                         if (ret)
5284                                 goto restart_fail;
5285                 }
5286         }
5287
5288 restart_fail:
5289         mutex_unlock(&qm_list->lock);
5290         return ret;
5291 }
5292
5293 static int qm_try_start_vfs(struct hisi_qm *qm, enum qm_mb_cmd cmd)
5294 {
5295         struct pci_dev *pdev = qm->pdev;
5296         int ret;
5297
5298         if (!qm->vfs_num)
5299                 return 0;
5300
5301         ret = qm_vf_q_assign(qm, qm->vfs_num);
5302         if (ret) {
5303                 pci_err(pdev, "failed to assign VFs, ret = %d.\n", ret);
5304                 return ret;
5305         }
5306
5307         /* Kunpeng930 supports to notify VFs to start after PF reset. */
5308         if (test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps)) {
5309                 ret = qm_ping_all_vfs(qm, cmd);
5310                 if (ret)
5311                         pci_warn(pdev, "failed to send cmd to all VFs after PF reset!\n");
5312         } else {
5313                 ret = qm_vf_reset_done(qm);
5314                 if (ret)
5315                         pci_warn(pdev, "failed to start vfs, ret = %d.\n", ret);
5316         }
5317
5318         return ret;
5319 }
5320
5321 static int qm_dev_hw_init(struct hisi_qm *qm)
5322 {
5323         return qm->err_ini->hw_init(qm);
5324 }
5325
5326 static void qm_restart_prepare(struct hisi_qm *qm)
5327 {
5328         u32 value;
5329
5330         if (qm->err_ini->open_sva_prefetch)
5331                 qm->err_ini->open_sva_prefetch(qm);
5332
5333         if (qm->ver >= QM_HW_V3)
5334                 return;
5335
5336         if (!qm->err_status.is_qm_ecc_mbit &&
5337             !qm->err_status.is_dev_ecc_mbit)
5338                 return;
5339
5340         /* temporarily close the OOO port used for PEH to write out MSI */
5341         value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
5342         writel(value & ~qm->err_info.msi_wr_port,
5343                qm->io_base + ACC_AM_CFG_PORT_WR_EN);
5344
5345         /* clear dev ecc 2bit error source if having */
5346         value = qm_get_dev_err_status(qm) & qm->err_info.ecc_2bits_mask;
5347         if (value && qm->err_ini->clear_dev_hw_err_status)
5348                 qm->err_ini->clear_dev_hw_err_status(qm, value);
5349
5350         /* clear QM ecc mbit error source */
5351         writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SOURCE);
5352
5353         /* clear AM Reorder Buffer ecc mbit source */
5354         writel(ACC_ROB_ECC_ERR_MULTPL, qm->io_base + ACC_AM_ROB_ECC_INT_STS);
5355 }
5356
5357 static void qm_restart_done(struct hisi_qm *qm)
5358 {
5359         u32 value;
5360
5361         if (qm->ver >= QM_HW_V3)
5362                 goto clear_flags;
5363
5364         if (!qm->err_status.is_qm_ecc_mbit &&
5365             !qm->err_status.is_dev_ecc_mbit)
5366                 return;
5367
5368         /* open the OOO port for PEH to write out MSI */
5369         value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
5370         value |= qm->err_info.msi_wr_port;
5371         writel(value, qm->io_base + ACC_AM_CFG_PORT_WR_EN);
5372
5373 clear_flags:
5374         qm->err_status.is_qm_ecc_mbit = false;
5375         qm->err_status.is_dev_ecc_mbit = false;
5376 }
5377
5378 static int qm_controller_reset_done(struct hisi_qm *qm)
5379 {
5380         struct pci_dev *pdev = qm->pdev;
5381         int ret;
5382
5383         ret = qm->ops->set_msi(qm, true);
5384         if (ret) {
5385                 pci_err(pdev, "Fails to enable PEH MSI bit!\n");
5386                 return ret;
5387         }
5388
5389         ret = qm_set_pf_mse(qm, true);
5390         if (ret) {
5391                 pci_err(pdev, "Fails to enable pf MSE bit!\n");
5392                 return ret;
5393         }
5394
5395         if (qm->vfs_num) {
5396                 ret = qm_set_vf_mse(qm, true);
5397                 if (ret) {
5398                         pci_err(pdev, "Fails to enable vf MSE bit!\n");
5399                         return ret;
5400                 }
5401         }
5402
5403         ret = qm_dev_hw_init(qm);
5404         if (ret) {
5405                 pci_err(pdev, "Failed to init device\n");
5406                 return ret;
5407         }
5408
5409         qm_restart_prepare(qm);
5410         hisi_qm_dev_err_init(qm);
5411         if (qm->err_ini->open_axi_master_ooo)
5412                 qm->err_ini->open_axi_master_ooo(qm);
5413
5414         ret = qm_dev_mem_reset(qm);
5415         if (ret) {
5416                 pci_err(pdev, "failed to reset device memory\n");
5417                 return ret;
5418         }
5419
5420         ret = qm_restart(qm);
5421         if (ret) {
5422                 pci_err(pdev, "Failed to start QM!\n");
5423                 return ret;
5424         }
5425
5426         ret = qm_try_start_vfs(qm, QM_PF_RESET_DONE);
5427         if (ret)
5428                 pci_err(pdev, "failed to start vfs by pf in soft reset.\n");
5429
5430         ret = qm_wait_vf_prepare_finish(qm);
5431         if (ret)
5432                 pci_err(pdev, "failed to start by vfs in soft reset!\n");
5433
5434         qm_cmd_init(qm);
5435         qm_restart_done(qm);
5436
5437         qm_reset_bit_clear(qm);
5438
5439         return 0;
5440 }
5441
5442 static void qm_show_last_dfx_regs(struct hisi_qm *qm)
5443 {
5444         struct qm_debug *debug = &qm->debug;
5445         struct pci_dev *pdev = qm->pdev;
5446         u32 val;
5447         int i;
5448
5449         if (qm->fun_type == QM_HW_VF || !debug->qm_last_words)
5450                 return;
5451
5452         for (i = 0; i < ARRAY_SIZE(qm_dfx_regs); i++) {
5453                 val = readl_relaxed(qm->io_base + qm_dfx_regs[i].offset);
5454                 if (debug->qm_last_words[i] != val)
5455                         pci_info(pdev, "%s \t= 0x%08x => 0x%08x\n",
5456                         qm_dfx_regs[i].name, debug->qm_last_words[i], val);
5457         }
5458 }
5459
5460 static int qm_controller_reset(struct hisi_qm *qm)
5461 {
5462         struct pci_dev *pdev = qm->pdev;
5463         int ret;
5464
5465         pci_info(pdev, "Controller resetting...\n");
5466
5467         ret = qm_controller_reset_prepare(qm);
5468         if (ret) {
5469                 hisi_qm_set_hw_reset(qm, QM_RESET_STOP_TX_OFFSET);
5470                 hisi_qm_set_hw_reset(qm, QM_RESET_STOP_RX_OFFSET);
5471                 clear_bit(QM_RST_SCHED, &qm->misc_ctl);
5472                 return ret;
5473         }
5474
5475         qm_show_last_dfx_regs(qm);
5476         if (qm->err_ini->show_last_dfx_regs)
5477                 qm->err_ini->show_last_dfx_regs(qm);
5478
5479         ret = qm_soft_reset(qm);
5480         if (ret) {
5481                 pci_err(pdev, "Controller reset failed (%d)\n", ret);
5482                 qm_reset_bit_clear(qm);
5483                 return ret;
5484         }
5485
5486         ret = qm_controller_reset_done(qm);
5487         if (ret) {
5488                 qm_reset_bit_clear(qm);
5489                 return ret;
5490         }
5491
5492         pci_info(pdev, "Controller reset complete\n");
5493
5494         return 0;
5495 }
5496
5497 /**
5498  * hisi_qm_dev_slot_reset() - slot reset
5499  * @pdev: the PCIe device
5500  *
5501  * This function offers QM relate PCIe device reset interface. Drivers which
5502  * use QM can use this function as slot_reset in its struct pci_error_handlers.
5503  */
5504 pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev)
5505 {
5506         struct hisi_qm *qm = pci_get_drvdata(pdev);
5507         int ret;
5508
5509         if (pdev->is_virtfn)
5510                 return PCI_ERS_RESULT_RECOVERED;
5511
5512         /* reset pcie device controller */
5513         ret = qm_controller_reset(qm);
5514         if (ret) {
5515                 pci_err(pdev, "Controller reset failed (%d)\n", ret);
5516                 return PCI_ERS_RESULT_DISCONNECT;
5517         }
5518
5519         return PCI_ERS_RESULT_RECOVERED;
5520 }
5521 EXPORT_SYMBOL_GPL(hisi_qm_dev_slot_reset);
5522
5523 void hisi_qm_reset_prepare(struct pci_dev *pdev)
5524 {
5525         struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(pdev));
5526         struct hisi_qm *qm = pci_get_drvdata(pdev);
5527         u32 delay = 0;
5528         int ret;
5529
5530         hisi_qm_dev_err_uninit(pf_qm);
5531
5532         /*
5533          * Check whether there is an ECC mbit error, If it occurs, need to
5534          * wait for soft reset to fix it.
5535          */
5536         while (qm_check_dev_error(pf_qm)) {
5537                 msleep(++delay);
5538                 if (delay > QM_RESET_WAIT_TIMEOUT)
5539                         return;
5540         }
5541
5542         ret = qm_reset_prepare_ready(qm);
5543         if (ret) {
5544                 pci_err(pdev, "FLR not ready!\n");
5545                 return;
5546         }
5547
5548         /* PF obtains the information of VF by querying the register. */
5549         if (qm->fun_type == QM_HW_PF)
5550                 qm_cmd_uninit(qm);
5551
5552         ret = qm_try_stop_vfs(qm, QM_PF_FLR_PREPARE, QM_FLR);
5553         if (ret)
5554                 pci_err(pdev, "failed to stop vfs by pf in FLR.\n");
5555
5556         ret = hisi_qm_stop(qm, QM_FLR);
5557         if (ret) {
5558                 pci_err(pdev, "Failed to stop QM, ret = %d.\n", ret);
5559                 hisi_qm_set_hw_reset(qm, QM_RESET_STOP_TX_OFFSET);
5560                 hisi_qm_set_hw_reset(qm, QM_RESET_STOP_RX_OFFSET);
5561                 return;
5562         }
5563
5564         ret = qm_wait_vf_prepare_finish(qm);
5565         if (ret)
5566                 pci_err(pdev, "failed to stop by vfs in FLR!\n");
5567
5568         pci_info(pdev, "FLR resetting...\n");
5569 }
5570 EXPORT_SYMBOL_GPL(hisi_qm_reset_prepare);
5571
5572 static bool qm_flr_reset_complete(struct pci_dev *pdev)
5573 {
5574         struct pci_dev *pf_pdev = pci_physfn(pdev);
5575         struct hisi_qm *qm = pci_get_drvdata(pf_pdev);
5576         u32 id;
5577
5578         pci_read_config_dword(qm->pdev, PCI_COMMAND, &id);
5579         if (id == QM_PCI_COMMAND_INVALID) {
5580                 pci_err(pdev, "Device can not be used!\n");
5581                 return false;
5582         }
5583
5584         return true;
5585 }
5586
5587 void hisi_qm_reset_done(struct pci_dev *pdev)
5588 {
5589         struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(pdev));
5590         struct hisi_qm *qm = pci_get_drvdata(pdev);
5591         int ret;
5592
5593         if (qm->fun_type == QM_HW_PF) {
5594                 ret = qm_dev_hw_init(qm);
5595                 if (ret) {
5596                         pci_err(pdev, "Failed to init PF, ret = %d.\n", ret);
5597                         goto flr_done;
5598                 }
5599         }
5600
5601         hisi_qm_dev_err_init(pf_qm);
5602
5603         ret = qm_restart(qm);
5604         if (ret) {
5605                 pci_err(pdev, "Failed to start QM, ret = %d.\n", ret);
5606                 goto flr_done;
5607         }
5608
5609         ret = qm_try_start_vfs(qm, QM_PF_RESET_DONE);
5610         if (ret)
5611                 pci_err(pdev, "failed to start vfs by pf in FLR.\n");
5612
5613         ret = qm_wait_vf_prepare_finish(qm);
5614         if (ret)
5615                 pci_err(pdev, "failed to start by vfs in FLR!\n");
5616
5617 flr_done:
5618         if (qm->fun_type == QM_HW_PF)
5619                 qm_cmd_init(qm);
5620
5621         if (qm_flr_reset_complete(pdev))
5622                 pci_info(pdev, "FLR reset complete\n");
5623
5624         qm_reset_bit_clear(qm);
5625 }
5626 EXPORT_SYMBOL_GPL(hisi_qm_reset_done);
5627
5628 static irqreturn_t qm_abnormal_irq(int irq, void *data)
5629 {
5630         struct hisi_qm *qm = data;
5631         enum acc_err_result ret;
5632
5633         atomic64_inc(&qm->debug.dfx.abnormal_irq_cnt);
5634         ret = qm_process_dev_error(qm);
5635         if (ret == ACC_ERR_NEED_RESET &&
5636             !test_bit(QM_DRIVER_REMOVING, &qm->misc_ctl) &&
5637             !test_and_set_bit(QM_RST_SCHED, &qm->misc_ctl))
5638                 schedule_work(&qm->rst_work);
5639
5640         return IRQ_HANDLED;
5641 }
5642
5643
5644 /**
5645  * hisi_qm_dev_shutdown() - Shutdown device.
5646  * @pdev: The device will be shutdown.
5647  *
5648  * This function will stop qm when OS shutdown or rebooting.
5649  */
5650 void hisi_qm_dev_shutdown(struct pci_dev *pdev)
5651 {
5652         struct hisi_qm *qm = pci_get_drvdata(pdev);
5653         int ret;
5654
5655         ret = hisi_qm_stop(qm, QM_NORMAL);
5656         if (ret)
5657                 dev_err(&pdev->dev, "Fail to stop qm in shutdown!\n");
5658 }
5659 EXPORT_SYMBOL_GPL(hisi_qm_dev_shutdown);
5660
5661 static void hisi_qm_controller_reset(struct work_struct *rst_work)
5662 {
5663         struct hisi_qm *qm = container_of(rst_work, struct hisi_qm, rst_work);
5664         int ret;
5665
5666         ret = qm_pm_get_sync(qm);
5667         if (ret) {
5668                 clear_bit(QM_RST_SCHED, &qm->misc_ctl);
5669                 return;
5670         }
5671
5672         /* reset pcie device controller */
5673         ret = qm_controller_reset(qm);
5674         if (ret)
5675                 dev_err(&qm->pdev->dev, "controller reset failed (%d)\n", ret);
5676
5677         qm_pm_put_sync(qm);
5678 }
5679
5680 static void qm_pf_reset_vf_prepare(struct hisi_qm *qm,
5681                                    enum qm_stop_reason stop_reason)
5682 {
5683         enum qm_mb_cmd cmd = QM_VF_PREPARE_DONE;
5684         struct pci_dev *pdev = qm->pdev;
5685         int ret;
5686
5687         ret = qm_reset_prepare_ready(qm);
5688         if (ret) {
5689                 dev_err(&pdev->dev, "reset prepare not ready!\n");
5690                 atomic_set(&qm->status.flags, QM_STOP);
5691                 cmd = QM_VF_PREPARE_FAIL;
5692                 goto err_prepare;
5693         }
5694
5695         ret = hisi_qm_stop(qm, stop_reason);
5696         if (ret) {
5697                 dev_err(&pdev->dev, "failed to stop QM, ret = %d.\n", ret);
5698                 atomic_set(&qm->status.flags, QM_STOP);
5699                 cmd = QM_VF_PREPARE_FAIL;
5700                 goto err_prepare;
5701         } else {
5702                 goto out;
5703         }
5704
5705 err_prepare:
5706         hisi_qm_set_hw_reset(qm, QM_RESET_STOP_TX_OFFSET);
5707         hisi_qm_set_hw_reset(qm, QM_RESET_STOP_RX_OFFSET);
5708 out:
5709         pci_save_state(pdev);
5710         ret = qm_ping_pf(qm, cmd);
5711         if (ret)
5712                 dev_warn(&pdev->dev, "PF responds timeout in reset prepare!\n");
5713 }
5714
5715 static void qm_pf_reset_vf_done(struct hisi_qm *qm)
5716 {
5717         enum qm_mb_cmd cmd = QM_VF_START_DONE;
5718         struct pci_dev *pdev = qm->pdev;
5719         int ret;
5720
5721         pci_restore_state(pdev);
5722         ret = hisi_qm_start(qm);
5723         if (ret) {
5724                 dev_err(&pdev->dev, "failed to start QM, ret = %d.\n", ret);
5725                 cmd = QM_VF_START_FAIL;
5726         }
5727
5728         ret = qm_ping_pf(qm, cmd);
5729         if (ret)
5730                 dev_warn(&pdev->dev, "PF responds timeout in reset done!\n");
5731
5732         qm_reset_bit_clear(qm);
5733 }
5734
5735 static int qm_wait_pf_reset_finish(struct hisi_qm *qm)
5736 {
5737         struct device *dev = &qm->pdev->dev;
5738         u32 val, cmd;
5739         u64 msg;
5740         int ret;
5741
5742         /* Wait for reset to finish */
5743         ret = readl_relaxed_poll_timeout(qm->io_base + QM_IFC_INT_SOURCE_V, val,
5744                                          val == BIT(0), QM_VF_RESET_WAIT_US,
5745                                          QM_VF_RESET_WAIT_TIMEOUT_US);
5746         /* hardware completion status should be available by this time */
5747         if (ret) {
5748                 dev_err(dev, "couldn't get reset done status from PF, timeout!\n");
5749                 return -ETIMEDOUT;
5750         }
5751
5752         /*
5753          * Whether message is got successfully,
5754          * VF needs to ack PF by clearing the interrupt.
5755          */
5756         ret = qm_get_mb_cmd(qm, &msg, 0);
5757         qm_clear_cmd_interrupt(qm, 0);
5758         if (ret) {
5759                 dev_err(dev, "failed to get msg from PF in reset done!\n");
5760                 return ret;
5761         }
5762
5763         cmd = msg & QM_MB_CMD_DATA_MASK;
5764         if (cmd != QM_PF_RESET_DONE) {
5765                 dev_err(dev, "the cmd(%u) is not reset done!\n", cmd);
5766                 ret = -EINVAL;
5767         }
5768
5769         return ret;
5770 }
5771
5772 static void qm_pf_reset_vf_process(struct hisi_qm *qm,
5773                                    enum qm_stop_reason stop_reason)
5774 {
5775         struct device *dev = &qm->pdev->dev;
5776         int ret;
5777
5778         dev_info(dev, "device reset start...\n");
5779
5780         /* The message is obtained by querying the register during resetting */
5781         qm_cmd_uninit(qm);
5782         qm_pf_reset_vf_prepare(qm, stop_reason);
5783
5784         ret = qm_wait_pf_reset_finish(qm);
5785         if (ret)
5786                 goto err_get_status;
5787
5788         qm_pf_reset_vf_done(qm);
5789         qm_cmd_init(qm);
5790
5791         dev_info(dev, "device reset done.\n");
5792
5793         return;
5794
5795 err_get_status:
5796         qm_cmd_init(qm);
5797         qm_reset_bit_clear(qm);
5798 }
5799
5800 static void qm_handle_cmd_msg(struct hisi_qm *qm, u32 fun_num)
5801 {
5802         struct device *dev = &qm->pdev->dev;
5803         u64 msg;
5804         u32 cmd;
5805         int ret;
5806
5807         /*
5808          * Get the msg from source by sending mailbox. Whether message is got
5809          * successfully, destination needs to ack source by clearing the interrupt.
5810          */
5811         ret = qm_get_mb_cmd(qm, &msg, fun_num);
5812         qm_clear_cmd_interrupt(qm, BIT(fun_num));
5813         if (ret) {
5814                 dev_err(dev, "failed to get msg from source!\n");
5815                 return;
5816         }
5817
5818         cmd = msg & QM_MB_CMD_DATA_MASK;
5819         switch (cmd) {
5820         case QM_PF_FLR_PREPARE:
5821                 qm_pf_reset_vf_process(qm, QM_FLR);
5822                 break;
5823         case QM_PF_SRST_PREPARE:
5824                 qm_pf_reset_vf_process(qm, QM_SOFT_RESET);
5825                 break;
5826         case QM_VF_GET_QOS:
5827                 qm_vf_get_qos(qm, fun_num);
5828                 break;
5829         case QM_PF_SET_QOS:
5830                 qm->mb_qos = msg >> QM_MB_CMD_DATA_SHIFT;
5831                 break;
5832         default:
5833                 dev_err(dev, "unsupported cmd %u sent by function(%u)!\n", cmd, fun_num);
5834                 break;
5835         }
5836 }
5837
5838 static void qm_cmd_process(struct work_struct *cmd_process)
5839 {
5840         struct hisi_qm *qm = container_of(cmd_process,
5841                                         struct hisi_qm, cmd_process);
5842         u32 vfs_num = qm->vfs_num;
5843         u64 val;
5844         u32 i;
5845
5846         if (qm->fun_type == QM_HW_PF) {
5847                 val = readq(qm->io_base + QM_IFC_INT_SOURCE_P);
5848                 if (!val)
5849                         return;
5850
5851                 for (i = 1; i <= vfs_num; i++) {
5852                         if (val & BIT(i))
5853                                 qm_handle_cmd_msg(qm, i);
5854                 }
5855
5856                 return;
5857         }
5858
5859         qm_handle_cmd_msg(qm, 0);
5860 }
5861
5862 /**
5863  * hisi_qm_alg_register() - Register alg to crypto and add qm to qm_list.
5864  * @qm: The qm needs add.
5865  * @qm_list: The qm list.
5866  *
5867  * This function adds qm to qm list, and will register algorithm to
5868  * crypto when the qm list is empty.
5869  */
5870 int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
5871 {
5872         struct device *dev = &qm->pdev->dev;
5873         int flag = 0;
5874         int ret = 0;
5875
5876         mutex_lock(&qm_list->lock);
5877         if (list_empty(&qm_list->list))
5878                 flag = 1;
5879         list_add_tail(&qm->list, &qm_list->list);
5880         mutex_unlock(&qm_list->lock);
5881
5882         if (qm->ver <= QM_HW_V2 && qm->use_sva) {
5883                 dev_info(dev, "HW V2 not both use uacce sva mode and hardware crypto algs.\n");
5884                 return 0;
5885         }
5886
5887         if (flag) {
5888                 ret = qm_list->register_to_crypto(qm);
5889                 if (ret) {
5890                         mutex_lock(&qm_list->lock);
5891                         list_del(&qm->list);
5892                         mutex_unlock(&qm_list->lock);
5893                 }
5894         }
5895
5896         return ret;
5897 }
5898 EXPORT_SYMBOL_GPL(hisi_qm_alg_register);
5899
5900 /**
5901  * hisi_qm_alg_unregister() - Unregister alg from crypto and delete qm from
5902  * qm list.
5903  * @qm: The qm needs delete.
5904  * @qm_list: The qm list.
5905  *
5906  * This function deletes qm from qm list, and will unregister algorithm
5907  * from crypto when the qm list is empty.
5908  */
5909 void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
5910 {
5911         mutex_lock(&qm_list->lock);
5912         list_del(&qm->list);
5913         mutex_unlock(&qm_list->lock);
5914
5915         if (qm->ver <= QM_HW_V2 && qm->use_sva)
5916                 return;
5917
5918         if (list_empty(&qm_list->list))
5919                 qm_list->unregister_from_crypto(qm);
5920 }
5921 EXPORT_SYMBOL_GPL(hisi_qm_alg_unregister);
5922
5923 static void qm_unregister_abnormal_irq(struct hisi_qm *qm)
5924 {
5925         struct pci_dev *pdev = qm->pdev;
5926         u32 irq_vector, val;
5927
5928         if (qm->fun_type == QM_HW_VF)
5929                 return;
5930
5931         val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_ABN_IRQ_TYPE_CAP, qm->cap_ver);
5932         if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_ABN_IRQ_TYPE_MASK))
5933                 return;
5934
5935         irq_vector = val & QM_IRQ_VECTOR_MASK;
5936         free_irq(pci_irq_vector(pdev, irq_vector), qm);
5937 }
5938
5939 static int qm_register_abnormal_irq(struct hisi_qm *qm)
5940 {
5941         struct pci_dev *pdev = qm->pdev;
5942         u32 irq_vector, val;
5943         int ret;
5944
5945         if (qm->fun_type == QM_HW_VF)
5946                 return 0;
5947
5948         val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_ABN_IRQ_TYPE_CAP, qm->cap_ver);
5949         if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_ABN_IRQ_TYPE_MASK))
5950                 return 0;
5951
5952         irq_vector = val & QM_IRQ_VECTOR_MASK;
5953         ret = request_irq(pci_irq_vector(pdev, irq_vector), qm_abnormal_irq, 0, qm->dev_name, qm);
5954         if (ret)
5955                 dev_err(&qm->pdev->dev, "failed to request abnormal irq, ret = %d", ret);
5956
5957         return ret;
5958 }
5959
5960 static void qm_unregister_mb_cmd_irq(struct hisi_qm *qm)
5961 {
5962         struct pci_dev *pdev = qm->pdev;
5963         u32 irq_vector, val;
5964
5965         val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_PF2VF_IRQ_TYPE_CAP, qm->cap_ver);
5966         if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
5967                 return;
5968
5969         irq_vector = val & QM_IRQ_VECTOR_MASK;
5970         free_irq(pci_irq_vector(pdev, irq_vector), qm);
5971 }
5972
5973 static int qm_register_mb_cmd_irq(struct hisi_qm *qm)
5974 {
5975         struct pci_dev *pdev = qm->pdev;
5976         u32 irq_vector, val;
5977         int ret;
5978
5979         val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_PF2VF_IRQ_TYPE_CAP, qm->cap_ver);
5980         if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
5981                 return 0;
5982
5983         irq_vector = val & QM_IRQ_VECTOR_MASK;
5984         ret = request_irq(pci_irq_vector(pdev, irq_vector), qm_mb_cmd_irq, 0, qm->dev_name, qm);
5985         if (ret)
5986                 dev_err(&pdev->dev, "failed to request function communication irq, ret = %d", ret);
5987
5988         return ret;
5989 }
5990
5991 static void qm_unregister_aeq_irq(struct hisi_qm *qm)
5992 {
5993         struct pci_dev *pdev = qm->pdev;
5994         u32 irq_vector, val;
5995
5996         val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_AEQ_IRQ_TYPE_CAP, qm->cap_ver);
5997         if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
5998                 return;
5999
6000         irq_vector = val & QM_IRQ_VECTOR_MASK;
6001         free_irq(pci_irq_vector(pdev, irq_vector), qm);
6002 }
6003
6004 static int qm_register_aeq_irq(struct hisi_qm *qm)
6005 {
6006         struct pci_dev *pdev = qm->pdev;
6007         u32 irq_vector, val;
6008         int ret;
6009
6010         val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_AEQ_IRQ_TYPE_CAP, qm->cap_ver);
6011         if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
6012                 return 0;
6013
6014         irq_vector = val & QM_IRQ_VECTOR_MASK;
6015         ret = request_threaded_irq(pci_irq_vector(pdev, irq_vector), qm_aeq_irq,
6016                                                    qm_aeq_thread, 0, qm->dev_name, qm);
6017         if (ret)
6018                 dev_err(&pdev->dev, "failed to request eq irq, ret = %d", ret);
6019
6020         return ret;
6021 }
6022
6023 static void qm_unregister_eq_irq(struct hisi_qm *qm)
6024 {
6025         struct pci_dev *pdev = qm->pdev;
6026         u32 irq_vector, val;
6027
6028         val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_EQ_IRQ_TYPE_CAP, qm->cap_ver);
6029         if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
6030                 return;
6031
6032         irq_vector = val & QM_IRQ_VECTOR_MASK;
6033         free_irq(pci_irq_vector(pdev, irq_vector), qm);
6034 }
6035
6036 static int qm_register_eq_irq(struct hisi_qm *qm)
6037 {
6038         struct pci_dev *pdev = qm->pdev;
6039         u32 irq_vector, val;
6040         int ret;
6041
6042         val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_EQ_IRQ_TYPE_CAP, qm->cap_ver);
6043         if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
6044                 return 0;
6045
6046         irq_vector = val & QM_IRQ_VECTOR_MASK;
6047         ret = request_irq(pci_irq_vector(pdev, irq_vector), qm_irq, 0, qm->dev_name, qm);
6048         if (ret)
6049                 dev_err(&pdev->dev, "failed to request eq irq, ret = %d", ret);
6050
6051         return ret;
6052 }
6053
6054 static void qm_irqs_unregister(struct hisi_qm *qm)
6055 {
6056         qm_unregister_mb_cmd_irq(qm);
6057         qm_unregister_abnormal_irq(qm);
6058         qm_unregister_aeq_irq(qm);
6059         qm_unregister_eq_irq(qm);
6060 }
6061
6062 static int qm_irqs_register(struct hisi_qm *qm)
6063 {
6064         int ret;
6065
6066         ret = qm_register_eq_irq(qm);
6067         if (ret)
6068                 return ret;
6069
6070         ret = qm_register_aeq_irq(qm);
6071         if (ret)
6072                 goto free_eq_irq;
6073
6074         ret = qm_register_abnormal_irq(qm);
6075         if (ret)
6076                 goto free_aeq_irq;
6077
6078         ret = qm_register_mb_cmd_irq(qm);
6079         if (ret)
6080                 goto free_abnormal_irq;
6081
6082         return 0;
6083
6084 free_abnormal_irq:
6085         qm_unregister_abnormal_irq(qm);
6086 free_aeq_irq:
6087         qm_unregister_aeq_irq(qm);
6088 free_eq_irq:
6089         qm_unregister_eq_irq(qm);
6090         return ret;
6091 }
6092
6093 static int qm_get_qp_num(struct hisi_qm *qm)
6094 {
6095         bool is_db_isolation;
6096
6097         /* VF's qp_num assigned by PF in v2, and VF can get qp_num by vft. */
6098         if (qm->fun_type == QM_HW_VF) {
6099                 if (qm->ver != QM_HW_V1)
6100                         /* v2 starts to support get vft by mailbox */
6101                         return hisi_qm_get_vft(qm, &qm->qp_base, &qm->qp_num);
6102
6103                 return 0;
6104         }
6105
6106         is_db_isolation = test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps);
6107         qm->ctrl_qp_num = hisi_qm_get_hw_info(qm, qm_basic_info, QM_TOTAL_QP_NUM_CAP, true);
6108         qm->max_qp_num = hisi_qm_get_hw_info(qm, qm_basic_info,
6109                                              QM_FUNC_MAX_QP_CAP, is_db_isolation);
6110
6111         /* check if qp number is valid */
6112         if (qm->qp_num > qm->max_qp_num) {
6113                 dev_err(&qm->pdev->dev, "qp num(%u) is more than max qp num(%u)!\n",
6114                         qm->qp_num, qm->max_qp_num);
6115                 return -EINVAL;
6116         }
6117
6118         return 0;
6119 }
6120
6121 static void qm_get_hw_caps(struct hisi_qm *qm)
6122 {
6123         const struct hisi_qm_cap_info *cap_info = qm->fun_type == QM_HW_PF ?
6124                                                   qm_cap_info_pf : qm_cap_info_vf;
6125         u32 size = qm->fun_type == QM_HW_PF ? ARRAY_SIZE(qm_cap_info_pf) :
6126                                    ARRAY_SIZE(qm_cap_info_vf);
6127         u32 val, i;
6128
6129         /* Doorbell isolate register is a independent register. */
6130         val = hisi_qm_get_hw_info(qm, qm_cap_info_comm, QM_SUPPORT_DB_ISOLATION, true);
6131         if (val)
6132                 set_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps);
6133
6134         if (qm->ver >= QM_HW_V3) {
6135                 val = readl(qm->io_base + QM_FUNC_CAPS_REG);
6136                 qm->cap_ver = val & QM_CAPBILITY_VERSION;
6137         }
6138
6139         /* Get PF/VF common capbility */
6140         for (i = 1; i < ARRAY_SIZE(qm_cap_info_comm); i++) {
6141                 val = hisi_qm_get_hw_info(qm, qm_cap_info_comm, i, qm->cap_ver);
6142                 if (val)
6143                         set_bit(qm_cap_info_comm[i].type, &qm->caps);
6144         }
6145
6146         /* Get PF/VF different capbility */
6147         for (i = 0; i < size; i++) {
6148                 val = hisi_qm_get_hw_info(qm, cap_info, i, qm->cap_ver);
6149                 if (val)
6150                         set_bit(cap_info[i].type, &qm->caps);
6151         }
6152 }
6153
6154 static int qm_get_pci_res(struct hisi_qm *qm)
6155 {
6156         struct pci_dev *pdev = qm->pdev;
6157         struct device *dev = &pdev->dev;
6158         int ret;
6159
6160         ret = pci_request_mem_regions(pdev, qm->dev_name);
6161         if (ret < 0) {
6162                 dev_err(dev, "Failed to request mem regions!\n");
6163                 return ret;
6164         }
6165
6166         qm->phys_base = pci_resource_start(pdev, PCI_BAR_2);
6167         qm->io_base = ioremap(qm->phys_base, pci_resource_len(pdev, PCI_BAR_2));
6168         if (!qm->io_base) {
6169                 ret = -EIO;
6170                 goto err_request_mem_regions;
6171         }
6172
6173         qm_get_hw_caps(qm);
6174         if (test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps)) {
6175                 qm->db_interval = QM_QP_DB_INTERVAL;
6176                 qm->db_phys_base = pci_resource_start(pdev, PCI_BAR_4);
6177                 qm->db_io_base = ioremap(qm->db_phys_base,
6178                                          pci_resource_len(pdev, PCI_BAR_4));
6179                 if (!qm->db_io_base) {
6180                         ret = -EIO;
6181                         goto err_ioremap;
6182                 }
6183         } else {
6184                 qm->db_phys_base = qm->phys_base;
6185                 qm->db_io_base = qm->io_base;
6186                 qm->db_interval = 0;
6187         }
6188
6189         ret = qm_get_qp_num(qm);
6190         if (ret)
6191                 goto err_db_ioremap;
6192
6193         return 0;
6194
6195 err_db_ioremap:
6196         if (test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps))
6197                 iounmap(qm->db_io_base);
6198 err_ioremap:
6199         iounmap(qm->io_base);
6200 err_request_mem_regions:
6201         pci_release_mem_regions(pdev);
6202         return ret;
6203 }
6204
6205 static int hisi_qm_pci_init(struct hisi_qm *qm)
6206 {
6207         struct pci_dev *pdev = qm->pdev;
6208         struct device *dev = &pdev->dev;
6209         unsigned int num_vec;
6210         int ret;
6211
6212         ret = pci_enable_device_mem(pdev);
6213         if (ret < 0) {
6214                 dev_err(dev, "Failed to enable device mem!\n");
6215                 return ret;
6216         }
6217
6218         ret = qm_get_pci_res(qm);
6219         if (ret)
6220                 goto err_disable_pcidev;
6221
6222         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
6223         if (ret < 0)
6224                 goto err_get_pci_res;
6225         pci_set_master(pdev);
6226
6227         num_vec = qm_get_irq_num(qm);
6228         ret = pci_alloc_irq_vectors(pdev, num_vec, num_vec, PCI_IRQ_MSI);
6229         if (ret < 0) {
6230                 dev_err(dev, "Failed to enable MSI vectors!\n");
6231                 goto err_get_pci_res;
6232         }
6233
6234         return 0;
6235
6236 err_get_pci_res:
6237         qm_put_pci_res(qm);
6238 err_disable_pcidev:
6239         pci_disable_device(pdev);
6240         return ret;
6241 }
6242
6243 static int hisi_qm_init_work(struct hisi_qm *qm)
6244 {
6245         int i;
6246
6247         for (i = 0; i < qm->qp_num; i++)
6248                 INIT_WORK(&qm->poll_data[i].work, qm_work_process);
6249
6250         if (qm->fun_type == QM_HW_PF)
6251                 INIT_WORK(&qm->rst_work, hisi_qm_controller_reset);
6252
6253         if (qm->ver > QM_HW_V2)
6254                 INIT_WORK(&qm->cmd_process, qm_cmd_process);
6255
6256         qm->wq = alloc_workqueue("%s", WQ_HIGHPRI | WQ_MEM_RECLAIM |
6257                                  WQ_UNBOUND, num_online_cpus(),
6258                                  pci_name(qm->pdev));
6259         if (!qm->wq) {
6260                 pci_err(qm->pdev, "failed to alloc workqueue!\n");
6261                 return -ENOMEM;
6262         }
6263
6264         return 0;
6265 }
6266
6267 static int hisi_qp_alloc_memory(struct hisi_qm *qm)
6268 {
6269         struct device *dev = &qm->pdev->dev;
6270         u16 sq_depth, cq_depth;
6271         size_t qp_dma_size;
6272         int i, ret;
6273
6274         qm->qp_array = kcalloc(qm->qp_num, sizeof(struct hisi_qp), GFP_KERNEL);
6275         if (!qm->qp_array)
6276                 return -ENOMEM;
6277
6278         qm->poll_data = kcalloc(qm->qp_num, sizeof(struct hisi_qm_poll_data), GFP_KERNEL);
6279         if (!qm->poll_data) {
6280                 kfree(qm->qp_array);
6281                 return -ENOMEM;
6282         }
6283
6284         qm_get_xqc_depth(qm, &sq_depth, &cq_depth, QM_QP_DEPTH_CAP);
6285
6286         /* one more page for device or qp statuses */
6287         qp_dma_size = qm->sqe_size * sq_depth + sizeof(struct qm_cqe) * cq_depth;
6288         qp_dma_size = PAGE_ALIGN(qp_dma_size) + PAGE_SIZE;
6289         for (i = 0; i < qm->qp_num; i++) {
6290                 qm->poll_data[i].qm = qm;
6291                 ret = hisi_qp_memory_init(qm, qp_dma_size, i, sq_depth, cq_depth);
6292                 if (ret)
6293                         goto err_init_qp_mem;
6294
6295                 dev_dbg(dev, "allocate qp dma buf size=%zx)\n", qp_dma_size);
6296         }
6297
6298         return 0;
6299 err_init_qp_mem:
6300         hisi_qp_memory_uninit(qm, i);
6301
6302         return ret;
6303 }
6304
6305 static int hisi_qm_memory_init(struct hisi_qm *qm)
6306 {
6307         struct device *dev = &qm->pdev->dev;
6308         int ret, total_func;
6309         size_t off = 0;
6310
6311         if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps)) {
6312                 total_func = pci_sriov_get_totalvfs(qm->pdev) + 1;
6313                 qm->factor = kcalloc(total_func, sizeof(struct qm_shaper_factor), GFP_KERNEL);
6314                 if (!qm->factor)
6315                         return -ENOMEM;
6316
6317                 /* Only the PF value needs to be initialized */
6318                 qm->factor[0].func_qos = QM_QOS_MAX_VAL;
6319         }
6320
6321 #define QM_INIT_BUF(qm, type, num) do { \
6322         (qm)->type = ((qm)->qdma.va + (off)); \
6323         (qm)->type##_dma = (qm)->qdma.dma + (off); \
6324         off += QMC_ALIGN(sizeof(struct qm_##type) * (num)); \
6325 } while (0)
6326
6327         idr_init(&qm->qp_idr);
6328         qm_get_xqc_depth(qm, &qm->eq_depth, &qm->aeq_depth, QM_XEQ_DEPTH_CAP);
6329         qm->qdma.size = QMC_ALIGN(sizeof(struct qm_eqe) * qm->eq_depth) +
6330                         QMC_ALIGN(sizeof(struct qm_aeqe) * qm->aeq_depth) +
6331                         QMC_ALIGN(sizeof(struct qm_sqc) * qm->qp_num) +
6332                         QMC_ALIGN(sizeof(struct qm_cqc) * qm->qp_num);
6333         qm->qdma.va = dma_alloc_coherent(dev, qm->qdma.size, &qm->qdma.dma,
6334                                          GFP_ATOMIC);
6335         dev_dbg(dev, "allocate qm dma buf size=%zx)\n", qm->qdma.size);
6336         if (!qm->qdma.va) {
6337                 ret = -ENOMEM;
6338                 goto err_destroy_idr;
6339         }
6340
6341         QM_INIT_BUF(qm, eqe, qm->eq_depth);
6342         QM_INIT_BUF(qm, aeqe, qm->aeq_depth);
6343         QM_INIT_BUF(qm, sqc, qm->qp_num);
6344         QM_INIT_BUF(qm, cqc, qm->qp_num);
6345
6346         ret = hisi_qp_alloc_memory(qm);
6347         if (ret)
6348                 goto err_alloc_qp_array;
6349
6350         return 0;
6351
6352 err_alloc_qp_array:
6353         dma_free_coherent(dev, qm->qdma.size, qm->qdma.va, qm->qdma.dma);
6354 err_destroy_idr:
6355         idr_destroy(&qm->qp_idr);
6356         if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps))
6357                 kfree(qm->factor);
6358
6359         return ret;
6360 }
6361
6362 static void qm_last_regs_init(struct hisi_qm *qm)
6363 {
6364         int dfx_regs_num = ARRAY_SIZE(qm_dfx_regs);
6365         struct qm_debug *debug = &qm->debug;
6366         int i;
6367
6368         if (qm->fun_type == QM_HW_VF)
6369                 return;
6370
6371         debug->qm_last_words = kcalloc(dfx_regs_num, sizeof(unsigned int),
6372                                                                 GFP_KERNEL);
6373         if (!debug->qm_last_words)
6374                 return;
6375
6376         for (i = 0; i < dfx_regs_num; i++) {
6377                 debug->qm_last_words[i] = readl_relaxed(qm->io_base +
6378                         qm_dfx_regs[i].offset);
6379         }
6380 }
6381
6382 /**
6383  * hisi_qm_init() - Initialize configures about qm.
6384  * @qm: The qm needing init.
6385  *
6386  * This function init qm, then we can call hisi_qm_start to put qm into work.
6387  */
6388 int hisi_qm_init(struct hisi_qm *qm)
6389 {
6390         struct pci_dev *pdev = qm->pdev;
6391         struct device *dev = &pdev->dev;
6392         int ret;
6393
6394         hisi_qm_pre_init(qm);
6395
6396         ret = hisi_qm_pci_init(qm);
6397         if (ret)
6398                 return ret;
6399
6400         ret = qm_irqs_register(qm);
6401         if (ret)
6402                 goto err_pci_init;
6403
6404         if (qm->fun_type == QM_HW_PF) {
6405                 qm_disable_clock_gate(qm);
6406                 ret = qm_dev_mem_reset(qm);
6407                 if (ret) {
6408                         dev_err(dev, "failed to reset device memory\n");
6409                         goto err_irq_register;
6410                 }
6411         }
6412
6413         if (qm->mode == UACCE_MODE_SVA) {
6414                 ret = qm_alloc_uacce(qm);
6415                 if (ret < 0)
6416                         dev_warn(dev, "fail to alloc uacce (%d)\n", ret);
6417         }
6418
6419         ret = hisi_qm_memory_init(qm);
6420         if (ret)
6421                 goto err_alloc_uacce;
6422
6423         ret = hisi_qm_init_work(qm);
6424         if (ret)
6425                 goto err_free_qm_memory;
6426
6427         qm_cmd_init(qm);
6428         atomic_set(&qm->status.flags, QM_INIT);
6429
6430         qm_last_regs_init(qm);
6431
6432         return 0;
6433
6434 err_free_qm_memory:
6435         hisi_qm_memory_uninit(qm);
6436 err_alloc_uacce:
6437         if (qm->use_sva) {
6438                 uacce_remove(qm->uacce);
6439                 qm->uacce = NULL;
6440         }
6441 err_irq_register:
6442         qm_irqs_unregister(qm);
6443 err_pci_init:
6444         hisi_qm_pci_uninit(qm);
6445         return ret;
6446 }
6447 EXPORT_SYMBOL_GPL(hisi_qm_init);
6448
6449 /**
6450  * hisi_qm_get_dfx_access() - Try to get dfx access.
6451  * @qm: pointer to accelerator device.
6452  *
6453  * Try to get dfx access, then user can get message.
6454  *
6455  * If device is in suspended, return failure, otherwise
6456  * bump up the runtime PM usage counter.
6457  */
6458 int hisi_qm_get_dfx_access(struct hisi_qm *qm)
6459 {
6460         struct device *dev = &qm->pdev->dev;
6461
6462         if (pm_runtime_suspended(dev)) {
6463                 dev_info(dev, "can not read/write - device in suspended.\n");
6464                 return -EAGAIN;
6465         }
6466
6467         return qm_pm_get_sync(qm);
6468 }
6469 EXPORT_SYMBOL_GPL(hisi_qm_get_dfx_access);
6470
6471 /**
6472  * hisi_qm_put_dfx_access() - Put dfx access.
6473  * @qm: pointer to accelerator device.
6474  *
6475  * Put dfx access, drop runtime PM usage counter.
6476  */
6477 void hisi_qm_put_dfx_access(struct hisi_qm *qm)
6478 {
6479         qm_pm_put_sync(qm);
6480 }
6481 EXPORT_SYMBOL_GPL(hisi_qm_put_dfx_access);
6482
6483 /**
6484  * hisi_qm_pm_init() - Initialize qm runtime PM.
6485  * @qm: pointer to accelerator device.
6486  *
6487  * Function that initialize qm runtime PM.
6488  */
6489 void hisi_qm_pm_init(struct hisi_qm *qm)
6490 {
6491         struct device *dev = &qm->pdev->dev;
6492
6493         if (!test_bit(QM_SUPPORT_RPM, &qm->caps))
6494                 return;
6495
6496         pm_runtime_set_autosuspend_delay(dev, QM_AUTOSUSPEND_DELAY);
6497         pm_runtime_use_autosuspend(dev);
6498         pm_runtime_put_noidle(dev);
6499 }
6500 EXPORT_SYMBOL_GPL(hisi_qm_pm_init);
6501
6502 /**
6503  * hisi_qm_pm_uninit() - Uninitialize qm runtime PM.
6504  * @qm: pointer to accelerator device.
6505  *
6506  * Function that uninitialize qm runtime PM.
6507  */
6508 void hisi_qm_pm_uninit(struct hisi_qm *qm)
6509 {
6510         struct device *dev = &qm->pdev->dev;
6511
6512         if (!test_bit(QM_SUPPORT_RPM, &qm->caps))
6513                 return;
6514
6515         pm_runtime_get_noresume(dev);
6516         pm_runtime_dont_use_autosuspend(dev);
6517 }
6518 EXPORT_SYMBOL_GPL(hisi_qm_pm_uninit);
6519
6520 static int qm_prepare_for_suspend(struct hisi_qm *qm)
6521 {
6522         struct pci_dev *pdev = qm->pdev;
6523         int ret;
6524         u32 val;
6525
6526         ret = qm->ops->set_msi(qm, false);
6527         if (ret) {
6528                 pci_err(pdev, "failed to disable MSI before suspending!\n");
6529                 return ret;
6530         }
6531
6532         /* shutdown OOO register */
6533         writel(ACC_MASTER_GLOBAL_CTRL_SHUTDOWN,
6534                qm->io_base + ACC_MASTER_GLOBAL_CTRL);
6535
6536         ret = readl_relaxed_poll_timeout(qm->io_base + ACC_MASTER_TRANS_RETURN,
6537                                          val,
6538                                          (val == ACC_MASTER_TRANS_RETURN_RW),
6539                                          POLL_PERIOD, POLL_TIMEOUT);
6540         if (ret) {
6541                 pci_emerg(pdev, "Bus lock! Please reset system.\n");
6542                 return ret;
6543         }
6544
6545         ret = qm_set_pf_mse(qm, false);
6546         if (ret)
6547                 pci_err(pdev, "failed to disable MSE before suspending!\n");
6548
6549         return ret;
6550 }
6551
6552 static int qm_rebuild_for_resume(struct hisi_qm *qm)
6553 {
6554         struct pci_dev *pdev = qm->pdev;
6555         int ret;
6556
6557         ret = qm_set_pf_mse(qm, true);
6558         if (ret) {
6559                 pci_err(pdev, "failed to enable MSE after resuming!\n");
6560                 return ret;
6561         }
6562
6563         ret = qm->ops->set_msi(qm, true);
6564         if (ret) {
6565                 pci_err(pdev, "failed to enable MSI after resuming!\n");
6566                 return ret;
6567         }
6568
6569         ret = qm_dev_hw_init(qm);
6570         if (ret) {
6571                 pci_err(pdev, "failed to init device after resuming\n");
6572                 return ret;
6573         }
6574
6575         qm_cmd_init(qm);
6576         hisi_qm_dev_err_init(qm);
6577         qm_disable_clock_gate(qm);
6578         ret = qm_dev_mem_reset(qm);
6579         if (ret)
6580                 pci_err(pdev, "failed to reset device memory\n");
6581
6582         return ret;
6583 }
6584
6585 /**
6586  * hisi_qm_suspend() - Runtime suspend of given device.
6587  * @dev: device to suspend.
6588  *
6589  * Function that suspend the device.
6590  */
6591 int hisi_qm_suspend(struct device *dev)
6592 {
6593         struct pci_dev *pdev = to_pci_dev(dev);
6594         struct hisi_qm *qm = pci_get_drvdata(pdev);
6595         int ret;
6596
6597         pci_info(pdev, "entering suspended state\n");
6598
6599         ret = hisi_qm_stop(qm, QM_NORMAL);
6600         if (ret) {
6601                 pci_err(pdev, "failed to stop qm(%d)\n", ret);
6602                 return ret;
6603         }
6604
6605         ret = qm_prepare_for_suspend(qm);
6606         if (ret)
6607                 pci_err(pdev, "failed to prepare suspended(%d)\n", ret);
6608
6609         return ret;
6610 }
6611 EXPORT_SYMBOL_GPL(hisi_qm_suspend);
6612
6613 /**
6614  * hisi_qm_resume() - Runtime resume of given device.
6615  * @dev: device to resume.
6616  *
6617  * Function that resume the device.
6618  */
6619 int hisi_qm_resume(struct device *dev)
6620 {
6621         struct pci_dev *pdev = to_pci_dev(dev);
6622         struct hisi_qm *qm = pci_get_drvdata(pdev);
6623         int ret;
6624
6625         pci_info(pdev, "resuming from suspend state\n");
6626
6627         ret = qm_rebuild_for_resume(qm);
6628         if (ret) {
6629                 pci_err(pdev, "failed to rebuild resume(%d)\n", ret);
6630                 return ret;
6631         }
6632
6633         ret = hisi_qm_start(qm);
6634         if (ret)
6635                 pci_err(pdev, "failed to start qm(%d)\n", ret);
6636
6637         return ret;
6638 }
6639 EXPORT_SYMBOL_GPL(hisi_qm_resume);
6640
6641 MODULE_LICENSE("GPL v2");
6642 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
6643 MODULE_DESCRIPTION("HiSilicon Accelerator queue manager driver");