2 * This file is part of the Chelsio T4/T5/T6 Ethernet driver for Linux.
4 * Copyright (C) 2011-2016 Chelsio Communications. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
10 * Written and Maintained by:
11 * Manoj Malviya (manojmalviya@chelsio.com)
12 * Atul Gupta (atul.gupta@chelsio.com)
13 * Jitendra Lulla (jlulla@chelsio.com)
14 * Yeshaswi M R Gowda (yeshaswi@chelsio.com)
15 * Harsh Jain (harsh@chelsio.com)
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/skbuff.h>
22 #include <crypto/aes.h>
23 #include <crypto/hash.h>
26 #include "chcr_core.h"
27 #include "cxgb4_uld.h"
29 static LIST_HEAD(uld_ctx_list);
30 static DEFINE_MUTEX(dev_mutex);
31 static atomic_t dev_count;
33 typedef int (*chcr_handler_func)(struct chcr_dev *dev, unsigned char *input);
34 static int cpl_fw6_pld_handler(struct chcr_dev *dev, unsigned char *input);
35 static void *chcr_uld_add(const struct cxgb4_lld_info *lld);
36 static int chcr_uld_state_change(void *handle, enum cxgb4_state state);
38 static chcr_handler_func work_handlers[NUM_CPL_CMDS] = {
39 [CPL_FW6_PLD] = cpl_fw6_pld_handler,
42 static struct cxgb4_uld_info chcr_uld_info = {
43 .name = DRV_MODULE_NAME,
44 .nrxq = MAX_ULD_QSETS,
45 .ntxq = MAX_ULD_QSETS,
48 .state_change = chcr_uld_state_change,
49 .rx_handler = chcr_uld_rx_handler,
52 int assign_chcr_device(struct chcr_dev **dev)
54 struct uld_ctx *u_ctx;
58 * Which device to use if multiple devices are available TODO
59 * May be select the device based on round robin. One session
60 * must go to the same device to maintain the ordering.
62 mutex_lock(&dev_mutex); /* TODO ? */
63 list_for_each_entry(u_ctx, &uld_ctx_list, entry)
69 mutex_unlock(&dev_mutex);
73 static int chcr_dev_add(struct uld_ctx *u_ctx)
77 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
81 spin_lock_init(&dev->lock_chcr_dev);
84 atomic_inc(&dev_count);
88 static int chcr_dev_remove(struct uld_ctx *u_ctx)
92 atomic_dec(&dev_count);
96 static int cpl_fw6_pld_handler(struct chcr_dev *dev,
99 struct crypto_async_request *req;
100 struct cpl_fw6_pld *fw6_pld;
101 u32 ack_err_status = 0;
102 int error_status = 0;
104 fw6_pld = (struct cpl_fw6_pld *)input;
105 req = (struct crypto_async_request *)(uintptr_t)be64_to_cpu(
109 ntohl(*(__be32 *)((unsigned char *)&fw6_pld->data[0] + 4));
110 if (ack_err_status) {
111 if (CHK_MAC_ERR_BIT(ack_err_status) ||
112 CHK_PAD_ERR_BIT(ack_err_status))
113 error_status = -EBADMSG;
115 /* call completion callback with failure status */
117 error_status = chcr_handle_resp(req, input, error_status);
119 pr_err("Incorrect request address from the firmware\n");
125 int chcr_send_wr(struct sk_buff *skb)
127 return cxgb4_crypto_send(skb->dev, skb);
130 static void *chcr_uld_add(const struct cxgb4_lld_info *lld)
132 struct uld_ctx *u_ctx;
134 /* Create the device and add it in the device list */
135 u_ctx = kzalloc(sizeof(*u_ctx), GFP_KERNEL);
137 u_ctx = ERR_PTR(-ENOMEM);
141 mutex_lock(&dev_mutex);
142 list_add_tail(&u_ctx->entry, &uld_ctx_list);
143 mutex_unlock(&dev_mutex);
148 int chcr_uld_rx_handler(void *handle, const __be64 *rsp,
149 const struct pkt_gl *pgl)
151 struct uld_ctx *u_ctx = (struct uld_ctx *)handle;
152 struct chcr_dev *dev = u_ctx->dev;
153 const struct cpl_fw6_pld *rpl = (struct cpl_fw6_pld *)rsp;
155 if (rpl->opcode != CPL_FW6_PLD) {
156 pr_err("Unsupported opcode\n");
161 work_handlers[rpl->opcode](dev, (unsigned char *)&rsp[1]);
163 work_handlers[rpl->opcode](dev, pgl->va);
167 static int chcr_uld_state_change(void *handle, enum cxgb4_state state)
169 struct uld_ctx *u_ctx = handle;
175 ret = chcr_dev_add(u_ctx);
179 if (atomic_read(&dev_count) == 1)
180 ret = start_crypto();
183 case CXGB4_STATE_DETACH:
185 mutex_lock(&dev_mutex);
186 chcr_dev_remove(u_ctx);
187 mutex_unlock(&dev_mutex);
189 if (!atomic_read(&dev_count))
193 case CXGB4_STATE_START_RECOVERY:
194 case CXGB4_STATE_DOWN:
201 static int __init chcr_crypto_init(void)
203 if (cxgb4_register_uld(CXGB4_ULD_CRYPTO, &chcr_uld_info))
204 pr_err("ULD register fail: No chcr crypto support in cxgb4");
209 static void __exit chcr_crypto_exit(void)
211 struct uld_ctx *u_ctx, *tmp;
213 if (atomic_read(&dev_count))
216 /* Remove all devices from list */
217 mutex_lock(&dev_mutex);
218 list_for_each_entry_safe(u_ctx, tmp, &uld_ctx_list, entry) {
220 chcr_dev_remove(u_ctx);
223 mutex_unlock(&dev_mutex);
224 cxgb4_unregister_uld(CXGB4_ULD_CRYPTO);
227 module_init(chcr_crypto_init);
228 module_exit(chcr_crypto_exit);
230 MODULE_DESCRIPTION("Crypto Co-processor for Chelsio Terminator cards.");
231 MODULE_LICENSE("GPL");
232 MODULE_AUTHOR("Chelsio Communications");
233 MODULE_VERSION(DRV_VERSION);