1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
5 * ARM CryptoCell Linux Crypto Driver
8 #ifndef __CC_DRIVER_H__
9 #define __CC_DRIVER_H__
12 #include <linux/workqueue.h>
14 #include <linux/interrupt.h>
16 #include <linux/dma-mapping.h>
17 #include <crypto/algapi.h>
18 #include <crypto/internal/skcipher.h>
19 #include <crypto/aes.h>
20 #include <crypto/sha.h>
21 #include <crypto/aead.h>
22 #include <crypto/authenc.h>
23 #include <crypto/hash.h>
24 #include <crypto/skcipher.h>
25 #include <linux/version.h>
26 #include <linux/clk.h>
27 #include <linux/platform_device.h>
29 /* Registers definitions from shared/hw/ree_include */
30 #include "cc_host_regs.h"
31 #define CC_DEV_SHA_MAX 512
32 #include "cc_crypto_ctx.h"
33 #include "cc_hw_queue_defs.h"
34 #include "cc_sram_mgr.h"
36 extern bool cc_dump_desc;
37 extern bool cc_dump_bytes;
39 #define DRV_MODULE_VERSION "5.0"
54 #define CC_COHERENT_CACHE_PARAMS 0xEEE
56 /* Maximum DMA mask supported by IP */
57 #define DMA_BIT_MASK_LEN 48
59 #define CC_AXI_IRQ_MASK ((1 << CC_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \
60 (1 << CC_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \
61 (1 << CC_AXIM_CFG_INFLTMASK_BIT_SHIFT) | \
62 (1 << CC_AXIM_CFG_COMPMASK_BIT_SHIFT))
64 #define CC_AXI_ERR_IRQ_MASK BIT(CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT)
66 #define CC_COMP_IRQ_MASK BIT(CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)
68 #define AXIM_MON_COMP_VALUE GENMASK(CC_AXIM_MON_COMP_VALUE_BIT_SIZE + \
69 CC_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
70 CC_AXIM_MON_COMP_VALUE_BIT_SHIFT)
72 /* Register name mangling macro */
73 #define CC_REG(reg_name) CC_ ## reg_name ## _REG_OFFSET
75 /* TEE FIPS status interrupt */
76 #define CC_GPR0_IRQ_MASK BIT(CC_HOST_IRR_GPR0_BIT_SHIFT)
78 #define CC_CRA_PRIO 400
80 #define MIN_HW_QUEUE_SIZE 50 /* Minimum size required for proper function */
82 #define MAX_REQUEST_QUEUE_SIZE 4096
83 #define MAX_MLLI_BUFF_SIZE 2080
84 #define MAX_ICV_NENTS_SUPPORTED 2
86 /* Definitions for HW descriptors DIN/DOUT fields */
89 /* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID
90 * field in the HW descriptor. The DMA engine +8 that value.
93 #define CC_MAX_IVGEN_DMA_ADDRESSES 3
94 struct cc_crypto_req {
95 void (*user_cb)(struct device *dev, void *req, int err);
97 dma_addr_t ivgen_dma_addr[CC_MAX_IVGEN_DMA_ADDRESSES];
98 /* For the first 'ivgen_dma_addr_len' addresses of this array,
99 * generated IV would be placed in it by send_request().
100 * Same generated IV for all addresses!
102 /* Amount of 'ivgen_dma_addr' elements to be filled. */
103 unsigned int ivgen_dma_addr_len;
104 /* The generated IV size required, 8/16 B allowed. */
105 unsigned int ivgen_size;
106 struct completion seq_compl; /* request completion */
110 * struct cc_drvdata - driver private data context
111 * @cc_base: virt address of the CC registers
112 * @irq: device IRQ number
113 * @irq_mask: Interrupt mask shadow (1 for masked interrupts)
116 void __iomem *cc_base;
119 struct completion hw_queue_avail; /* wait for HW queue availability */
120 struct platform_device *plat_dev;
121 cc_sram_addr_t mlli_sram_addr;
122 void *buff_mgr_handle;
126 void *request_mgr_handle;
129 void *sram_mgr_handle;
134 enum cc_hw_rev hw_rev;
141 struct cc_crypto_alg {
142 struct list_head entry;
144 int flow_mode; /* Note: currently, refers to the cipher mode only. */
146 unsigned int data_unit;
147 struct cc_drvdata *drvdata;
148 struct skcipher_alg skcipher_alg;
149 struct aead_alg aead_alg;
152 struct cc_alg_template {
153 char name[CRYPTO_MAX_ALG_NAME];
154 char driver_name[CRYPTO_MAX_ALG_NAME];
155 unsigned int blocksize;
157 struct skcipher_alg skcipher;
158 struct aead_alg aead;
161 int flow_mode; /* Note: currently, refers to the cipher mode only. */
164 enum cc_std_body std_body;
165 unsigned int data_unit;
166 struct cc_drvdata *drvdata;
169 struct async_gen_req_ctx {
170 dma_addr_t iv_dma_addr;
171 enum drv_crypto_direction op_type;
174 static inline struct device *drvdata_to_dev(struct cc_drvdata *drvdata)
176 return &drvdata->plat_dev->dev;
179 void __dump_byte_array(const char *name, const u8 *buf, size_t len);
180 static inline void dump_byte_array(const char *name, const u8 *the_array,
184 __dump_byte_array(name, the_array, size);
187 int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe);
188 void fini_cc_regs(struct cc_drvdata *drvdata);
189 int cc_clk_on(struct cc_drvdata *drvdata);
190 void cc_clk_off(struct cc_drvdata *drvdata);
191 unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata);
193 static inline void cc_iowrite(struct cc_drvdata *drvdata, u32 reg, u32 val)
195 iowrite32(val, (drvdata->cc_base + reg));
198 static inline u32 cc_ioread(struct cc_drvdata *drvdata, u32 reg)
200 return ioread32(drvdata->cc_base + reg);
203 static inline gfp_t cc_gfp_flags(struct crypto_async_request *req)
205 return (req->flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
206 GFP_KERNEL : GFP_ATOMIC;
209 static inline void set_queue_last_ind(struct cc_drvdata *drvdata,
210 struct cc_hw_desc *pdesc)
212 if (drvdata->hw_rev >= CC_HW_REV_712)
213 set_queue_last_ind_bit(pdesc);
216 #endif /*__CC_DRIVER_H__*/