1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
4 #include <linux/kernel.h>
5 #include <linux/module.h>
7 #include <linux/crypto.h>
8 #include <linux/moduleparam.h>
9 #include <linux/types.h>
10 #include <linux/interrupt.h>
11 #include <linux/platform_device.h>
12 #include <linux/slab.h>
13 #include <linux/spinlock.h>
15 #include <linux/clk.h>
16 #include <linux/of_address.h>
18 #include "cc_driver.h"
19 #include "cc_request_mgr.h"
20 #include "cc_buffer_mgr.h"
21 #include "cc_debugfs.h"
22 #include "cc_cipher.h"
26 #include "cc_sram_mgr.h"
31 module_param_named(dump_desc, cc_dump_desc, bool, 0600);
32 MODULE_PARM_DESC(cc_dump_desc, "Dump descriptors to kernel log as debugging aid");
35 module_param_named(dump_bytes, cc_dump_bytes, bool, 0600);
36 MODULE_PARM_DESC(cc_dump_bytes, "Dump buffers to kernel log as debugging aid");
45 /* Hardware revisions defs. */
47 /* The 703 is a OSCCA only variant of the 713 */
48 static const struct cc_hw_data cc703_hw = {
49 .name = "703", .rev = CC_HW_REV_713, .std_bodies = CC_STD_OSCCA
52 static const struct cc_hw_data cc713_hw = {
53 .name = "713", .rev = CC_HW_REV_713, .std_bodies = CC_STD_ALL
56 static const struct cc_hw_data cc712_hw = {
57 .name = "712", .rev = CC_HW_REV_712, .sig = 0xDCC71200U,
58 .std_bodies = CC_STD_ALL
61 static const struct cc_hw_data cc710_hw = {
62 .name = "710", .rev = CC_HW_REV_710, .sig = 0xDCC63200U,
63 .std_bodies = CC_STD_ALL
66 static const struct cc_hw_data cc630p_hw = {
67 .name = "630P", .rev = CC_HW_REV_630, .sig = 0xDCC63000U,
68 .std_bodies = CC_STD_ALL
71 static const struct of_device_id arm_ccree_dev_of_match[] = {
72 { .compatible = "arm,cryptocell-703-ree", .data = &cc703_hw },
73 { .compatible = "arm,cryptocell-713-ree", .data = &cc713_hw },
74 { .compatible = "arm,cryptocell-712-ree", .data = &cc712_hw },
75 { .compatible = "arm,cryptocell-710-ree", .data = &cc710_hw },
76 { .compatible = "arm,cryptocell-630p-ree", .data = &cc630p_hw },
79 MODULE_DEVICE_TABLE(of, arm_ccree_dev_of_match);
81 void __dump_byte_array(const char *name, const u8 *buf, size_t len)
88 snprintf(prefix, sizeof(prefix), "%s[%zu]: ", name, len);
90 print_hex_dump(KERN_DEBUG, prefix, DUMP_PREFIX_ADDRESS, 16, 1, buf,
94 static irqreturn_t cc_isr(int irq, void *dev_id)
96 struct cc_drvdata *drvdata = (struct cc_drvdata *)dev_id;
97 struct device *dev = drvdata_to_dev(drvdata);
101 /* STAT_OP_TYPE_GENERIC STAT_PHASE_0: Interrupt */
103 /* read the interrupt status */
104 irr = cc_ioread(drvdata, CC_REG(HOST_IRR));
105 dev_dbg(dev, "Got IRR=0x%08X\n", irr);
107 if (irr == 0) /* Probably shared interrupt line */
110 imr = cc_ioread(drvdata, CC_REG(HOST_IMR));
112 /* clear interrupt - must be before processing events */
113 cc_iowrite(drvdata, CC_REG(HOST_ICR), irr);
116 /* Completion interrupt - most probable */
117 if (irr & CC_COMP_IRQ_MASK) {
118 /* Mask AXI completion interrupt - will be unmasked in
119 * Deferred service handler
121 cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | CC_COMP_IRQ_MASK);
122 irr &= ~CC_COMP_IRQ_MASK;
123 complete_request(drvdata);
125 #ifdef CONFIG_CRYPTO_FIPS
126 /* TEE FIPS interrupt */
127 if (irr & CC_GPR0_IRQ_MASK) {
128 /* Mask interrupt - will be unmasked in Deferred service
131 cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | CC_GPR0_IRQ_MASK);
132 irr &= ~CC_GPR0_IRQ_MASK;
133 fips_handler(drvdata);
136 /* AXI error interrupt */
137 if (irr & CC_AXI_ERR_IRQ_MASK) {
140 /* Read the AXI error ID */
141 axi_err = cc_ioread(drvdata, CC_REG(AXIM_MON_ERR));
142 dev_dbg(dev, "AXI completion error: axim_mon_err=0x%08X\n",
145 irr &= ~CC_AXI_ERR_IRQ_MASK;
149 dev_dbg_ratelimited(dev, "IRR includes unknown cause bits (0x%08X)\n",
157 int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe)
159 unsigned int val, cache_params;
160 struct device *dev = drvdata_to_dev(drvdata);
162 /* Unmask all AXI interrupt sources AXI_CFG1 register */
163 val = cc_ioread(drvdata, CC_REG(AXIM_CFG));
164 cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~CC_AXI_IRQ_MASK);
165 dev_dbg(dev, "AXIM_CFG=0x%08X\n",
166 cc_ioread(drvdata, CC_REG(AXIM_CFG)));
168 /* Clear all pending interrupts */
169 val = cc_ioread(drvdata, CC_REG(HOST_IRR));
170 dev_dbg(dev, "IRR=0x%08X\n", val);
171 cc_iowrite(drvdata, CC_REG(HOST_ICR), val);
173 /* Unmask relevant interrupt cause */
174 val = CC_COMP_IRQ_MASK | CC_AXI_ERR_IRQ_MASK;
176 if (drvdata->hw_rev >= CC_HW_REV_712)
177 val |= CC_GPR0_IRQ_MASK;
179 cc_iowrite(drvdata, CC_REG(HOST_IMR), ~val);
181 cache_params = (drvdata->coherent ? CC_COHERENT_CACHE_PARAMS : 0x0);
183 val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS));
186 dev_dbg(dev, "Cache params previous: 0x%08X\n", val);
188 cc_iowrite(drvdata, CC_REG(AXIM_CACHE_PARAMS), cache_params);
189 val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS));
192 dev_dbg(dev, "Cache params current: 0x%08X (expect: 0x%08X)\n",
198 static int init_cc_resources(struct platform_device *plat_dev)
200 struct resource *req_mem_cc_regs = NULL;
201 struct cc_drvdata *new_drvdata;
202 struct device *dev = &plat_dev->dev;
203 struct device_node *np = dev->of_node;
206 const struct cc_hw_data *hw_rev;
207 const struct of_device_id *dev_id;
211 new_drvdata = devm_kzalloc(dev, sizeof(*new_drvdata), GFP_KERNEL);
215 dev_id = of_match_node(arm_ccree_dev_of_match, np);
219 hw_rev = (struct cc_hw_data *)dev_id->data;
220 new_drvdata->hw_rev_name = hw_rev->name;
221 new_drvdata->hw_rev = hw_rev->rev;
222 new_drvdata->std_bodies = hw_rev->std_bodies;
224 if (hw_rev->rev >= CC_HW_REV_712) {
225 new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP);
226 new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_712);
227 new_drvdata->ver_offset = CC_REG(HOST_VERSION_712);
229 new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP8);
230 new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_630);
231 new_drvdata->ver_offset = CC_REG(HOST_VERSION_630);
234 platform_set_drvdata(plat_dev, new_drvdata);
235 new_drvdata->plat_dev = plat_dev;
237 clk = devm_clk_get(dev, NULL);
239 switch (PTR_ERR(clk)) {
240 /* Clock is optional so this might be fine */
244 /* Clock not available, let's try again soon */
246 return -EPROBE_DEFER;
249 dev_err(dev, "Error getting clock: %ld\n",
253 new_drvdata->clk = clk;
255 new_drvdata->coherent = of_dma_is_coherent(np);
257 /* Get device resources */
258 /* First CC registers space */
259 req_mem_cc_regs = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);
260 /* Map registers space */
261 new_drvdata->cc_base = devm_ioremap_resource(dev, req_mem_cc_regs);
262 if (IS_ERR(new_drvdata->cc_base)) {
263 dev_err(dev, "Failed to ioremap registers");
264 return PTR_ERR(new_drvdata->cc_base);
267 dev_dbg(dev, "Got MEM resource (%s): %pR\n", req_mem_cc_regs->name,
269 dev_dbg(dev, "CC registers mapped from %pa to 0x%p\n",
270 &req_mem_cc_regs->start, new_drvdata->cc_base);
273 new_drvdata->irq = platform_get_irq(plat_dev, 0);
274 if (new_drvdata->irq < 0) {
275 dev_err(dev, "Failed getting IRQ resource\n");
276 return new_drvdata->irq;
279 rc = devm_request_irq(dev, new_drvdata->irq, cc_isr,
280 IRQF_SHARED, "ccree", new_drvdata);
282 dev_err(dev, "Could not register to interrupt %d\n",
286 dev_dbg(dev, "Registered to IRQ: %d\n", new_drvdata->irq);
288 init_completion(&new_drvdata->hw_queue_avail);
290 if (!plat_dev->dev.dma_mask)
291 plat_dev->dev.dma_mask = &plat_dev->dev.coherent_dma_mask;
293 dma_mask = DMA_BIT_MASK(DMA_BIT_MASK_LEN);
294 while (dma_mask > 0x7fffffffUL) {
295 if (dma_supported(&plat_dev->dev, dma_mask)) {
296 rc = dma_set_coherent_mask(&plat_dev->dev, dma_mask);
304 dev_err(dev, "Failed in dma_set_mask, mask=%llx\n", dma_mask);
308 rc = cc_clk_on(new_drvdata);
310 dev_err(dev, "Failed to enable clock");
314 if (hw_rev->rev <= CC_HW_REV_712) {
315 /* Verify correct mapping */
316 signature_val = cc_ioread(new_drvdata, new_drvdata->sig_offset);
317 if (signature_val != hw_rev->sig) {
318 dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n",
319 signature_val, hw_rev->sig);
323 dev_dbg(dev, "CC SIGNATURE=0x%08X\n", signature_val);
326 /* Display HW versions */
327 dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X, Driver version %s\n",
328 hw_rev->name, cc_ioread(new_drvdata, new_drvdata->ver_offset),
331 rc = init_cc_regs(new_drvdata, true);
333 dev_err(dev, "init_cc_regs failed\n");
337 rc = cc_debugfs_init(new_drvdata);
339 dev_err(dev, "Failed registering debugfs interface\n");
343 rc = cc_fips_init(new_drvdata);
345 dev_err(dev, "CC_FIPS_INIT failed 0x%x\n", rc);
346 goto post_debugfs_err;
348 rc = cc_sram_mgr_init(new_drvdata);
350 dev_err(dev, "cc_sram_mgr_init failed\n");
351 goto post_fips_init_err;
354 new_drvdata->mlli_sram_addr =
355 cc_sram_alloc(new_drvdata, MAX_MLLI_BUFF_SIZE);
356 if (new_drvdata->mlli_sram_addr == NULL_SRAM_ADDR) {
357 dev_err(dev, "Failed to alloc MLLI Sram buffer\n");
359 goto post_sram_mgr_err;
362 rc = cc_req_mgr_init(new_drvdata);
364 dev_err(dev, "cc_req_mgr_init failed\n");
365 goto post_sram_mgr_err;
368 rc = cc_buffer_mgr_init(new_drvdata);
370 dev_err(dev, "buffer_mgr_init failed\n");
371 goto post_req_mgr_err;
374 rc = cc_pm_init(new_drvdata);
376 dev_err(dev, "ssi_power_mgr_init failed\n");
377 goto post_buf_mgr_err;
380 rc = cc_ivgen_init(new_drvdata);
382 dev_err(dev, "cc_ivgen_init failed\n");
383 goto post_buf_mgr_err;
386 /* Allocate crypto algs */
387 rc = cc_cipher_alloc(new_drvdata);
389 dev_err(dev, "cc_cipher_alloc failed\n");
393 /* hash must be allocated before aead since hash exports APIs */
394 rc = cc_hash_alloc(new_drvdata);
396 dev_err(dev, "cc_hash_alloc failed\n");
397 goto post_cipher_err;
400 rc = cc_aead_alloc(new_drvdata);
402 dev_err(dev, "cc_aead_alloc failed\n");
406 /* All set, we can allow autosuspend */
407 cc_pm_go(new_drvdata);
409 /* If we got here and FIPS mode is enabled
410 * it means all FIPS test passed, so let TEE
413 cc_set_ree_fips_status(new_drvdata, true);
418 cc_hash_free(new_drvdata);
420 cc_cipher_free(new_drvdata);
422 cc_ivgen_fini(new_drvdata);
424 cc_buffer_mgr_fini(new_drvdata);
426 cc_req_mgr_fini(new_drvdata);
428 cc_sram_mgr_fini(new_drvdata);
430 cc_fips_fini(new_drvdata);
432 cc_debugfs_fini(new_drvdata);
434 fini_cc_regs(new_drvdata);
436 cc_clk_off(new_drvdata);
440 void fini_cc_regs(struct cc_drvdata *drvdata)
442 /* Mask all interrupts */
443 cc_iowrite(drvdata, CC_REG(HOST_IMR), 0xFFFFFFFF);
446 static void cleanup_cc_resources(struct platform_device *plat_dev)
448 struct cc_drvdata *drvdata =
449 (struct cc_drvdata *)platform_get_drvdata(plat_dev);
451 cc_aead_free(drvdata);
452 cc_hash_free(drvdata);
453 cc_cipher_free(drvdata);
454 cc_ivgen_fini(drvdata);
456 cc_buffer_mgr_fini(drvdata);
457 cc_req_mgr_fini(drvdata);
458 cc_sram_mgr_fini(drvdata);
459 cc_fips_fini(drvdata);
460 cc_debugfs_fini(drvdata);
461 fini_cc_regs(drvdata);
465 int cc_clk_on(struct cc_drvdata *drvdata)
467 struct clk *clk = drvdata->clk;
471 /* Not all devices have a clock associated with CCREE */
474 rc = clk_prepare_enable(clk);
481 unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata)
483 if (drvdata->hw_rev >= CC_HW_REV_712)
484 return HASH_LEN_SIZE_712;
486 return HASH_LEN_SIZE_630;
489 void cc_clk_off(struct cc_drvdata *drvdata)
491 struct clk *clk = drvdata->clk;
494 /* Not all devices have a clock associated with CCREE */
497 clk_disable_unprepare(clk);
500 static int ccree_probe(struct platform_device *plat_dev)
503 struct device *dev = &plat_dev->dev;
505 /* Map registers space */
506 rc = init_cc_resources(plat_dev);
510 dev_info(dev, "ARM ccree device initialized\n");
515 static int ccree_remove(struct platform_device *plat_dev)
517 struct device *dev = &plat_dev->dev;
519 dev_dbg(dev, "Releasing ccree resources...\n");
521 cleanup_cc_resources(plat_dev);
523 dev_info(dev, "ARM ccree device terminated\n");
528 static struct platform_driver ccree_driver = {
531 .of_match_table = arm_ccree_dev_of_match,
536 .probe = ccree_probe,
537 .remove = ccree_remove,
540 static int __init ccree_init(void)
542 cc_hash_global_init();
543 cc_debugfs_global_init();
545 return platform_driver_register(&ccree_driver);
547 module_init(ccree_init);
549 static void __exit ccree_exit(void)
551 platform_driver_unregister(&ccree_driver);
552 cc_debugfs_global_fini();
554 module_exit(ccree_exit);
556 /* Module description */
557 MODULE_DESCRIPTION("ARM TrustZone CryptoCell REE Driver");
558 MODULE_VERSION(DRV_MODULE_VERSION);
559 MODULE_AUTHOR("ARM");
560 MODULE_LICENSE("GPL v2");