drivers/crypto/caam/ctrl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* * CAAM control-plane driver backend
   3  * Controller-level driver, kernel property detection, initialization
   4  *
   5  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   6  * Copyright 2018 NXP
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/of_address.h>
  11 #include <linux/of_irq.h>
  12 #include <linux/sys_soc.h>
  13
  14 #include "compat.h"
  15 #include "regs.h"
  16 #include "intern.h"
  17 #include "jr.h"
  18 #include "desc_constr.h"
  19 #include "ctrl.h"
  20
  21 bool caam_dpaa2;
  22 EXPORT_SYMBOL(caam_dpaa2);
  23
  24 #ifdef CONFIG_CAAM_QI
  25 #include "qi.h"
  26 #endif
  27
  28 /*
  29  * i.MX targets tend to have clock control subsystems that can
  30  * enable/disable clocking to our device.
  31  */
  32 static inline struct clk *caam_drv_identify_clk(struct device *dev,
  33                                                 char *clk_name)
  34 {
  35         return caam_imx ? devm_clk_get(dev, clk_name) : NULL;
  36 }
  37
  38 /*
  39  * Descriptor to instantiate RNG State Handle 0 in normal mode and
  40  * load the JDKEK, TDKEK and TDSK registers
  41  */
  42 static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
  43 {
  44         u32 *jump_cmd, op_flags;
  45
  46         init_job_desc(desc, 0);
  47
  48         op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  49                         (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT;
  50
  51         /* INIT RNG in non-test mode */
  52         append_operation(desc, op_flags);
  53
  54         if (!handle && do_sk) {
  55                 /*
  56                  * For SH0, Secure Keys must be generated as well
  57                  */
  58
  59                 /* wait for done */
  60                 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
  61                 set_jump_tgt_here(desc, jump_cmd);
  62
  63                 /*
  64                  * load 1 to clear written reg:
  65                  * resets the done interrrupt and returns the RNG to idle.
  66                  */
  67                 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
  68
  69                 /* Initialize State Handle  */
  70                 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  71                                  OP_ALG_AAI_RNG4_SK);
  72         }
  73
  74         append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
  75 }
  76
  77 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
  78 static void build_deinstantiation_desc(u32 *desc, int handle)
  79 {
  80         init_job_desc(desc, 0);
  81
  82         /* Uninstantiate State Handle 0 */
  83         append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  84                          (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
  85
  86         append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
  87 }
  88
  89 /*
  90  * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
  91  *                        the software (no JR/QI used).
  92  * @ctrldev - pointer to device
  93  * @status - descriptor status, after being run
  94  *
  95  * Return: - 0 if no error occurred
  96  *         - -ENODEV if the DECO couldn't be acquired
  97  *         - -EAGAIN if an error occurred while executing the descriptor
  98  */
  99 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
 100                                         u32 *status)
 101 {
 102         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 103         struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
 104         struct caam_deco __iomem *deco = ctrlpriv->deco;
 105         unsigned int timeout = 100000;
 106         u32 deco_dbg_reg, deco_state, flags;
 107         int i;
 108
 109
 110         if (ctrlpriv->virt_en == 1) {
 111                 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
 112
 113                 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
 114                        --timeout)
 115                         cpu_relax();
 116
 117                 timeout = 100000;
 118         }
 119
 120         clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
 121
 122         while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
 123                                                                  --timeout)
 124                 cpu_relax();
 125
 126         if (!timeout) {
 127                 dev_err(ctrldev, "failed to acquire DECO 0\n");
 128                 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 129                 return -ENODEV;
 130         }
 131
 132         for (i = 0; i < desc_len(desc); i++)
 133                 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
 134
 135         flags = DECO_JQCR_WHL;
 136         /*
 137          * If the descriptor length is longer than 4 words, then the
 138          * FOUR bit in JRCTRL register must be set.
 139          */
 140         if (desc_len(desc) >= 4)
 141                 flags |= DECO_JQCR_FOUR;
 142
 143         /* Instruct the DECO to execute it */
 144         clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
 145
 146         timeout = 10000000;
 147         do {
 148                 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
 149
 150                 if (ctrlpriv->era < 10)
 151                         deco_state = (deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) >>
 152                                      DESC_DBG_DECO_STAT_SHIFT;
 153                 else
 154                         deco_state = (rd_reg32(&deco->dbg_exec) &
 155                                       DESC_DER_DECO_STAT_MASK) >>
 156                                      DESC_DER_DECO_STAT_SHIFT;
 157
 158                 /*
 159                  * If an error occured in the descriptor, then
 160                  * the DECO status field will be set to 0x0D
 161                  */
 162                 if (deco_state == DECO_STAT_HOST_ERR)
 163                         break;
 164
 165                 cpu_relax();
 166         } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
 167
 168         *status = rd_reg32(&deco->op_status_hi) &
 169                   DECO_OP_STATUS_HI_ERR_MASK;
 170
 171         if (ctrlpriv->virt_en == 1)
 172                 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
 173
 174         /* Mark the DECO as free */
 175         clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 176
 177         if (!timeout)
 178                 return -EAGAIN;
 179
 180         return 0;
 181 }
 182
 183 /*
 184  * instantiate_rng - builds and executes a descriptor on DECO0,
 185  *                   which initializes the RNG block.
 186  * @ctrldev - pointer to device
 187  * @state_handle_mask - bitmask containing the instantiation status
 188  *                      for the RNG4 state handles which exist in
 189  *                      the RNG4 block: 1 if it's been instantiated
 190  *                      by an external entry, 0 otherwise.
 191  * @gen_sk  - generate data to be loaded into the JDKEK, TDKEK and TDSK;
 192  *            Caution: this can be done only once; if the keys need to be
 193  *            regenerated, a POR is required
 194  *
 195  * Return: - 0 if no error occurred
 196  *         - -ENOMEM if there isn't enough memory to allocate the descriptor
 197  *         - -ENODEV if DECO0 couldn't be acquired
 198  *         - -EAGAIN if an error occurred when executing the descriptor
 199  *            f.i. there was a RNG hardware error due to not "good enough"
 200  *            entropy being aquired.
 201  */
 202 static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
 203                            int gen_sk)
 204 {
 205         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 206         struct caam_ctrl __iomem *ctrl;
 207         u32 *desc, status = 0, rdsta_val;
 208         int ret = 0, sh_idx;
 209
 210         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 211         desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
 212         if (!desc)
 213                 return -ENOMEM;
 214
 215         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 216                 /*
 217                  * If the corresponding bit is set, this state handle
 218                  * was initialized by somebody else, so it's left alone.
 219                  */
 220                 if ((1 << sh_idx) & state_handle_mask)
 221                         continue;
 222
 223                 /* Create the descriptor for instantiating RNG State Handle */
 224                 build_instantiation_desc(desc, sh_idx, gen_sk);
 225
 226                 /* Try to run it through DECO0 */
 227                 ret = run_descriptor_deco0(ctrldev, desc, &status);
 228
 229                 /*
 230                  * If ret is not 0, or descriptor status is not 0, then
 231                  * something went wrong. No need to try the next state
 232                  * handle (if available), bail out here.
 233                  * Also, if for some reason, the State Handle didn't get
 234                  * instantiated although the descriptor has finished
 235                  * without any error (HW optimizations for later
 236                  * CAAM eras), then try again.
 237                  */
 238                 if (ret)
 239                         break;
 240
 241                 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
 242                 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
 243                     !(rdsta_val & (1 << sh_idx))) {
 244                         ret = -EAGAIN;
 245                         break;
 246                 }
 247
 248                 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
 249                 /* Clear the contents before recreating the descriptor */
 250                 memset(desc, 0x00, CAAM_CMD_SZ * 7);
 251         }
 252
 253         kfree(desc);
 254
 255         return ret;
 256 }
 257
 258 /*
 259  * deinstantiate_rng - builds and executes a descriptor on DECO0,
 260  *                     which deinitializes the RNG block.
 261  * @ctrldev - pointer to device
 262  * @state_handle_mask - bitmask containing the instantiation status
 263  *                      for the RNG4 state handles which exist in
 264  *                      the RNG4 block: 1 if it's been instantiated
 265  *
 266  * Return: - 0 if no error occurred
 267  *         - -ENOMEM if there isn't enough memory to allocate the descriptor
 268  *         - -ENODEV if DECO0 couldn't be acquired
 269  *         - -EAGAIN if an error occurred when executing the descriptor
 270  */
 271 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
 272 {
 273         u32 *desc, status;
 274         int sh_idx, ret = 0;
 275
 276         desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
 277         if (!desc)
 278                 return -ENOMEM;
 279
 280         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 281                 /*
 282                  * If the corresponding bit is set, then it means the state
 283                  * handle was initialized by us, and thus it needs to be
 284                  * deinitialized as well
 285                  */
 286                 if ((1 << sh_idx) & state_handle_mask) {
 287                         /*
 288                          * Create the descriptor for deinstantating this state
 289                          * handle
 290                          */
 291                         build_deinstantiation_desc(desc, sh_idx);
 292
 293                         /* Try to run it through DECO0 */
 294                         ret = run_descriptor_deco0(ctrldev, desc, &status);
 295
 296                         if (ret ||
 297                             (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
 298                                 dev_err(ctrldev,
 299                                         "Failed to deinstantiate RNG4 SH%d\n",
 300                                         sh_idx);
 301                                 break;
 302                         }
 303                         dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
 304                 }
 305         }
 306
 307         kfree(desc);
 308
 309         return ret;
 310 }
 311
 312 static int caam_remove(struct platform_device *pdev)
 313 {
 314         struct device *ctrldev;
 315         struct caam_drv_private *ctrlpriv;
 316         struct caam_ctrl __iomem *ctrl;
 317
 318         ctrldev = &pdev->dev;
 319         ctrlpriv = dev_get_drvdata(ctrldev);
 320         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 321
 322         /* Remove platform devices under the crypto node */
 323         of_platform_depopulate(ctrldev);
 324
 325 #ifdef CONFIG_CAAM_QI
 326         if (ctrlpriv->qidev)
 327                 caam_qi_shutdown(ctrlpriv->qidev);
 328 #endif
 329
 330         /*
 331          * De-initialize RNG state handles initialized by this driver.
 332          * In case of SoCs with Management Complex, RNG is managed by MC f/w.
 333          */
 334         if (!ctrlpriv->mc_en && ctrlpriv->rng4_sh_init)
 335                 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
 336
 337         /* Shut down debug views */
 338 #ifdef CONFIG_DEBUG_FS
 339         debugfs_remove_recursive(ctrlpriv->dfs_root);
 340 #endif
 341
 342         /* Unmap controller region */
 343         iounmap(ctrl);
 344
 345         /* shut clocks off before finalizing shutdown */
 346         clk_disable_unprepare(ctrlpriv->caam_ipg);
 347         if (ctrlpriv->caam_mem)
 348                 clk_disable_unprepare(ctrlpriv->caam_mem);
 349         clk_disable_unprepare(ctrlpriv->caam_aclk);
 350         if (ctrlpriv->caam_emi_slow)
 351                 clk_disable_unprepare(ctrlpriv->caam_emi_slow);
 352         return 0;
 353 }
 354
 355 /*
 356  * kick_trng - sets the various parameters for enabling the initialization
 357  *             of the RNG4 block in CAAM
 358  * @pdev - pointer to the platform device
 359  * @ent_delay - Defines the length (in system clocks) of each entropy sample.
 360  */
 361 static void kick_trng(struct platform_device *pdev, int ent_delay)
 362 {
 363         struct device *ctrldev = &pdev->dev;
 364         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 365         struct caam_ctrl __iomem *ctrl;
 366         struct rng4tst __iomem *r4tst;
 367         u32 val;
 368
 369         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 370         r4tst = &ctrl->r4tst[0];
 371
 372         /* put RNG4 into program mode */
 373         clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM);
 374
 375         /*
 376          * Performance-wise, it does not make sense to
 377          * set the delay to a value that is lower
 378          * than the last one that worked (i.e. the state handles
 379          * were instantiated properly. Thus, instead of wasting
 380          * time trying to set the values controlling the sample
 381          * frequency, the function simply returns.
 382          */
 383         val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
 384               >> RTSDCTL_ENT_DLY_SHIFT;
 385         if (ent_delay <= val)
 386                 goto start_rng;
 387
 388         val = rd_reg32(&r4tst->rtsdctl);
 389         val = (val & ~RTSDCTL_ENT_DLY_MASK) |
 390               (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
 391         wr_reg32(&r4tst->rtsdctl, val);
 392         /* min. freq. count, equal to 1/4 of the entropy sample length */
 393         wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
 394         /* disable maximum frequency count */
 395         wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
 396         /* read the control register */
 397         val = rd_reg32(&r4tst->rtmctl);
 398 start_rng:
 399         /*
 400          * select raw sampling in both entropy shifter
 401          * and statistical checker; ; put RNG4 into run mode
 402          */
 403         clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC);
 404 }
 405
 406 static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl)
 407 {
 408         static const struct {
 409                 u16 ip_id;
 410                 u8 maj_rev;
 411                 u8 era;
 412         } id[] = {
 413                 {0x0A10, 1, 1},
 414                 {0x0A10, 2, 2},
 415                 {0x0A12, 1, 3},
 416                 {0x0A14, 1, 3},
 417                 {0x0A14, 2, 4},
 418                 {0x0A16, 1, 4},
 419                 {0x0A10, 3, 4},
 420                 {0x0A11, 1, 4},
 421                 {0x0A18, 1, 4},
 422                 {0x0A11, 2, 5},
 423                 {0x0A12, 2, 5},
 424                 {0x0A13, 1, 5},
 425                 {0x0A1C, 1, 5}
 426         };
 427         u32 ccbvid, id_ms;
 428         u8 maj_rev, era;
 429         u16 ip_id;
 430         int i;
 431
 432         ccbvid = rd_reg32(&ctrl->perfmon.ccb_id);
 433         era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
 434         if (era)        /* This is '0' prior to CAAM ERA-6 */
 435                 return era;
 436
 437         id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms);
 438         ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
 439         maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
 440
 441         for (i = 0; i < ARRAY_SIZE(id); i++)
 442                 if (id[i].ip_id == ip_id && id[i].maj_rev == maj_rev)
 443                         return id[i].era;
 444
 445         return -ENOTSUPP;
 446 }
 447
 448 /**
 449  * caam_get_era() - Return the ERA of the SEC on SoC, based
 450  * on "sec-era" optional property in the DTS. This property is updated
 451  * by u-boot.
 452  * In case this property is not passed an attempt to retrieve the CAAM
 453  * era via register reads will be made.
 454  **/
 455 static int caam_get_era(struct caam_ctrl __iomem *ctrl)
 456 {
 457         struct device_node *caam_node;
 458         int ret;
 459         u32 prop;
 460
 461         caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
 462         ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
 463         of_node_put(caam_node);
 464
 465         if (!ret)
 466                 return prop;
 467         else
 468                 return caam_get_era_from_hw(ctrl);
 469 }
 470
 471 /*
 472  * ERRATA: imx6 devices (imx6D, imx6Q, imx6DL, imx6S, imx6DP and imx6DQ)
 473  * have an issue wherein AXI bus transactions may not occur in the correct
 474  * order. This isn't a problem running single descriptors, but can be if
 475  * running multiple concurrent descriptors. Reworking the driver to throttle
 476  * to single requests is impractical, thus the workaround is to limit the AXI
 477  * pipeline to a depth of 1 (from it's default of 4) to preclude this situation
 478  * from occurring.
 479  */
 480 static void handle_imx6_err005766(u32 *mcr)
 481 {
 482         if (of_machine_is_compatible("fsl,imx6q") ||
 483             of_machine_is_compatible("fsl,imx6dl") ||
 484             of_machine_is_compatible("fsl,imx6qp"))
 485                 clrsetbits_32(mcr, MCFGR_AXIPIPE_MASK,
 486                               1 << MCFGR_AXIPIPE_SHIFT);
 487 }
 488
 489 static const struct of_device_id caam_match[] = {
 490         {
 491                 .compatible = "fsl,sec-v4.0",
 492         },
 493         {
 494                 .compatible = "fsl,sec4.0",
 495         },
 496         {},
 497 };
 498 MODULE_DEVICE_TABLE(of, caam_match);
 499
 500 /* Probe routine for CAAM top (controller) level */
 501 static int caam_probe(struct platform_device *pdev)
 502 {
 503         int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
 504         u64 caam_id;
 505         static const struct soc_device_attribute imx_soc[] = {
 506                 {.family = "Freescale i.MX"},
 507                 {},
 508         };
 509         struct device *dev;
 510         struct device_node *nprop, *np;
 511         struct caam_ctrl __iomem *ctrl;
 512         struct caam_drv_private *ctrlpriv;
 513         struct clk *clk;
 514 #ifdef CONFIG_DEBUG_FS
 515         struct caam_perfmon *perfmon;
 516 #endif
 517         u32 scfgr, comp_params;
 518         u8 rng_vid;
 519         int pg_size;
 520         int BLOCK_OFFSET = 0;
 521
 522         ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
 523         if (!ctrlpriv)
 524                 return -ENOMEM;
 525
 526         dev = &pdev->dev;
 527         dev_set_drvdata(dev, ctrlpriv);
 528         nprop = pdev->dev.of_node;
 529
 530         caam_imx = (bool)soc_device_match(imx_soc);
 531
 532         /* Enable clocking */
 533         clk = caam_drv_identify_clk(&pdev->dev, "ipg");
 534         if (IS_ERR(clk)) {
 535                 ret = PTR_ERR(clk);
 536                 dev_err(&pdev->dev,
 537                         "can't identify CAAM ipg clk: %d\n", ret);
 538                 return ret;
 539         }
 540         ctrlpriv->caam_ipg = clk;
 541
 542         if (!of_machine_is_compatible("fsl,imx7d") &&
 543             !of_machine_is_compatible("fsl,imx7s")) {
 544                 clk = caam_drv_identify_clk(&pdev->dev, "mem");
 545                 if (IS_ERR(clk)) {
 546                         ret = PTR_ERR(clk);
 547                         dev_err(&pdev->dev,
 548                                 "can't identify CAAM mem clk: %d\n", ret);
 549                         return ret;
 550                 }
 551                 ctrlpriv->caam_mem = clk;
 552         }
 553
 554         clk = caam_drv_identify_clk(&pdev->dev, "aclk");
 555         if (IS_ERR(clk)) {
 556                 ret = PTR_ERR(clk);
 557                 dev_err(&pdev->dev,
 558                         "can't identify CAAM aclk clk: %d\n", ret);
 559                 return ret;
 560         }
 561         ctrlpriv->caam_aclk = clk;
 562
 563         if (!of_machine_is_compatible("fsl,imx6ul") &&
 564             !of_machine_is_compatible("fsl,imx7d") &&
 565             !of_machine_is_compatible("fsl,imx7s")) {
 566                 clk = caam_drv_identify_clk(&pdev->dev, "emi_slow");
 567                 if (IS_ERR(clk)) {
 568                         ret = PTR_ERR(clk);
 569                         dev_err(&pdev->dev,
 570                                 "can't identify CAAM emi_slow clk: %d\n", ret);
 571                         return ret;
 572                 }
 573                 ctrlpriv->caam_emi_slow = clk;
 574         }
 575
 576         ret = clk_prepare_enable(ctrlpriv->caam_ipg);
 577         if (ret < 0) {
 578                 dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
 579                 return ret;
 580         }
 581
 582         if (ctrlpriv->caam_mem) {
 583                 ret = clk_prepare_enable(ctrlpriv->caam_mem);
 584                 if (ret < 0) {
 585                         dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n",
 586                                 ret);
 587                         goto disable_caam_ipg;
 588                 }
 589         }
 590
 591         ret = clk_prepare_enable(ctrlpriv->caam_aclk);
 592         if (ret < 0) {
 593                 dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
 594                 goto disable_caam_mem;
 595         }
 596
 597         if (ctrlpriv->caam_emi_slow) {
 598                 ret = clk_prepare_enable(ctrlpriv->caam_emi_slow);
 599                 if (ret < 0) {
 600                         dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
 601                                 ret);
 602                         goto disable_caam_aclk;
 603                 }
 604         }
 605
 606         /* Get configuration properties from device tree */
 607         /* First, get register page */
 608         ctrl = of_iomap(nprop, 0);
 609         if (ctrl == NULL) {
 610                 dev_err(dev, "caam: of_iomap() failed\n");
 611                 ret = -ENOMEM;
 612                 goto disable_caam_emi_slow;
 613         }
 614
 615         caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
 616                                   (CSTA_PLEND | CSTA_ALT_PLEND));
 617
 618         /* Finding the page size for using the CTPR_MS register */
 619         comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
 620         pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
 621
 622         /* Allocating the BLOCK_OFFSET based on the supported page size on
 623          * the platform
 624          */
 625         if (pg_size == 0)
 626                 BLOCK_OFFSET = PG_SIZE_4K;
 627         else
 628                 BLOCK_OFFSET = PG_SIZE_64K;
 629
 630         ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
 631         ctrlpriv->assure = (struct caam_assurance __iomem __force *)
 632                            ((__force uint8_t *)ctrl +
 633                             BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
 634                            );
 635         ctrlpriv->deco = (struct caam_deco __iomem __force *)
 636                          ((__force uint8_t *)ctrl +
 637                          BLOCK_OFFSET * DECO_BLOCK_NUMBER
 638                          );
 639
 640         /* Get the IRQ of the controller (for security violations only) */
 641         ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
 642
 643         /*
 644          * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
 645          * long pointers in master configuration register.
 646          * In case of SoCs with Management Complex, MC f/w performs
 647          * the configuration.
 648          */
 649         caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
 650         np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");
 651         ctrlpriv->mc_en = !!np;
 652         of_node_put(np);
 653
 654         if (!ctrlpriv->mc_en)
 655                 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR,
 656                               MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
 657                               MCFGR_WDENABLE | MCFGR_LARGE_BURST |
 658                               (sizeof(dma_addr_t) == sizeof(u64) ?
 659                                MCFGR_LONG_PTR : 0));
 660
 661         handle_imx6_err005766(&ctrl->mcr);
 662
 663         /*
 664          *  Read the Compile Time paramters and SCFGR to determine
 665          * if Virtualization is enabled for this platform
 666          */
 667         scfgr = rd_reg32(&ctrl->scfgr);
 668
 669         ctrlpriv->virt_en = 0;
 670         if (comp_params & CTPR_MS_VIRT_EN_INCL) {
 671                 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
 672                  * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
 673                  */
 674                 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
 675                     (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
 676                        (scfgr & SCFGR_VIRT_EN)))
 677                                 ctrlpriv->virt_en = 1;
 678         } else {
 679                 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
 680                 if (comp_params & CTPR_MS_VIRT_EN_POR)
 681                                 ctrlpriv->virt_en = 1;
 682         }
 683
 684         if (ctrlpriv->virt_en == 1)
 685                 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
 686                               JRSTART_JR1_START | JRSTART_JR2_START |
 687                               JRSTART_JR3_START);
 688
 689         if (sizeof(dma_addr_t) == sizeof(u64)) {
 690                 if (caam_dpaa2)
 691                         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(49));
 692                 else if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
 693                         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
 694                 else
 695                         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
 696         } else {
 697                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
 698         }
 699         if (ret) {
 700                 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
 701                 goto iounmap_ctrl;
 702         }
 703
 704         ctrlpriv->era = caam_get_era(ctrl);
 705
 706         ret = of_platform_populate(nprop, caam_match, NULL, dev);
 707         if (ret) {
 708                 dev_err(dev, "JR platform devices creation error\n");
 709                 goto iounmap_ctrl;
 710         }
 711
 712 #ifdef CONFIG_DEBUG_FS
 713         /*
 714          * FIXME: needs better naming distinction, as some amalgamation of
 715          * "caam" and nprop->full_name. The OF name isn't distinctive,
 716          * but does separate instances
 717          */
 718         perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
 719
 720         ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL);
 721         ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
 722 #endif
 723
 724         ring = 0;
 725         for_each_available_child_of_node(nprop, np)
 726                 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
 727                     of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
 728                         ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
 729                                              ((__force uint8_t *)ctrl +
 730                                              (ring + JR_BLOCK_NUMBER) *
 731                                               BLOCK_OFFSET
 732                                              );
 733                         ctrlpriv->total_jobrs++;
 734                         ring++;
 735                 }
 736
 737         /* Check to see if (DPAA 1.x) QI present. If so, enable */
 738         ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
 739         if (ctrlpriv->qi_present && !caam_dpaa2) {
 740                 ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
 741                                ((__force uint8_t *)ctrl +
 742                                  BLOCK_OFFSET * QI_BLOCK_NUMBER
 743                                );
 744                 /* This is all that's required to physically enable QI */
 745                 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
 746
 747                 /* If QMAN driver is present, init CAAM-QI backend */
 748 #ifdef CONFIG_CAAM_QI
 749                 ret = caam_qi_init(pdev);
 750                 if (ret)
 751                         dev_err(dev, "caam qi i/f init failed: %d\n", ret);
 752 #endif
 753         }
 754
 755         /* If no QI and no rings specified, quit and go home */
 756         if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
 757                 dev_err(dev, "no queues configured, terminating\n");
 758                 ret = -ENOMEM;
 759                 goto caam_remove;
 760         }
 761
 762         if (ctrlpriv->era < 10)
 763                 rng_vid = (rd_reg32(&ctrl->perfmon.cha_id_ls) &
 764                            CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
 765         else
 766                 rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >>
 767                            CHA_VER_VID_SHIFT;
 768
 769         /*
 770          * If SEC has RNG version >= 4 and RNG state handle has not been
 771          * already instantiated, do RNG instantiation
 772          * In case of SoCs with Management Complex, RNG is managed by MC f/w.
 773          */
 774         if (!ctrlpriv->mc_en && rng_vid >= 4) {
 775                 ctrlpriv->rng4_sh_init =
 776                         rd_reg32(&ctrl->r4tst[0].rdsta);
 777                 /*
 778                  * If the secure keys (TDKEK, JDKEK, TDSK), were already
 779                  * generated, signal this to the function that is instantiating
 780                  * the state handles. An error would occur if RNG4 attempts
 781                  * to regenerate these keys before the next POR.
 782                  */
 783                 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
 784                 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
 785                 do {
 786                         int inst_handles =
 787                                 rd_reg32(&ctrl->r4tst[0].rdsta) &
 788                                                                 RDSTA_IFMASK;
 789                         /*
 790                          * If either SH were instantiated by somebody else
 791                          * (e.g. u-boot) then it is assumed that the entropy
 792                          * parameters are properly set and thus the function
 793                          * setting these (kick_trng(...)) is skipped.
 794                          * Also, if a handle was instantiated, do not change
 795                          * the TRNG parameters.
 796                          */
 797                         if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
 798                                 dev_info(dev,
 799                                          "Entropy delay = %u\n",
 800                                          ent_delay);
 801                                 kick_trng(pdev, ent_delay);
 802                                 ent_delay += 400;
 803                         }
 804                         /*
 805                          * if instantiate_rng(...) fails, the loop will rerun
 806                          * and the kick_trng(...) function will modfiy the
 807                          * upper and lower limits of the entropy sampling
 808                          * interval, leading to a sucessful initialization of
 809                          * the RNG.
 810                          */
 811                         ret = instantiate_rng(dev, inst_handles,
 812                                               gen_sk);
 813                         if (ret == -EAGAIN)
 814                                 /*
 815                                  * if here, the loop will rerun,
 816                                  * so don't hog the CPU
 817                                  */
 818                                 cpu_relax();
 819                 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
 820                 if (ret) {
 821                         dev_err(dev, "failed to instantiate RNG");
 822                         goto caam_remove;
 823                 }
 824                 /*
 825                  * Set handles init'ed by this module as the complement of the
 826                  * already initialized ones
 827                  */
 828                 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
 829
 830                 /* Enable RDB bit so that RNG works faster */
 831                 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
 832         }
 833
 834         /* NOTE: RTIC detection ought to go here, around Si time */
 835
 836         caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
 837                   (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
 838
 839         /* Report "alive" for developer to see */
 840         dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
 841                  ctrlpriv->era);
 842         dev_info(dev, "job rings = %d, qi = %d\n",
 843                  ctrlpriv->total_jobrs, ctrlpriv->qi_present);
 844
 845 #ifdef CONFIG_DEBUG_FS
 846         debugfs_create_file("rq_dequeued", S_IRUSR | S_IRGRP | S_IROTH,
 847                             ctrlpriv->ctl, &perfmon->req_dequeued,
 848                             &caam_fops_u64_ro);
 849         debugfs_create_file("ob_rq_encrypted", S_IRUSR | S_IRGRP | S_IROTH,
 850                             ctrlpriv->ctl, &perfmon->ob_enc_req,
 851                             &caam_fops_u64_ro);
 852         debugfs_create_file("ib_rq_decrypted", S_IRUSR | S_IRGRP | S_IROTH,
 853                             ctrlpriv->ctl, &perfmon->ib_dec_req,
 854                             &caam_fops_u64_ro);
 855         debugfs_create_file("ob_bytes_encrypted", S_IRUSR | S_IRGRP | S_IROTH,
 856                             ctrlpriv->ctl, &perfmon->ob_enc_bytes,
 857                             &caam_fops_u64_ro);
 858         debugfs_create_file("ob_bytes_protected", S_IRUSR | S_IRGRP | S_IROTH,
 859                             ctrlpriv->ctl, &perfmon->ob_prot_bytes,
 860                             &caam_fops_u64_ro);
 861         debugfs_create_file("ib_bytes_decrypted", S_IRUSR | S_IRGRP | S_IROTH,
 862                             ctrlpriv->ctl, &perfmon->ib_dec_bytes,
 863                             &caam_fops_u64_ro);
 864         debugfs_create_file("ib_bytes_validated", S_IRUSR | S_IRGRP | S_IROTH,
 865                             ctrlpriv->ctl, &perfmon->ib_valid_bytes,
 866                             &caam_fops_u64_ro);
 867
 868         /* Controller level - global status values */
 869         debugfs_create_file("fault_addr", S_IRUSR | S_IRGRP | S_IROTH,
 870                             ctrlpriv->ctl, &perfmon->faultaddr,
 871                             &caam_fops_u32_ro);
 872         debugfs_create_file("fault_detail", S_IRUSR | S_IRGRP | S_IROTH,
 873                             ctrlpriv->ctl, &perfmon->faultdetail,
 874                             &caam_fops_u32_ro);
 875         debugfs_create_file("fault_status", S_IRUSR | S_IRGRP | S_IROTH,
 876                             ctrlpriv->ctl, &perfmon->status,
 877                             &caam_fops_u32_ro);
 878
 879         /* Internal covering keys (useful in non-secure mode only) */
 880         ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0];
 881         ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 882         debugfs_create_blob("kek", S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl,
 883                             &ctrlpriv->ctl_kek_wrap);
 884
 885         ctrlpriv->ctl_tkek_wrap.data = (__force void *)&ctrlpriv->ctrl->tkek[0];
 886         ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 887         debugfs_create_blob("tkek", S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl,
 888                             &ctrlpriv->ctl_tkek_wrap);
 889
 890         ctrlpriv->ctl_tdsk_wrap.data = (__force void *)&ctrlpriv->ctrl->tdsk[0];
 891         ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 892         debugfs_create_blob("tdsk", S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl,
 893                             &ctrlpriv->ctl_tdsk_wrap);
 894 #endif
 895         return 0;
 896
 897 caam_remove:
 898         caam_remove(pdev);
 899         return ret;
 900
 901 iounmap_ctrl:
 902         iounmap(ctrl);
 903 disable_caam_emi_slow:
 904         if (ctrlpriv->caam_emi_slow)
 905                 clk_disable_unprepare(ctrlpriv->caam_emi_slow);
 906 disable_caam_aclk:
 907         clk_disable_unprepare(ctrlpriv->caam_aclk);
 908 disable_caam_mem:
 909         if (ctrlpriv->caam_mem)
 910                 clk_disable_unprepare(ctrlpriv->caam_mem);
 911 disable_caam_ipg:
 912         clk_disable_unprepare(ctrlpriv->caam_ipg);
 913         return ret;
 914 }
 915
 916 static struct platform_driver caam_driver = {
 917         .driver = {
 918                 .name = "caam",
 919                 .of_match_table = caam_match,
 920         },
 921         .probe       = caam_probe,
 922         .remove      = caam_remove,
 923 };
 924
 925 module_platform_driver(caam_driver);
 926
 927 MODULE_LICENSE("GPL");
 928 MODULE_DESCRIPTION("FSL CAAM request backend");
 929 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");