1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2021 Aspeed Technology Inc.
7 #include <linux/module.h>
8 #include <linux/of_address.h>
9 #include <linux/of_device.h>
10 #include <linux/of_irq.h>
12 #include <linux/platform_device.h>
14 #include "aspeed-hace.h"
16 #ifdef CONFIG_CRYPTO_DEV_ASPEED_DEBUG
17 #define HACE_DBG(d, fmt, ...) \
18 dev_info((d)->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
20 #define HACE_DBG(d, fmt, ...) \
21 dev_dbg((d)->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
24 /* HACE interrupt service routine */
25 static irqreturn_t aspeed_hace_irq(int irq, void *dev)
27 struct aspeed_hace_dev *hace_dev = (struct aspeed_hace_dev *)dev;
28 struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
29 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine;
32 sts = ast_hace_read(hace_dev, ASPEED_HACE_STS);
33 ast_hace_write(hace_dev, sts, ASPEED_HACE_STS);
35 HACE_DBG(hace_dev, "irq status: 0x%x\n", sts);
37 if (sts & HACE_HASH_ISR) {
38 if (hash_engine->flags & CRYPTO_FLAGS_BUSY)
39 tasklet_schedule(&hash_engine->done_task);
41 dev_warn(hace_dev->dev, "HASH no active requests.\n");
44 if (sts & HACE_CRYPTO_ISR) {
45 if (crypto_engine->flags & CRYPTO_FLAGS_BUSY)
46 tasklet_schedule(&crypto_engine->done_task);
48 dev_warn(hace_dev->dev, "CRYPTO no active requests.\n");
54 static void aspeed_hace_crypto_done_task(unsigned long data)
56 struct aspeed_hace_dev *hace_dev = (struct aspeed_hace_dev *)data;
57 struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
59 crypto_engine->resume(hace_dev);
62 static void aspeed_hace_hash_done_task(unsigned long data)
64 struct aspeed_hace_dev *hace_dev = (struct aspeed_hace_dev *)data;
65 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine;
67 hash_engine->resume(hace_dev);
70 static void aspeed_hace_register(struct aspeed_hace_dev *hace_dev)
72 #ifdef CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH
73 aspeed_register_hace_hash_algs(hace_dev);
75 #ifdef CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO
76 aspeed_register_hace_crypto_algs(hace_dev);
80 static void aspeed_hace_unregister(struct aspeed_hace_dev *hace_dev)
82 #ifdef CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH
83 aspeed_unregister_hace_hash_algs(hace_dev);
85 #ifdef CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO
86 aspeed_unregister_hace_crypto_algs(hace_dev);
90 static const struct of_device_id aspeed_hace_of_matches[] = {
91 { .compatible = "aspeed,ast2500-hace", .data = (void *)5, },
92 { .compatible = "aspeed,ast2600-hace", .data = (void *)6, },
96 static int aspeed_hace_probe(struct platform_device *pdev)
98 struct aspeed_engine_crypto *crypto_engine;
99 const struct of_device_id *hace_dev_id;
100 struct aspeed_engine_hash *hash_engine;
101 struct aspeed_hace_dev *hace_dev;
102 struct resource *res;
105 hace_dev = devm_kzalloc(&pdev->dev, sizeof(struct aspeed_hace_dev),
110 hace_dev_id = of_match_device(aspeed_hace_of_matches, &pdev->dev);
112 dev_err(&pdev->dev, "Failed to match hace dev id\n");
116 hace_dev->dev = &pdev->dev;
117 hace_dev->version = (unsigned long)hace_dev_id->data;
118 hash_engine = &hace_dev->hash_engine;
119 crypto_engine = &hace_dev->crypto_engine;
121 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
123 platform_set_drvdata(pdev, hace_dev);
125 hace_dev->regs = devm_ioremap_resource(&pdev->dev, res);
126 if (IS_ERR(hace_dev->regs)) {
127 dev_err(&pdev->dev, "Failed to map resources\n");
128 return PTR_ERR(hace_dev->regs);
131 /* Get irq number and register it */
132 hace_dev->irq = platform_get_irq(pdev, 0);
133 if (hace_dev->irq < 0)
136 rc = devm_request_irq(&pdev->dev, hace_dev->irq, aspeed_hace_irq, 0,
137 dev_name(&pdev->dev), hace_dev);
139 dev_err(&pdev->dev, "Failed to request interrupt\n");
143 /* Get clk and enable it */
144 hace_dev->clk = devm_clk_get(&pdev->dev, NULL);
145 if (IS_ERR(hace_dev->clk)) {
146 dev_err(&pdev->dev, "Failed to get clk\n");
150 rc = clk_prepare_enable(hace_dev->clk);
152 dev_err(&pdev->dev, "Failed to enable clock 0x%x\n", rc);
156 /* Initialize crypto hardware engine structure for hash */
157 hace_dev->crypt_engine_hash = crypto_engine_alloc_init(hace_dev->dev,
159 if (!hace_dev->crypt_engine_hash) {
164 rc = crypto_engine_start(hace_dev->crypt_engine_hash);
166 goto err_engine_hash_start;
168 tasklet_init(&hash_engine->done_task, aspeed_hace_hash_done_task,
169 (unsigned long)hace_dev);
171 /* Initialize crypto hardware engine structure for crypto */
172 hace_dev->crypt_engine_crypto = crypto_engine_alloc_init(hace_dev->dev,
174 if (!hace_dev->crypt_engine_crypto) {
176 goto err_engine_hash_start;
179 rc = crypto_engine_start(hace_dev->crypt_engine_crypto);
181 goto err_engine_crypto_start;
183 tasklet_init(&crypto_engine->done_task, aspeed_hace_crypto_done_task,
184 (unsigned long)hace_dev);
186 /* Allocate DMA buffer for hash engine input used */
187 hash_engine->ahash_src_addr =
188 dmam_alloc_coherent(&pdev->dev,
189 ASPEED_HASH_SRC_DMA_BUF_LEN,
190 &hash_engine->ahash_src_dma_addr,
192 if (!hash_engine->ahash_src_addr) {
193 dev_err(&pdev->dev, "Failed to allocate dma buffer\n");
195 goto err_engine_crypto_start;
198 /* Allocate DMA buffer for crypto engine context used */
199 crypto_engine->cipher_ctx =
200 dmam_alloc_coherent(&pdev->dev,
202 &crypto_engine->cipher_ctx_dma,
204 if (!crypto_engine->cipher_ctx) {
205 dev_err(&pdev->dev, "Failed to allocate cipher ctx dma\n");
207 goto err_engine_crypto_start;
210 /* Allocate DMA buffer for crypto engine input used */
211 crypto_engine->cipher_addr =
212 dmam_alloc_coherent(&pdev->dev,
213 ASPEED_CRYPTO_SRC_DMA_BUF_LEN,
214 &crypto_engine->cipher_dma_addr,
216 if (!crypto_engine->cipher_addr) {
217 dev_err(&pdev->dev, "Failed to allocate cipher addr dma\n");
219 goto err_engine_crypto_start;
222 /* Allocate DMA buffer for crypto engine output used */
223 if (hace_dev->version == AST2600_VERSION) {
224 crypto_engine->dst_sg_addr =
225 dmam_alloc_coherent(&pdev->dev,
226 ASPEED_CRYPTO_DST_DMA_BUF_LEN,
227 &crypto_engine->dst_sg_dma_addr,
229 if (!crypto_engine->dst_sg_addr) {
230 dev_err(&pdev->dev, "Failed to allocate dst_sg dma\n");
232 goto err_engine_crypto_start;
236 aspeed_hace_register(hace_dev);
238 dev_info(&pdev->dev, "Aspeed Crypto Accelerator successfully registered\n");
242 err_engine_crypto_start:
243 crypto_engine_exit(hace_dev->crypt_engine_crypto);
244 err_engine_hash_start:
245 crypto_engine_exit(hace_dev->crypt_engine_hash);
247 clk_disable_unprepare(hace_dev->clk);
252 static int aspeed_hace_remove(struct platform_device *pdev)
254 struct aspeed_hace_dev *hace_dev = platform_get_drvdata(pdev);
255 struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
256 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine;
258 aspeed_hace_unregister(hace_dev);
260 crypto_engine_exit(hace_dev->crypt_engine_hash);
261 crypto_engine_exit(hace_dev->crypt_engine_crypto);
263 tasklet_kill(&hash_engine->done_task);
264 tasklet_kill(&crypto_engine->done_task);
266 clk_disable_unprepare(hace_dev->clk);
271 MODULE_DEVICE_TABLE(of, aspeed_hace_of_matches);
273 static struct platform_driver aspeed_hace_driver = {
274 .probe = aspeed_hace_probe,
275 .remove = aspeed_hace_remove,
277 .name = KBUILD_MODNAME,
278 .of_match_table = aspeed_hace_of_matches,
282 module_platform_driver(aspeed_hace_driver);
284 MODULE_AUTHOR("Neal Liu <neal_liu@aspeedtech.com>");
285 MODULE_DESCRIPTION("Aspeed HACE driver Crypto Accelerator");
286 MODULE_LICENSE("GPL");