2 * AMCC SoC PPC4xx Crypto Driver
4 * Copyright (c) 2008 Applied Micro Circuits Corporation.
5 * All rights reserved. James Hsiao <jhsiao@amcc.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * This file implements AMCC crypto offload Linux device driver for use with
21 #include <linux/kernel.h>
22 #include <linux/interrupt.h>
23 #include <linux/spinlock_types.h>
24 #include <linux/random.h>
25 #include <linux/scatterlist.h>
26 #include <linux/crypto.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_platform.h>
34 #include <linux/slab.h>
36 #include <asm/dcr-regs.h>
37 #include <asm/cacheflush.h>
38 #include <crypto/aead.h>
39 #include <crypto/aes.h>
40 #include <crypto/ctr.h>
41 #include <crypto/gcm.h>
42 #include <crypto/sha.h>
43 #include <crypto/rng.h>
44 #include <crypto/scatterwalk.h>
45 #include <crypto/skcipher.h>
46 #include <crypto/internal/aead.h>
47 #include <crypto/internal/rng.h>
48 #include <crypto/internal/skcipher.h>
49 #include "crypto4xx_reg_def.h"
50 #include "crypto4xx_core.h"
51 #include "crypto4xx_sa.h"
52 #include "crypto4xx_trng.h"
54 #define PPC4XX_SEC_VERSION_STR "0.5"
57 * PPC4xx Crypto Engine Initialization Routine
59 static void crypto4xx_hw_init(struct crypto4xx_device *dev)
61 union ce_ring_size ring_size;
62 union ce_ring_control ring_ctrl;
63 union ce_part_ring_size part_ring_size;
64 union ce_io_threshold io_threshold;
66 union ce_pe_dma_cfg pe_dma_cfg;
69 writel(PPC4XX_BYTE_ORDER, dev->ce_base + CRYPTO4XX_BYTE_ORDER_CFG);
70 /* setup pe dma, include reset sg, pdr and pe, then release reset */
72 pe_dma_cfg.bf.bo_sgpd_en = 1;
73 pe_dma_cfg.bf.bo_data_en = 0;
74 pe_dma_cfg.bf.bo_sa_en = 1;
75 pe_dma_cfg.bf.bo_pd_en = 1;
76 pe_dma_cfg.bf.dynamic_sa_en = 1;
77 pe_dma_cfg.bf.reset_sg = 1;
78 pe_dma_cfg.bf.reset_pdr = 1;
79 pe_dma_cfg.bf.reset_pe = 1;
80 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
81 /* un reset pe,sg and pdr */
82 pe_dma_cfg.bf.pe_mode = 0;
83 pe_dma_cfg.bf.reset_sg = 0;
84 pe_dma_cfg.bf.reset_pdr = 0;
85 pe_dma_cfg.bf.reset_pe = 0;
86 pe_dma_cfg.bf.bo_td_en = 0;
87 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
88 writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_PDR_BASE);
89 writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_RDR_BASE);
90 writel(PPC4XX_PRNG_CTRL_AUTO_EN, dev->ce_base + CRYPTO4XX_PRNG_CTRL);
91 get_random_bytes(&rand_num, sizeof(rand_num));
92 writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_L);
93 get_random_bytes(&rand_num, sizeof(rand_num));
94 writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_H);
96 ring_size.bf.ring_offset = PPC4XX_PD_SIZE;
97 ring_size.bf.ring_size = PPC4XX_NUM_PD;
98 writel(ring_size.w, dev->ce_base + CRYPTO4XX_RING_SIZE);
100 writel(ring_ctrl.w, dev->ce_base + CRYPTO4XX_RING_CTRL);
101 device_ctrl = readl(dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
102 device_ctrl |= PPC4XX_DC_3DES_EN;
103 writel(device_ctrl, dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
104 writel(dev->gdr_pa, dev->ce_base + CRYPTO4XX_GATH_RING_BASE);
105 writel(dev->sdr_pa, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE);
106 part_ring_size.w = 0;
107 part_ring_size.bf.sdr_size = PPC4XX_SDR_SIZE;
108 part_ring_size.bf.gdr_size = PPC4XX_GDR_SIZE;
109 writel(part_ring_size.w, dev->ce_base + CRYPTO4XX_PART_RING_SIZE);
110 writel(PPC4XX_SD_BUFFER_SIZE, dev->ce_base + CRYPTO4XX_PART_RING_CFG);
112 io_threshold.bf.output_threshold = PPC4XX_OUTPUT_THRESHOLD;
113 io_threshold.bf.input_threshold = PPC4XX_INPUT_THRESHOLD;
114 writel(io_threshold.w, dev->ce_base + CRYPTO4XX_IO_THRESHOLD);
115 writel(0, dev->ce_base + CRYPTO4XX_PDR_BASE_UADDR);
116 writel(0, dev->ce_base + CRYPTO4XX_RDR_BASE_UADDR);
117 writel(0, dev->ce_base + CRYPTO4XX_PKT_SRC_UADDR);
118 writel(0, dev->ce_base + CRYPTO4XX_PKT_DEST_UADDR);
119 writel(0, dev->ce_base + CRYPTO4XX_SA_UADDR);
120 writel(0, dev->ce_base + CRYPTO4XX_GATH_RING_BASE_UADDR);
121 writel(0, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE_UADDR);
122 /* un reset pe,sg and pdr */
123 pe_dma_cfg.bf.pe_mode = 1;
124 pe_dma_cfg.bf.reset_sg = 0;
125 pe_dma_cfg.bf.reset_pdr = 0;
126 pe_dma_cfg.bf.reset_pe = 0;
127 pe_dma_cfg.bf.bo_td_en = 0;
128 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
129 /*clear all pending interrupt*/
130 writel(PPC4XX_INTERRUPT_CLR, dev->ce_base + CRYPTO4XX_INT_CLR);
131 writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
132 writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
133 writel(PPC4XX_INT_CFG, dev->ce_base + CRYPTO4XX_INT_CFG);
135 writel(PPC4XX_INT_TIMEOUT_CNT_REVB << 10,
136 dev->ce_base + CRYPTO4XX_INT_TIMEOUT_CNT);
137 writel(PPC4XX_PD_DONE_INT | PPC4XX_TMO_ERR_INT,
138 dev->ce_base + CRYPTO4XX_INT_EN);
140 writel(PPC4XX_PD_DONE_INT, dev->ce_base + CRYPTO4XX_INT_EN);
144 int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size)
146 ctx->sa_in = kcalloc(size, 4, GFP_ATOMIC);
147 if (ctx->sa_in == NULL)
150 ctx->sa_out = kcalloc(size, 4, GFP_ATOMIC);
151 if (ctx->sa_out == NULL) {
162 void crypto4xx_free_sa(struct crypto4xx_ctx *ctx)
172 * alloc memory for the gather ring
173 * no need to alloc buf for the ring
174 * gdr_tail, gdr_head and gdr_count are initialized by this function
176 static u32 crypto4xx_build_pdr(struct crypto4xx_device *dev)
179 dev->pdr = dma_alloc_coherent(dev->core_dev->device,
180 sizeof(struct ce_pd) * PPC4XX_NUM_PD,
181 &dev->pdr_pa, GFP_ATOMIC);
185 dev->pdr_uinfo = kcalloc(PPC4XX_NUM_PD, sizeof(struct pd_uinfo),
187 if (!dev->pdr_uinfo) {
188 dma_free_coherent(dev->core_dev->device,
189 sizeof(struct ce_pd) * PPC4XX_NUM_PD,
194 memset(dev->pdr, 0, sizeof(struct ce_pd) * PPC4XX_NUM_PD);
195 dev->shadow_sa_pool = dma_alloc_coherent(dev->core_dev->device,
196 sizeof(union shadow_sa_buf) * PPC4XX_NUM_PD,
197 &dev->shadow_sa_pool_pa,
199 if (!dev->shadow_sa_pool)
202 dev->shadow_sr_pool = dma_alloc_coherent(dev->core_dev->device,
203 sizeof(struct sa_state_record) * PPC4XX_NUM_PD,
204 &dev->shadow_sr_pool_pa, GFP_ATOMIC);
205 if (!dev->shadow_sr_pool)
207 for (i = 0; i < PPC4XX_NUM_PD; i++) {
208 struct ce_pd *pd = &dev->pdr[i];
209 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[i];
211 pd->sa = dev->shadow_sa_pool_pa +
212 sizeof(union shadow_sa_buf) * i;
214 /* alloc 256 bytes which is enough for any kind of dynamic sa */
215 pd_uinfo->sa_va = &dev->shadow_sa_pool[i].sa;
217 /* alloc state record */
218 pd_uinfo->sr_va = &dev->shadow_sr_pool[i];
219 pd_uinfo->sr_pa = dev->shadow_sr_pool_pa +
220 sizeof(struct sa_state_record) * i;
226 static void crypto4xx_destroy_pdr(struct crypto4xx_device *dev)
229 dma_free_coherent(dev->core_dev->device,
230 sizeof(struct ce_pd) * PPC4XX_NUM_PD,
231 dev->pdr, dev->pdr_pa);
233 if (dev->shadow_sa_pool)
234 dma_free_coherent(dev->core_dev->device,
235 sizeof(union shadow_sa_buf) * PPC4XX_NUM_PD,
236 dev->shadow_sa_pool, dev->shadow_sa_pool_pa);
238 if (dev->shadow_sr_pool)
239 dma_free_coherent(dev->core_dev->device,
240 sizeof(struct sa_state_record) * PPC4XX_NUM_PD,
241 dev->shadow_sr_pool, dev->shadow_sr_pool_pa);
243 kfree(dev->pdr_uinfo);
246 static u32 crypto4xx_get_pd_from_pdr_nolock(struct crypto4xx_device *dev)
251 retval = dev->pdr_head;
252 tmp = (dev->pdr_head + 1) % PPC4XX_NUM_PD;
254 if (tmp == dev->pdr_tail)
255 return ERING_WAS_FULL;
262 static u32 crypto4xx_put_pd_to_pdr(struct crypto4xx_device *dev, u32 idx)
264 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[idx];
268 spin_lock_irqsave(&dev->core_dev->lock, flags);
269 pd_uinfo->state = PD_ENTRY_FREE;
271 if (dev->pdr_tail != PPC4XX_LAST_PD)
275 tail = dev->pdr_tail;
276 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
282 * alloc memory for the gather ring
283 * no need to alloc buf for the ring
284 * gdr_tail, gdr_head and gdr_count are initialized by this function
286 static u32 crypto4xx_build_gdr(struct crypto4xx_device *dev)
288 dev->gdr = dma_alloc_coherent(dev->core_dev->device,
289 sizeof(struct ce_gd) * PPC4XX_NUM_GD,
290 &dev->gdr_pa, GFP_ATOMIC);
297 static inline void crypto4xx_destroy_gdr(struct crypto4xx_device *dev)
299 dma_free_coherent(dev->core_dev->device,
300 sizeof(struct ce_gd) * PPC4XX_NUM_GD,
301 dev->gdr, dev->gdr_pa);
305 * when this function is called.
306 * preemption or interrupt must be disabled
308 static u32 crypto4xx_get_n_gd(struct crypto4xx_device *dev, int n)
313 if (n >= PPC4XX_NUM_GD)
314 return ERING_WAS_FULL;
316 retval = dev->gdr_head;
317 tmp = (dev->gdr_head + n) % PPC4XX_NUM_GD;
318 if (dev->gdr_head > dev->gdr_tail) {
319 if (tmp < dev->gdr_head && tmp >= dev->gdr_tail)
320 return ERING_WAS_FULL;
321 } else if (dev->gdr_head < dev->gdr_tail) {
322 if (tmp < dev->gdr_head || tmp >= dev->gdr_tail)
323 return ERING_WAS_FULL;
330 static u32 crypto4xx_put_gd_to_gdr(struct crypto4xx_device *dev)
334 spin_lock_irqsave(&dev->core_dev->lock, flags);
335 if (dev->gdr_tail == dev->gdr_head) {
336 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
340 if (dev->gdr_tail != PPC4XX_LAST_GD)
345 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
350 static inline struct ce_gd *crypto4xx_get_gdp(struct crypto4xx_device *dev,
351 dma_addr_t *gd_dma, u32 idx)
353 *gd_dma = dev->gdr_pa + sizeof(struct ce_gd) * idx;
355 return &dev->gdr[idx];
359 * alloc memory for the scatter ring
360 * need to alloc buf for the ring
361 * sdr_tail, sdr_head and sdr_count are initialized by this function
363 static u32 crypto4xx_build_sdr(struct crypto4xx_device *dev)
367 /* alloc memory for scatter descriptor ring */
368 dev->sdr = dma_alloc_coherent(dev->core_dev->device,
369 sizeof(struct ce_sd) * PPC4XX_NUM_SD,
370 &dev->sdr_pa, GFP_ATOMIC);
374 dev->scatter_buffer_va =
375 dma_alloc_coherent(dev->core_dev->device,
376 PPC4XX_SD_BUFFER_SIZE * PPC4XX_NUM_SD,
377 &dev->scatter_buffer_pa, GFP_ATOMIC);
378 if (!dev->scatter_buffer_va) {
379 dma_free_coherent(dev->core_dev->device,
380 sizeof(struct ce_sd) * PPC4XX_NUM_SD,
381 dev->sdr, dev->sdr_pa);
385 for (i = 0; i < PPC4XX_NUM_SD; i++) {
386 dev->sdr[i].ptr = dev->scatter_buffer_pa +
387 PPC4XX_SD_BUFFER_SIZE * i;
393 static void crypto4xx_destroy_sdr(struct crypto4xx_device *dev)
396 dma_free_coherent(dev->core_dev->device,
397 sizeof(struct ce_sd) * PPC4XX_NUM_SD,
398 dev->sdr, dev->sdr_pa);
400 if (dev->scatter_buffer_va)
401 dma_free_coherent(dev->core_dev->device,
402 PPC4XX_SD_BUFFER_SIZE * PPC4XX_NUM_SD,
403 dev->scatter_buffer_va,
404 dev->scatter_buffer_pa);
408 * when this function is called.
409 * preemption or interrupt must be disabled
411 static u32 crypto4xx_get_n_sd(struct crypto4xx_device *dev, int n)
416 if (n >= PPC4XX_NUM_SD)
417 return ERING_WAS_FULL;
419 retval = dev->sdr_head;
420 tmp = (dev->sdr_head + n) % PPC4XX_NUM_SD;
421 if (dev->sdr_head > dev->gdr_tail) {
422 if (tmp < dev->sdr_head && tmp >= dev->sdr_tail)
423 return ERING_WAS_FULL;
424 } else if (dev->sdr_head < dev->sdr_tail) {
425 if (tmp < dev->sdr_head || tmp >= dev->sdr_tail)
426 return ERING_WAS_FULL;
427 } /* the head = tail, or empty case is already take cared */
433 static u32 crypto4xx_put_sd_to_sdr(struct crypto4xx_device *dev)
437 spin_lock_irqsave(&dev->core_dev->lock, flags);
438 if (dev->sdr_tail == dev->sdr_head) {
439 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
442 if (dev->sdr_tail != PPC4XX_LAST_SD)
446 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
451 static inline struct ce_sd *crypto4xx_get_sdp(struct crypto4xx_device *dev,
452 dma_addr_t *sd_dma, u32 idx)
454 *sd_dma = dev->sdr_pa + sizeof(struct ce_sd) * idx;
456 return &dev->sdr[idx];
459 static void crypto4xx_copy_pkt_to_dst(struct crypto4xx_device *dev,
461 struct pd_uinfo *pd_uinfo,
463 struct scatterlist *dst)
465 unsigned int first_sd = pd_uinfo->first_sd;
466 unsigned int last_sd;
467 unsigned int overflow = 0;
468 unsigned int to_copy;
469 unsigned int dst_start = 0;
472 * Because the scatter buffers are all neatly organized in one
473 * big continuous ringbuffer; scatterwalk_map_and_copy() can
474 * be instructed to copy a range of buffers in one go.
477 last_sd = (first_sd + pd_uinfo->num_sd);
478 if (last_sd > PPC4XX_LAST_SD) {
479 last_sd = PPC4XX_LAST_SD;
480 overflow = last_sd % PPC4XX_NUM_SD;
484 void *buf = dev->scatter_buffer_va +
485 first_sd * PPC4XX_SD_BUFFER_SIZE;
487 to_copy = min(nbytes, PPC4XX_SD_BUFFER_SIZE *
488 (1 + last_sd - first_sd));
489 scatterwalk_map_and_copy(buf, dst, dst_start, to_copy, 1);
495 dst_start += to_copy;
501 static void crypto4xx_copy_digest_to_dst(void *dst,
502 struct pd_uinfo *pd_uinfo,
503 struct crypto4xx_ctx *ctx)
505 struct dynamic_sa_ctl *sa = (struct dynamic_sa_ctl *) ctx->sa_in;
507 if (sa->sa_command_0.bf.hash_alg == SA_HASH_ALG_SHA1) {
508 memcpy(dst, pd_uinfo->sr_va->save_digest,
509 SA_HASH_ALG_SHA1_DIGEST_SIZE);
513 static void crypto4xx_ret_sg_desc(struct crypto4xx_device *dev,
514 struct pd_uinfo *pd_uinfo)
517 if (pd_uinfo->num_gd) {
518 for (i = 0; i < pd_uinfo->num_gd; i++)
519 crypto4xx_put_gd_to_gdr(dev);
520 pd_uinfo->first_gd = 0xffffffff;
521 pd_uinfo->num_gd = 0;
523 if (pd_uinfo->num_sd) {
524 for (i = 0; i < pd_uinfo->num_sd; i++)
525 crypto4xx_put_sd_to_sdr(dev);
527 pd_uinfo->first_sd = 0xffffffff;
528 pd_uinfo->num_sd = 0;
532 static void crypto4xx_cipher_done(struct crypto4xx_device *dev,
533 struct pd_uinfo *pd_uinfo,
536 struct skcipher_request *req;
537 struct scatterlist *dst;
540 req = skcipher_request_cast(pd_uinfo->async_req);
542 if (pd_uinfo->sa_va->sa_command_0.bf.scatter) {
543 crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo,
544 req->cryptlen, req->dst);
546 dst = pd_uinfo->dest_va;
547 addr = dma_map_page(dev->core_dev->device, sg_page(dst),
548 dst->offset, dst->length, DMA_FROM_DEVICE);
551 if (pd_uinfo->sa_va->sa_command_0.bf.save_iv == SA_SAVE_IV) {
552 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
554 crypto4xx_memcpy_from_le32((u32 *)req->iv,
555 pd_uinfo->sr_va->save_iv,
556 crypto_skcipher_ivsize(skcipher));
559 crypto4xx_ret_sg_desc(dev, pd_uinfo);
561 if (pd_uinfo->state & PD_ENTRY_BUSY)
562 skcipher_request_complete(req, -EINPROGRESS);
563 skcipher_request_complete(req, 0);
566 static void crypto4xx_ahash_done(struct crypto4xx_device *dev,
567 struct pd_uinfo *pd_uinfo)
569 struct crypto4xx_ctx *ctx;
570 struct ahash_request *ahash_req;
572 ahash_req = ahash_request_cast(pd_uinfo->async_req);
573 ctx = crypto_tfm_ctx(ahash_req->base.tfm);
575 crypto4xx_copy_digest_to_dst(ahash_req->result, pd_uinfo,
576 crypto_tfm_ctx(ahash_req->base.tfm));
577 crypto4xx_ret_sg_desc(dev, pd_uinfo);
579 if (pd_uinfo->state & PD_ENTRY_BUSY)
580 ahash_request_complete(ahash_req, -EINPROGRESS);
581 ahash_request_complete(ahash_req, 0);
584 static void crypto4xx_aead_done(struct crypto4xx_device *dev,
585 struct pd_uinfo *pd_uinfo,
588 struct aead_request *aead_req = container_of(pd_uinfo->async_req,
589 struct aead_request, base);
590 struct scatterlist *dst = pd_uinfo->dest_va;
591 size_t cp_len = crypto_aead_authsize(
592 crypto_aead_reqtfm(aead_req));
593 u32 icv[AES_BLOCK_SIZE];
596 if (pd_uinfo->sa_va->sa_command_0.bf.scatter) {
597 crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo,
598 pd->pd_ctl_len.bf.pkt_len,
601 dma_unmap_page(dev->core_dev->device, pd->dest, dst->length,
605 if (pd_uinfo->sa_va->sa_command_0.bf.dir == DIR_OUTBOUND) {
606 /* append icv at the end */
607 crypto4xx_memcpy_from_le32(icv, pd_uinfo->sr_va->save_digest,
610 scatterwalk_map_and_copy(icv, dst, aead_req->cryptlen,
613 /* check icv at the end */
614 scatterwalk_map_and_copy(icv, aead_req->src,
615 aead_req->assoclen + aead_req->cryptlen -
618 crypto4xx_memcpy_from_le32(icv, icv, sizeof(icv));
620 if (crypto_memneq(icv, pd_uinfo->sr_va->save_digest, cp_len))
624 crypto4xx_ret_sg_desc(dev, pd_uinfo);
626 if (pd->pd_ctl.bf.status & 0xff) {
627 if (!__ratelimit(&dev->aead_ratelimit)) {
628 if (pd->pd_ctl.bf.status & 2)
629 pr_err("pad fail error\n");
630 if (pd->pd_ctl.bf.status & 4)
631 pr_err("seqnum fail\n");
632 if (pd->pd_ctl.bf.status & 8)
633 pr_err("error _notify\n");
634 pr_err("aead return err status = 0x%02x\n",
635 pd->pd_ctl.bf.status & 0xff);
636 pr_err("pd pad_ctl = 0x%08x\n",
637 pd->pd_ctl.bf.pd_pad_ctl);
642 if (pd_uinfo->state & PD_ENTRY_BUSY)
643 aead_request_complete(aead_req, -EINPROGRESS);
645 aead_request_complete(aead_req, err);
648 static void crypto4xx_pd_done(struct crypto4xx_device *dev, u32 idx)
650 struct ce_pd *pd = &dev->pdr[idx];
651 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[idx];
653 switch (crypto_tfm_alg_type(pd_uinfo->async_req->tfm)) {
654 case CRYPTO_ALG_TYPE_SKCIPHER:
655 crypto4xx_cipher_done(dev, pd_uinfo, pd);
657 case CRYPTO_ALG_TYPE_AEAD:
658 crypto4xx_aead_done(dev, pd_uinfo, pd);
660 case CRYPTO_ALG_TYPE_AHASH:
661 crypto4xx_ahash_done(dev, pd_uinfo);
666 static void crypto4xx_stop_all(struct crypto4xx_core_device *core_dev)
668 crypto4xx_destroy_pdr(core_dev->dev);
669 crypto4xx_destroy_gdr(core_dev->dev);
670 crypto4xx_destroy_sdr(core_dev->dev);
671 iounmap(core_dev->dev->ce_base);
672 kfree(core_dev->dev);
676 static u32 get_next_gd(u32 current)
678 if (current != PPC4XX_LAST_GD)
684 static u32 get_next_sd(u32 current)
686 if (current != PPC4XX_LAST_SD)
692 int crypto4xx_build_pd(struct crypto_async_request *req,
693 struct crypto4xx_ctx *ctx,
694 struct scatterlist *src,
695 struct scatterlist *dst,
696 const unsigned int datalen,
697 const __le32 *iv, const u32 iv_len,
698 const struct dynamic_sa_ctl *req_sa,
699 const unsigned int sa_len,
700 const unsigned int assoclen,
701 struct scatterlist *_dst)
703 struct crypto4xx_device *dev = ctx->dev;
704 struct dynamic_sa_ctl *sa;
708 u32 fst_gd = 0xffffffff;
709 u32 fst_sd = 0xffffffff;
712 struct pd_uinfo *pd_uinfo;
713 unsigned int nbytes = datalen;
714 size_t offset_to_sr_ptr;
717 bool is_busy, force_sd;
720 * There's a very subtile/disguised "bug" in the hardware that
721 * gets indirectly mentioned in 18.1.3.5 Encryption/Decryption
722 * of the hardware spec:
723 * *drum roll* the AES/(T)DES OFB and CFB modes are listed as
724 * operation modes for >>> "Block ciphers" <<<.
726 * To workaround this issue and stop the hardware from causing
727 * "overran dst buffer" on crypttexts that are not a multiple
728 * of 16 (AES_BLOCK_SIZE), we force the driver to use the
731 force_sd = (req_sa->sa_command_1.bf.crypto_mode9_8 == CRYPTO_MODE_CFB
732 || req_sa->sa_command_1.bf.crypto_mode9_8 == CRYPTO_MODE_OFB)
733 && (datalen % AES_BLOCK_SIZE);
735 /* figure how many gd are needed */
736 tmp = sg_nents_for_len(src, assoclen + datalen);
738 dev_err(dev->core_dev->device, "Invalid number of src SG.\n");
747 dst = scatterwalk_ffwd(_dst, dst, assoclen);
750 /* figure how many sd are needed */
751 if (sg_is_last(dst) && force_sd == false) {
754 if (datalen > PPC4XX_SD_BUFFER_SIZE) {
755 num_sd = datalen / PPC4XX_SD_BUFFER_SIZE;
756 if (datalen % PPC4XX_SD_BUFFER_SIZE)
764 * The follow section of code needs to be protected
765 * The gather ring and scatter ring needs to be consecutive
766 * In case of run out of any kind of descriptor, the descriptor
767 * already got must be return the original place.
769 spin_lock_irqsave(&dev->core_dev->lock, flags);
771 * Let the caller know to slow down, once more than 13/16ths = 81%
772 * of the available data contexts are being used simultaneously.
774 * With PPC4XX_NUM_PD = 256, this will leave a "backlog queue" for
775 * 31 more contexts. Before new requests have to be rejected.
777 if (req->flags & CRYPTO_TFM_REQ_MAY_BACKLOG) {
778 is_busy = ((dev->pdr_head - dev->pdr_tail) % PPC4XX_NUM_PD) >=
779 ((PPC4XX_NUM_PD * 13) / 16);
782 * To fix contention issues between ipsec (no blacklog) and
783 * dm-crypto (backlog) reserve 32 entries for "no backlog"
786 is_busy = ((dev->pdr_head - dev->pdr_tail) % PPC4XX_NUM_PD) >=
787 ((PPC4XX_NUM_PD * 15) / 16);
790 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
796 fst_gd = crypto4xx_get_n_gd(dev, num_gd);
797 if (fst_gd == ERING_WAS_FULL) {
798 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
803 fst_sd = crypto4xx_get_n_sd(dev, num_sd);
804 if (fst_sd == ERING_WAS_FULL) {
806 dev->gdr_head = fst_gd;
807 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
811 pd_entry = crypto4xx_get_pd_from_pdr_nolock(dev);
812 if (pd_entry == ERING_WAS_FULL) {
814 dev->gdr_head = fst_gd;
816 dev->sdr_head = fst_sd;
817 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
820 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
822 pd = &dev->pdr[pd_entry];
825 pd_uinfo = &dev->pdr_uinfo[pd_entry];
826 pd_uinfo->num_gd = num_gd;
827 pd_uinfo->num_sd = num_sd;
828 pd_uinfo->dest_va = dst;
829 pd_uinfo->async_req = req;
832 memcpy(pd_uinfo->sr_va->save_iv, iv, iv_len);
834 sa = pd_uinfo->sa_va;
835 memcpy(sa, req_sa, sa_len * 4);
837 sa->sa_command_1.bf.hash_crypto_offset = (assoclen >> 2);
838 offset_to_sr_ptr = get_dynamic_sa_offset_state_ptr_field(sa);
839 *(u32 *)((unsigned long)sa + offset_to_sr_ptr) = pd_uinfo->sr_pa;
843 struct scatterlist *sg;
845 /* get first gd we are going to use */
847 pd_uinfo->first_gd = fst_gd;
848 gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
851 sa->sa_command_0.bf.gather = 1;
852 /* walk the sg, and setup gather array */
858 len = min(sg->length, nbytes);
859 gd->ptr = dma_map_page(dev->core_dev->device,
860 sg_page(sg), sg->offset, len, DMA_TO_DEVICE);
861 gd->ctl_len.len = len;
862 gd->ctl_len.done = 0;
863 gd->ctl_len.ready = 1;
867 nbytes -= sg->length;
868 gd_idx = get_next_gd(gd_idx);
869 gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
873 pd->src = (u32)dma_map_page(dev->core_dev->device, sg_page(src),
874 src->offset, min(nbytes, src->length),
877 * Disable gather in sa command
879 sa->sa_command_0.bf.gather = 0;
881 * Indicate gather array is not used
883 pd_uinfo->first_gd = 0xffffffff;
887 * we know application give us dst a whole piece of memory
888 * no need to use scatter ring.
890 pd_uinfo->first_sd = 0xffffffff;
891 sa->sa_command_0.bf.scatter = 0;
892 pd->dest = (u32)dma_map_page(dev->core_dev->device,
893 sg_page(dst), dst->offset,
894 min(datalen, dst->length),
898 struct ce_sd *sd = NULL;
902 sa->sa_command_0.bf.scatter = 1;
903 pd_uinfo->first_sd = fst_sd;
904 sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
906 /* setup scatter descriptor */
909 /* sd->ptr should be setup by sd_init routine*/
910 if (nbytes >= PPC4XX_SD_BUFFER_SIZE)
911 nbytes -= PPC4XX_SD_BUFFER_SIZE;
915 sd_idx = get_next_sd(sd_idx);
916 sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
917 /* setup scatter descriptor */
920 if (nbytes >= PPC4XX_SD_BUFFER_SIZE) {
921 nbytes -= PPC4XX_SD_BUFFER_SIZE;
924 * SD entry can hold PPC4XX_SD_BUFFER_SIZE,
925 * which is more than nbytes, so done.
932 pd->pd_ctl.w = PD_CTL_HOST_READY |
933 ((crypto_tfm_alg_type(req->tfm) == CRYPTO_ALG_TYPE_AHASH) |
934 (crypto_tfm_alg_type(req->tfm) == CRYPTO_ALG_TYPE_AEAD) ?
935 PD_CTL_HASH_FINAL : 0);
936 pd->pd_ctl_len.w = 0x00400000 | (assoclen + datalen);
937 pd_uinfo->state = PD_ENTRY_INUSE | (is_busy ? PD_ENTRY_BUSY : 0);
940 /* write any value to push engine to read a pd */
941 writel(0, dev->ce_base + CRYPTO4XX_INT_DESCR_RD);
942 writel(1, dev->ce_base + CRYPTO4XX_INT_DESCR_RD);
943 return is_busy ? -EBUSY : -EINPROGRESS;
947 * Algorithm Registration Functions
949 static void crypto4xx_ctx_init(struct crypto4xx_alg *amcc_alg,
950 struct crypto4xx_ctx *ctx)
952 ctx->dev = amcc_alg->dev;
958 static int crypto4xx_sk_init(struct crypto_skcipher *sk)
960 struct skcipher_alg *alg = crypto_skcipher_alg(sk);
961 struct crypto4xx_alg *amcc_alg;
962 struct crypto4xx_ctx *ctx = crypto_skcipher_ctx(sk);
964 if (alg->base.cra_flags & CRYPTO_ALG_NEED_FALLBACK) {
965 ctx->sw_cipher.cipher =
966 crypto_alloc_sync_skcipher(alg->base.cra_name, 0,
967 CRYPTO_ALG_NEED_FALLBACK);
968 if (IS_ERR(ctx->sw_cipher.cipher))
969 return PTR_ERR(ctx->sw_cipher.cipher);
972 amcc_alg = container_of(alg, struct crypto4xx_alg, alg.u.cipher);
973 crypto4xx_ctx_init(amcc_alg, ctx);
977 static void crypto4xx_common_exit(struct crypto4xx_ctx *ctx)
979 crypto4xx_free_sa(ctx);
982 static void crypto4xx_sk_exit(struct crypto_skcipher *sk)
984 struct crypto4xx_ctx *ctx = crypto_skcipher_ctx(sk);
986 crypto4xx_common_exit(ctx);
987 if (ctx->sw_cipher.cipher)
988 crypto_free_sync_skcipher(ctx->sw_cipher.cipher);
991 static int crypto4xx_aead_init(struct crypto_aead *tfm)
993 struct aead_alg *alg = crypto_aead_alg(tfm);
994 struct crypto4xx_ctx *ctx = crypto_aead_ctx(tfm);
995 struct crypto4xx_alg *amcc_alg;
997 ctx->sw_cipher.aead = crypto_alloc_aead(alg->base.cra_name, 0,
998 CRYPTO_ALG_NEED_FALLBACK |
1000 if (IS_ERR(ctx->sw_cipher.aead))
1001 return PTR_ERR(ctx->sw_cipher.aead);
1003 amcc_alg = container_of(alg, struct crypto4xx_alg, alg.u.aead);
1004 crypto4xx_ctx_init(amcc_alg, ctx);
1005 crypto_aead_set_reqsize(tfm, max(sizeof(struct aead_request) + 32 +
1006 crypto_aead_reqsize(ctx->sw_cipher.aead),
1007 sizeof(struct crypto4xx_aead_reqctx)));
1011 static void crypto4xx_aead_exit(struct crypto_aead *tfm)
1013 struct crypto4xx_ctx *ctx = crypto_aead_ctx(tfm);
1015 crypto4xx_common_exit(ctx);
1016 crypto_free_aead(ctx->sw_cipher.aead);
1019 static int crypto4xx_register_alg(struct crypto4xx_device *sec_dev,
1020 struct crypto4xx_alg_common *crypto_alg,
1023 struct crypto4xx_alg *alg;
1027 for (i = 0; i < array_size; i++) {
1028 alg = kzalloc(sizeof(struct crypto4xx_alg), GFP_KERNEL);
1032 alg->alg = crypto_alg[i];
1035 switch (alg->alg.type) {
1036 case CRYPTO_ALG_TYPE_AEAD:
1037 rc = crypto_register_aead(&alg->alg.u.aead);
1040 case CRYPTO_ALG_TYPE_AHASH:
1041 rc = crypto_register_ahash(&alg->alg.u.hash);
1044 case CRYPTO_ALG_TYPE_RNG:
1045 rc = crypto_register_rng(&alg->alg.u.rng);
1049 rc = crypto_register_skcipher(&alg->alg.u.cipher);
1056 list_add_tail(&alg->entry, &sec_dev->alg_list);
1062 static void crypto4xx_unregister_alg(struct crypto4xx_device *sec_dev)
1064 struct crypto4xx_alg *alg, *tmp;
1066 list_for_each_entry_safe(alg, tmp, &sec_dev->alg_list, entry) {
1067 list_del(&alg->entry);
1068 switch (alg->alg.type) {
1069 case CRYPTO_ALG_TYPE_AHASH:
1070 crypto_unregister_ahash(&alg->alg.u.hash);
1073 case CRYPTO_ALG_TYPE_AEAD:
1074 crypto_unregister_aead(&alg->alg.u.aead);
1077 case CRYPTO_ALG_TYPE_RNG:
1078 crypto_unregister_rng(&alg->alg.u.rng);
1082 crypto_unregister_skcipher(&alg->alg.u.cipher);
1088 static void crypto4xx_bh_tasklet_cb(unsigned long data)
1090 struct device *dev = (struct device *)data;
1091 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1092 struct pd_uinfo *pd_uinfo;
1094 u32 tail = core_dev->dev->pdr_tail;
1095 u32 head = core_dev->dev->pdr_head;
1098 pd_uinfo = &core_dev->dev->pdr_uinfo[tail];
1099 pd = &core_dev->dev->pdr[tail];
1100 if ((pd_uinfo->state & PD_ENTRY_INUSE) &&
1101 ((READ_ONCE(pd->pd_ctl.w) &
1102 (PD_CTL_PE_DONE | PD_CTL_HOST_READY)) ==
1104 crypto4xx_pd_done(core_dev->dev, tail);
1105 tail = crypto4xx_put_pd_to_pdr(core_dev->dev, tail);
1107 /* if tail not done, break */
1110 } while (head != tail);
1116 static inline irqreturn_t crypto4xx_interrupt_handler(int irq, void *data,
1119 struct device *dev = (struct device *)data;
1120 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1122 writel(clr_val, core_dev->dev->ce_base + CRYPTO4XX_INT_CLR);
1123 tasklet_schedule(&core_dev->tasklet);
1128 static irqreturn_t crypto4xx_ce_interrupt_handler(int irq, void *data)
1130 return crypto4xx_interrupt_handler(irq, data, PPC4XX_INTERRUPT_CLR);
1133 static irqreturn_t crypto4xx_ce_interrupt_handler_revb(int irq, void *data)
1135 return crypto4xx_interrupt_handler(irq, data, PPC4XX_INTERRUPT_CLR |
1136 PPC4XX_TMO_ERR_INT);
1139 static int ppc4xx_prng_data_read(struct crypto4xx_device *dev,
1140 u8 *data, unsigned int max)
1142 unsigned int i, curr = 0;
1146 /* trigger PRN generation */
1147 writel(PPC4XX_PRNG_CTRL_AUTO_EN,
1148 dev->ce_base + CRYPTO4XX_PRNG_CTRL);
1150 for (i = 0; i < 1024; i++) {
1151 /* usually 19 iterations are enough */
1152 if ((readl(dev->ce_base + CRYPTO4XX_PRNG_STAT) &
1153 CRYPTO4XX_PRNG_STAT_BUSY))
1156 val[0] = readl_be(dev->ce_base + CRYPTO4XX_PRNG_RES_0);
1157 val[1] = readl_be(dev->ce_base + CRYPTO4XX_PRNG_RES_1);
1163 if ((max - curr) >= 8) {
1164 memcpy(data, &val, 8);
1168 /* copy only remaining bytes */
1169 memcpy(data, &val, max - curr);
1172 } while (curr < max);
1177 static int crypto4xx_prng_generate(struct crypto_rng *tfm,
1178 const u8 *src, unsigned int slen,
1179 u8 *dstn, unsigned int dlen)
1181 struct rng_alg *alg = crypto_rng_alg(tfm);
1182 struct crypto4xx_alg *amcc_alg;
1183 struct crypto4xx_device *dev;
1186 amcc_alg = container_of(alg, struct crypto4xx_alg, alg.u.rng);
1187 dev = amcc_alg->dev;
1189 mutex_lock(&dev->core_dev->rng_lock);
1190 ret = ppc4xx_prng_data_read(dev, dstn, dlen);
1191 mutex_unlock(&dev->core_dev->rng_lock);
1196 static int crypto4xx_prng_seed(struct crypto_rng *tfm, const u8 *seed,
1203 * Supported Crypto Algorithms
1205 static struct crypto4xx_alg_common crypto4xx_alg[] = {
1206 /* Crypto AES modes */
1207 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1209 .cra_name = "cbc(aes)",
1210 .cra_driver_name = "cbc-aes-ppc4xx",
1211 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1212 .cra_flags = CRYPTO_ALG_ASYNC |
1213 CRYPTO_ALG_KERN_DRIVER_ONLY,
1214 .cra_blocksize = AES_BLOCK_SIZE,
1215 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1216 .cra_module = THIS_MODULE,
1218 .min_keysize = AES_MIN_KEY_SIZE,
1219 .max_keysize = AES_MAX_KEY_SIZE,
1220 .ivsize = AES_IV_SIZE,
1221 .setkey = crypto4xx_setkey_aes_cbc,
1222 .encrypt = crypto4xx_encrypt_iv,
1223 .decrypt = crypto4xx_decrypt_iv,
1224 .init = crypto4xx_sk_init,
1225 .exit = crypto4xx_sk_exit,
1227 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1229 .cra_name = "cfb(aes)",
1230 .cra_driver_name = "cfb-aes-ppc4xx",
1231 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1232 .cra_flags = CRYPTO_ALG_ASYNC |
1233 CRYPTO_ALG_KERN_DRIVER_ONLY,
1235 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1236 .cra_module = THIS_MODULE,
1238 .min_keysize = AES_MIN_KEY_SIZE,
1239 .max_keysize = AES_MAX_KEY_SIZE,
1240 .ivsize = AES_IV_SIZE,
1241 .setkey = crypto4xx_setkey_aes_cfb,
1242 .encrypt = crypto4xx_encrypt_iv,
1243 .decrypt = crypto4xx_decrypt_iv,
1244 .init = crypto4xx_sk_init,
1245 .exit = crypto4xx_sk_exit,
1247 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1249 .cra_name = "ctr(aes)",
1250 .cra_driver_name = "ctr-aes-ppc4xx",
1251 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1252 .cra_flags = CRYPTO_ALG_NEED_FALLBACK |
1254 CRYPTO_ALG_KERN_DRIVER_ONLY,
1256 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1257 .cra_module = THIS_MODULE,
1259 .min_keysize = AES_MIN_KEY_SIZE,
1260 .max_keysize = AES_MAX_KEY_SIZE,
1261 .ivsize = AES_IV_SIZE,
1262 .setkey = crypto4xx_setkey_aes_ctr,
1263 .encrypt = crypto4xx_encrypt_ctr,
1264 .decrypt = crypto4xx_decrypt_ctr,
1265 .init = crypto4xx_sk_init,
1266 .exit = crypto4xx_sk_exit,
1268 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1270 .cra_name = "rfc3686(ctr(aes))",
1271 .cra_driver_name = "rfc3686-ctr-aes-ppc4xx",
1272 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1273 .cra_flags = CRYPTO_ALG_ASYNC |
1274 CRYPTO_ALG_KERN_DRIVER_ONLY,
1276 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1277 .cra_module = THIS_MODULE,
1279 .min_keysize = AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE,
1280 .max_keysize = AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE,
1281 .ivsize = CTR_RFC3686_IV_SIZE,
1282 .setkey = crypto4xx_setkey_rfc3686,
1283 .encrypt = crypto4xx_rfc3686_encrypt,
1284 .decrypt = crypto4xx_rfc3686_decrypt,
1285 .init = crypto4xx_sk_init,
1286 .exit = crypto4xx_sk_exit,
1288 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1290 .cra_name = "ecb(aes)",
1291 .cra_driver_name = "ecb-aes-ppc4xx",
1292 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1293 .cra_flags = CRYPTO_ALG_ASYNC |
1294 CRYPTO_ALG_KERN_DRIVER_ONLY,
1295 .cra_blocksize = AES_BLOCK_SIZE,
1296 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1297 .cra_module = THIS_MODULE,
1299 .min_keysize = AES_MIN_KEY_SIZE,
1300 .max_keysize = AES_MAX_KEY_SIZE,
1301 .setkey = crypto4xx_setkey_aes_ecb,
1302 .encrypt = crypto4xx_encrypt_noiv,
1303 .decrypt = crypto4xx_decrypt_noiv,
1304 .init = crypto4xx_sk_init,
1305 .exit = crypto4xx_sk_exit,
1307 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1309 .cra_name = "ofb(aes)",
1310 .cra_driver_name = "ofb-aes-ppc4xx",
1311 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1312 .cra_flags = CRYPTO_ALG_ASYNC |
1313 CRYPTO_ALG_KERN_DRIVER_ONLY,
1315 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1316 .cra_module = THIS_MODULE,
1318 .min_keysize = AES_MIN_KEY_SIZE,
1319 .max_keysize = AES_MAX_KEY_SIZE,
1320 .ivsize = AES_IV_SIZE,
1321 .setkey = crypto4xx_setkey_aes_ofb,
1322 .encrypt = crypto4xx_encrypt_iv,
1323 .decrypt = crypto4xx_decrypt_iv,
1324 .init = crypto4xx_sk_init,
1325 .exit = crypto4xx_sk_exit,
1329 { .type = CRYPTO_ALG_TYPE_AEAD, .u.aead = {
1330 .setkey = crypto4xx_setkey_aes_ccm,
1331 .setauthsize = crypto4xx_setauthsize_aead,
1332 .encrypt = crypto4xx_encrypt_aes_ccm,
1333 .decrypt = crypto4xx_decrypt_aes_ccm,
1334 .init = crypto4xx_aead_init,
1335 .exit = crypto4xx_aead_exit,
1336 .ivsize = AES_BLOCK_SIZE,
1339 .cra_name = "ccm(aes)",
1340 .cra_driver_name = "ccm-aes-ppc4xx",
1341 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1342 .cra_flags = CRYPTO_ALG_ASYNC |
1343 CRYPTO_ALG_NEED_FALLBACK |
1344 CRYPTO_ALG_KERN_DRIVER_ONLY,
1346 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1347 .cra_module = THIS_MODULE,
1350 { .type = CRYPTO_ALG_TYPE_AEAD, .u.aead = {
1351 .setkey = crypto4xx_setkey_aes_gcm,
1352 .setauthsize = crypto4xx_setauthsize_aead,
1353 .encrypt = crypto4xx_encrypt_aes_gcm,
1354 .decrypt = crypto4xx_decrypt_aes_gcm,
1355 .init = crypto4xx_aead_init,
1356 .exit = crypto4xx_aead_exit,
1357 .ivsize = GCM_AES_IV_SIZE,
1360 .cra_name = "gcm(aes)",
1361 .cra_driver_name = "gcm-aes-ppc4xx",
1362 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1363 .cra_flags = CRYPTO_ALG_ASYNC |
1364 CRYPTO_ALG_NEED_FALLBACK |
1365 CRYPTO_ALG_KERN_DRIVER_ONLY,
1367 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1368 .cra_module = THIS_MODULE,
1371 { .type = CRYPTO_ALG_TYPE_RNG, .u.rng = {
1373 .cra_name = "stdrng",
1374 .cra_driver_name = "crypto4xx_rng",
1375 .cra_priority = 300,
1377 .cra_module = THIS_MODULE,
1379 .generate = crypto4xx_prng_generate,
1380 .seed = crypto4xx_prng_seed,
1386 * Module Initialization Routine
1388 static int crypto4xx_probe(struct platform_device *ofdev)
1391 struct resource res;
1392 struct device *dev = &ofdev->dev;
1393 struct crypto4xx_core_device *core_dev;
1395 bool is_revb = true;
1397 rc = of_address_to_resource(ofdev->dev.of_node, 0, &res);
1401 if (of_find_compatible_node(NULL, NULL, "amcc,ppc460ex-crypto")) {
1402 mtdcri(SDR0, PPC460EX_SDR0_SRST,
1403 mfdcri(SDR0, PPC460EX_SDR0_SRST) | PPC460EX_CE_RESET);
1404 mtdcri(SDR0, PPC460EX_SDR0_SRST,
1405 mfdcri(SDR0, PPC460EX_SDR0_SRST) & ~PPC460EX_CE_RESET);
1406 } else if (of_find_compatible_node(NULL, NULL,
1407 "amcc,ppc405ex-crypto")) {
1408 mtdcri(SDR0, PPC405EX_SDR0_SRST,
1409 mfdcri(SDR0, PPC405EX_SDR0_SRST) | PPC405EX_CE_RESET);
1410 mtdcri(SDR0, PPC405EX_SDR0_SRST,
1411 mfdcri(SDR0, PPC405EX_SDR0_SRST) & ~PPC405EX_CE_RESET);
1413 } else if (of_find_compatible_node(NULL, NULL,
1414 "amcc,ppc460sx-crypto")) {
1415 mtdcri(SDR0, PPC460SX_SDR0_SRST,
1416 mfdcri(SDR0, PPC460SX_SDR0_SRST) | PPC460SX_CE_RESET);
1417 mtdcri(SDR0, PPC460SX_SDR0_SRST,
1418 mfdcri(SDR0, PPC460SX_SDR0_SRST) & ~PPC460SX_CE_RESET);
1420 printk(KERN_ERR "Crypto Function Not supported!\n");
1424 core_dev = kzalloc(sizeof(struct crypto4xx_core_device), GFP_KERNEL);
1428 dev_set_drvdata(dev, core_dev);
1429 core_dev->ofdev = ofdev;
1430 core_dev->dev = kzalloc(sizeof(struct crypto4xx_device), GFP_KERNEL);
1436 * Older version of 460EX/GT have a hardware bug.
1437 * Hence they do not support H/W based security intr coalescing
1439 pvr = mfspr(SPRN_PVR);
1440 if (is_revb && ((pvr >> 4) == 0x130218A)) {
1441 u32 min = PVR_MIN(pvr);
1444 dev_info(dev, "RevA detected - disable interrupt coalescing\n");
1449 core_dev->dev->core_dev = core_dev;
1450 core_dev->dev->is_revb = is_revb;
1451 core_dev->device = dev;
1452 mutex_init(&core_dev->rng_lock);
1453 spin_lock_init(&core_dev->lock);
1454 INIT_LIST_HEAD(&core_dev->dev->alg_list);
1455 ratelimit_default_init(&core_dev->dev->aead_ratelimit);
1456 rc = crypto4xx_build_pdr(core_dev->dev);
1460 rc = crypto4xx_build_gdr(core_dev->dev);
1464 rc = crypto4xx_build_sdr(core_dev->dev);
1468 /* Init tasklet for bottom half processing */
1469 tasklet_init(&core_dev->tasklet, crypto4xx_bh_tasklet_cb,
1470 (unsigned long) dev);
1472 core_dev->dev->ce_base = of_iomap(ofdev->dev.of_node, 0);
1473 if (!core_dev->dev->ce_base) {
1474 dev_err(dev, "failed to of_iomap\n");
1479 /* Register for Crypto isr, Crypto Engine IRQ */
1480 core_dev->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1481 rc = request_irq(core_dev->irq, is_revb ?
1482 crypto4xx_ce_interrupt_handler_revb :
1483 crypto4xx_ce_interrupt_handler, 0,
1484 KBUILD_MODNAME, dev);
1486 goto err_request_irq;
1488 /* need to setup pdr, rdr, gdr and sdr before this */
1489 crypto4xx_hw_init(core_dev->dev);
1491 /* Register security algorithms with Linux CryptoAPI */
1492 rc = crypto4xx_register_alg(core_dev->dev, crypto4xx_alg,
1493 ARRAY_SIZE(crypto4xx_alg));
1497 ppc4xx_trng_probe(core_dev);
1501 free_irq(core_dev->irq, dev);
1503 irq_dispose_mapping(core_dev->irq);
1504 iounmap(core_dev->dev->ce_base);
1506 tasklet_kill(&core_dev->tasklet);
1508 crypto4xx_destroy_sdr(core_dev->dev);
1509 crypto4xx_destroy_gdr(core_dev->dev);
1511 crypto4xx_destroy_pdr(core_dev->dev);
1512 kfree(core_dev->dev);
1519 static int crypto4xx_remove(struct platform_device *ofdev)
1521 struct device *dev = &ofdev->dev;
1522 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1524 ppc4xx_trng_remove(core_dev);
1526 free_irq(core_dev->irq, dev);
1527 irq_dispose_mapping(core_dev->irq);
1529 tasklet_kill(&core_dev->tasklet);
1530 /* Un-register with Linux CryptoAPI */
1531 crypto4xx_unregister_alg(core_dev->dev);
1532 mutex_destroy(&core_dev->rng_lock);
1533 /* Free all allocated memory */
1534 crypto4xx_stop_all(core_dev);
1539 static const struct of_device_id crypto4xx_match[] = {
1540 { .compatible = "amcc,ppc4xx-crypto",},
1543 MODULE_DEVICE_TABLE(of, crypto4xx_match);
1545 static struct platform_driver crypto4xx_driver = {
1547 .name = KBUILD_MODNAME,
1548 .of_match_table = crypto4xx_match,
1550 .probe = crypto4xx_probe,
1551 .remove = crypto4xx_remove,
1554 module_platform_driver(crypto4xx_driver);
1556 MODULE_LICENSE("GPL");
1557 MODULE_AUTHOR("James Hsiao <jhsiao@amcc.com>");
1558 MODULE_DESCRIPTION("Driver for AMCC PPC4xx crypto accelerator");