2 * Copyright (c) 2015 Linaro Ltd.
3 * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/cpu.h>
17 #include <linux/cpu_cooling.h>
18 #include <linux/cpufreq.h>
19 #include <linux/cpumask.h>
20 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_opp.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/slab.h>
26 #include <linux/thermal.h>
28 #define MIN_VOLT_SHIFT (100000)
29 #define MAX_VOLT_SHIFT (200000)
30 #define MAX_VOLT_LIMIT (1150000)
31 #define VOLT_TOL (10000)
34 * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS
35 * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
36 * Mediatek SoCs has two voltage inputs, Vproc and Vsram. In some cases the two
37 * voltage inputs need to be controlled under a hardware limitation:
38 * 100mV < Vsram - Vproc < 200mV
40 * When scaling the clock frequency of a CPU clock domain, the clock source
41 * needs to be switched to another stable PLL clock temporarily until
42 * the original PLL becomes stable at target frequency.
44 struct mtk_cpu_dvfs_info {
46 struct device *cpu_dev;
47 struct regulator *proc_reg;
48 struct regulator *sram_reg;
50 struct clk *inter_clk;
51 struct thermal_cooling_device *cdev;
52 struct list_head list_head;
53 int intermediate_voltage;
54 bool need_voltage_tracking;
57 static LIST_HEAD(dvfs_info_list);
59 static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu)
61 struct mtk_cpu_dvfs_info *info;
63 list_for_each_entry(info, &dvfs_info_list, list_head) {
64 if (cpumask_test_cpu(cpu, &info->cpus))
71 static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
74 struct regulator *proc_reg = info->proc_reg;
75 struct regulator *sram_reg = info->sram_reg;
76 int old_vproc, old_vsram, new_vsram, vsram, vproc, ret;
78 old_vproc = regulator_get_voltage(proc_reg);
80 pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
83 /* Vsram should not exceed the maximum allowed voltage of SoC. */
84 new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT);
86 if (old_vproc < new_vproc) {
88 * When scaling up voltages, Vsram and Vproc scale up step
89 * by step. At each step, set Vsram to (Vproc + 200mV) first,
90 * then set Vproc to (Vsram - 100mV).
91 * Keep doing it until Vsram and Vproc hit target voltages.
94 old_vsram = regulator_get_voltage(sram_reg);
96 pr_err("%s: invalid Vsram value: %d\n",
100 old_vproc = regulator_get_voltage(proc_reg);
102 pr_err("%s: invalid Vproc value: %d\n",
103 __func__, old_vproc);
107 vsram = min(new_vsram, old_vproc + MAX_VOLT_SHIFT);
109 if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
110 vsram = MAX_VOLT_LIMIT;
113 * If the target Vsram hits the maximum voltage,
114 * try to set the exact voltage value first.
116 ret = regulator_set_voltage(sram_reg, vsram,
119 ret = regulator_set_voltage(sram_reg,
125 ret = regulator_set_voltage(sram_reg, vsram,
128 vproc = vsram - MIN_VOLT_SHIFT;
133 ret = regulator_set_voltage(proc_reg, vproc,
136 regulator_set_voltage(sram_reg, old_vsram,
140 } while (vproc < new_vproc || vsram < new_vsram);
141 } else if (old_vproc > new_vproc) {
143 * When scaling down voltages, Vsram and Vproc scale down step
144 * by step. At each step, set Vproc to (Vsram - 200mV) first,
145 * then set Vproc to (Vproc + 100mV).
146 * Keep doing it until Vsram and Vproc hit target voltages.
149 old_vproc = regulator_get_voltage(proc_reg);
151 pr_err("%s: invalid Vproc value: %d\n",
152 __func__, old_vproc);
155 old_vsram = regulator_get_voltage(sram_reg);
157 pr_err("%s: invalid Vsram value: %d\n",
158 __func__, old_vsram);
162 vproc = max(new_vproc, old_vsram - MAX_VOLT_SHIFT);
163 ret = regulator_set_voltage(proc_reg, vproc,
168 if (vproc == new_vproc)
171 vsram = max(new_vsram, vproc + MIN_VOLT_SHIFT);
173 if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
174 vsram = MAX_VOLT_LIMIT;
177 * If the target Vsram hits the maximum voltage,
178 * try to set the exact voltage value first.
180 ret = regulator_set_voltage(sram_reg, vsram,
183 ret = regulator_set_voltage(sram_reg,
187 ret = regulator_set_voltage(sram_reg, vsram,
192 regulator_set_voltage(proc_reg, old_vproc,
196 } while (vproc > new_vproc + VOLT_TOL ||
197 vsram > new_vsram + VOLT_TOL);
203 static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
205 if (info->need_voltage_tracking)
206 return mtk_cpufreq_voltage_tracking(info, vproc);
208 return regulator_set_voltage(info->proc_reg, vproc,
212 static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
215 struct cpufreq_frequency_table *freq_table = policy->freq_table;
216 struct clk *cpu_clk = policy->clk;
217 struct clk *armpll = clk_get_parent(cpu_clk);
218 struct mtk_cpu_dvfs_info *info = policy->driver_data;
219 struct device *cpu_dev = info->cpu_dev;
220 struct dev_pm_opp *opp;
221 long freq_hz, old_freq_hz;
222 int vproc, old_vproc, inter_vproc, target_vproc, ret;
224 inter_vproc = info->intermediate_voltage;
226 old_freq_hz = clk_get_rate(cpu_clk);
227 old_vproc = regulator_get_voltage(info->proc_reg);
229 pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
233 freq_hz = freq_table[index].frequency * 1000;
235 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
237 pr_err("cpu%d: failed to find OPP for %ld\n",
238 policy->cpu, freq_hz);
241 vproc = dev_pm_opp_get_voltage(opp);
245 * If the new voltage or the intermediate voltage is higher than the
246 * current voltage, scale up voltage first.
248 target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
249 if (old_vproc < target_vproc) {
250 ret = mtk_cpufreq_set_voltage(info, target_vproc);
252 pr_err("cpu%d: failed to scale up voltage!\n",
254 mtk_cpufreq_set_voltage(info, old_vproc);
259 /* Reparent the CPU clock to intermediate clock. */
260 ret = clk_set_parent(cpu_clk, info->inter_clk);
262 pr_err("cpu%d: failed to re-parent cpu clock!\n",
264 mtk_cpufreq_set_voltage(info, old_vproc);
269 /* Set the original PLL to target rate. */
270 ret = clk_set_rate(armpll, freq_hz);
272 pr_err("cpu%d: failed to scale cpu clock rate!\n",
274 clk_set_parent(cpu_clk, armpll);
275 mtk_cpufreq_set_voltage(info, old_vproc);
279 /* Set parent of CPU clock back to the original PLL. */
280 ret = clk_set_parent(cpu_clk, armpll);
282 pr_err("cpu%d: failed to re-parent cpu clock!\n",
284 mtk_cpufreq_set_voltage(info, inter_vproc);
290 * If the new voltage is lower than the intermediate voltage or the
291 * original voltage, scale down to the new voltage.
293 if (vproc < inter_vproc || vproc < old_vproc) {
294 ret = mtk_cpufreq_set_voltage(info, vproc);
296 pr_err("cpu%d: failed to scale down voltage!\n",
298 clk_set_parent(cpu_clk, info->inter_clk);
299 clk_set_rate(armpll, old_freq_hz);
300 clk_set_parent(cpu_clk, armpll);
308 #define DYNAMIC_POWER "dynamic-power-coefficient"
310 static void mtk_cpufreq_ready(struct cpufreq_policy *policy)
312 struct mtk_cpu_dvfs_info *info = policy->driver_data;
313 struct device_node *np = of_node_get(info->cpu_dev->of_node);
319 if (of_find_property(np, "#cooling-cells", NULL)) {
320 of_property_read_u32(np, DYNAMIC_POWER, &capacitance);
322 info->cdev = of_cpufreq_power_cooling_register(np,
323 policy->related_cpus,
327 if (IS_ERR(info->cdev)) {
328 dev_err(info->cpu_dev,
329 "running cpufreq without cooling device: %ld\n",
330 PTR_ERR(info->cdev));
339 static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
341 struct device *cpu_dev;
342 struct regulator *proc_reg = ERR_PTR(-ENODEV);
343 struct regulator *sram_reg = ERR_PTR(-ENODEV);
344 struct clk *cpu_clk = ERR_PTR(-ENODEV);
345 struct clk *inter_clk = ERR_PTR(-ENODEV);
346 struct dev_pm_opp *opp;
350 cpu_dev = get_cpu_device(cpu);
352 pr_err("failed to get cpu%d device\n", cpu);
356 cpu_clk = clk_get(cpu_dev, "cpu");
357 if (IS_ERR(cpu_clk)) {
358 if (PTR_ERR(cpu_clk) == -EPROBE_DEFER)
359 pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu);
361 pr_err("failed to get cpu clk for cpu%d\n", cpu);
363 ret = PTR_ERR(cpu_clk);
367 inter_clk = clk_get(cpu_dev, "intermediate");
368 if (IS_ERR(inter_clk)) {
369 if (PTR_ERR(inter_clk) == -EPROBE_DEFER)
370 pr_warn("intermediate clk for cpu%d not ready, retry.\n",
373 pr_err("failed to get intermediate clk for cpu%d\n",
376 ret = PTR_ERR(inter_clk);
377 goto out_free_resources;
380 proc_reg = regulator_get_exclusive(cpu_dev, "proc");
381 if (IS_ERR(proc_reg)) {
382 if (PTR_ERR(proc_reg) == -EPROBE_DEFER)
383 pr_warn("proc regulator for cpu%d not ready, retry.\n",
386 pr_err("failed to get proc regulator for cpu%d\n",
389 ret = PTR_ERR(proc_reg);
390 goto out_free_resources;
393 /* Both presence and absence of sram regulator are valid cases. */
394 sram_reg = regulator_get_exclusive(cpu_dev, "sram");
396 /* Get OPP-sharing information from "operating-points-v2" bindings */
397 ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus);
399 pr_err("failed to get OPP-sharing information for cpu%d\n",
401 goto out_free_resources;
404 ret = dev_pm_opp_of_cpumask_add_table(&info->cpus);
406 pr_warn("no OPP table for cpu%d\n", cpu);
407 goto out_free_resources;
410 /* Search a safe voltage for intermediate frequency. */
411 rate = clk_get_rate(inter_clk);
412 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
414 pr_err("failed to get intermediate opp for cpu%d\n", cpu);
416 goto out_free_opp_table;
418 info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
421 info->cpu_dev = cpu_dev;
422 info->proc_reg = proc_reg;
423 info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg;
424 info->cpu_clk = cpu_clk;
425 info->inter_clk = inter_clk;
428 * If SRAM regulator is present, software "voltage tracking" is needed
429 * for this CPU power domain.
431 info->need_voltage_tracking = !IS_ERR(sram_reg);
436 dev_pm_opp_of_cpumask_remove_table(&info->cpus);
439 if (!IS_ERR(proc_reg))
440 regulator_put(proc_reg);
441 if (!IS_ERR(sram_reg))
442 regulator_put(sram_reg);
443 if (!IS_ERR(cpu_clk))
445 if (!IS_ERR(inter_clk))
451 static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
453 if (!IS_ERR(info->proc_reg))
454 regulator_put(info->proc_reg);
455 if (!IS_ERR(info->sram_reg))
456 regulator_put(info->sram_reg);
457 if (!IS_ERR(info->cpu_clk))
458 clk_put(info->cpu_clk);
459 if (!IS_ERR(info->inter_clk))
460 clk_put(info->inter_clk);
462 dev_pm_opp_of_cpumask_remove_table(&info->cpus);
465 static int mtk_cpufreq_init(struct cpufreq_policy *policy)
467 struct mtk_cpu_dvfs_info *info;
468 struct cpufreq_frequency_table *freq_table;
471 info = mtk_cpu_dvfs_info_lookup(policy->cpu);
473 pr_err("dvfs info for cpu%d is not initialized.\n",
478 ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table);
480 pr_err("failed to init cpufreq table for cpu%d: %d\n",
485 ret = cpufreq_table_validate_and_show(policy, freq_table);
487 pr_err("%s: invalid frequency table: %d\n", __func__, ret);
488 goto out_free_cpufreq_table;
491 cpumask_copy(policy->cpus, &info->cpus);
492 policy->driver_data = info;
493 policy->clk = info->cpu_clk;
497 out_free_cpufreq_table:
498 dev_pm_opp_free_cpufreq_table(info->cpu_dev, &freq_table);
502 static int mtk_cpufreq_exit(struct cpufreq_policy *policy)
504 struct mtk_cpu_dvfs_info *info = policy->driver_data;
506 cpufreq_cooling_unregister(info->cdev);
507 dev_pm_opp_free_cpufreq_table(info->cpu_dev, &policy->freq_table);
512 static struct cpufreq_driver mt8173_cpufreq_driver = {
513 .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
514 CPUFREQ_HAVE_GOVERNOR_PER_POLICY,
515 .verify = cpufreq_generic_frequency_table_verify,
516 .target_index = mtk_cpufreq_set_target,
517 .get = cpufreq_generic_get,
518 .init = mtk_cpufreq_init,
519 .exit = mtk_cpufreq_exit,
520 .ready = mtk_cpufreq_ready,
521 .name = "mtk-cpufreq",
522 .attr = cpufreq_generic_attr,
525 static int mt8173_cpufreq_probe(struct platform_device *pdev)
527 struct mtk_cpu_dvfs_info *info, *tmp;
530 for_each_possible_cpu(cpu) {
531 info = mtk_cpu_dvfs_info_lookup(cpu);
535 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
538 goto release_dvfs_info_list;
541 ret = mtk_cpu_dvfs_info_init(info, cpu);
544 "failed to initialize dvfs info for cpu%d\n",
546 goto release_dvfs_info_list;
549 list_add(&info->list_head, &dvfs_info_list);
552 ret = cpufreq_register_driver(&mt8173_cpufreq_driver);
554 dev_err(&pdev->dev, "failed to register mtk cpufreq driver\n");
555 goto release_dvfs_info_list;
560 release_dvfs_info_list:
561 list_for_each_entry_safe(info, tmp, &dvfs_info_list, list_head) {
562 mtk_cpu_dvfs_info_release(info);
563 list_del(&info->list_head);
569 static struct platform_driver mt8173_cpufreq_platdrv = {
571 .name = "mt8173-cpufreq",
573 .probe = mt8173_cpufreq_probe,
576 /* List of machines supported by this driver */
577 static const struct of_device_id mt8173_cpufreq_machines[] __initconst = {
578 { .compatible = "mediatek,mt817x", },
579 { .compatible = "mediatek,mt8173", },
580 { .compatible = "mediatek,mt8176", },
585 static int __init mt8173_cpufreq_driver_init(void)
587 struct device_node *np;
588 const struct of_device_id *match;
589 struct platform_device *pdev;
592 np = of_find_node_by_path("/");
596 match = of_match_node(mt8173_cpufreq_machines, np);
599 pr_warn("Machine is not compatible with mt8173-cpufreq\n");
603 err = platform_driver_register(&mt8173_cpufreq_platdrv);
608 * Since there's no place to hold device registration code and no
609 * device tree based way to match cpufreq driver yet, both the driver
610 * and the device registration codes are put here to handle defer
613 pdev = platform_device_register_simple("mt8173-cpufreq", -1, NULL, 0);
615 pr_err("failed to register mtk-cpufreq platform device\n");
616 return PTR_ERR(pdev);
621 device_initcall(mt8173_cpufreq_driver_init);