1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 Linaro Ltd.
4 * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
9 #include <linux/cpufreq.h>
10 #include <linux/cpumask.h>
11 #include <linux/minmax.h>
12 #include <linux/module.h>
14 #include <linux/of_platform.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_opp.h>
17 #include <linux/regulator/consumer.h>
19 struct mtk_cpufreq_platform_data {
25 bool ccifreq_supported;
29 * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS
30 * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
31 * Mediatek SoCs has two voltage inputs, Vproc and Vsram. In some cases the two
32 * voltage inputs need to be controlled under a hardware limitation:
33 * 100mV < Vsram - Vproc < 200mV
35 * When scaling the clock frequency of a CPU clock domain, the clock source
36 * needs to be switched to another stable PLL clock temporarily until
37 * the original PLL becomes stable at target frequency.
39 struct mtk_cpu_dvfs_info {
41 struct device *cpu_dev;
42 struct device *cci_dev;
43 struct regulator *proc_reg;
44 struct regulator *sram_reg;
46 struct clk *inter_clk;
47 struct list_head list_head;
48 int intermediate_voltage;
49 bool need_voltage_tracking;
52 /* Avoid race condition for regulators between notify and policy */
53 struct mutex reg_lock;
54 struct notifier_block opp_nb;
56 unsigned long current_freq;
57 const struct mtk_cpufreq_platform_data *soc_data;
62 static struct platform_device *cpufreq_pdev;
64 static LIST_HEAD(dvfs_info_list);
66 static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu)
68 struct mtk_cpu_dvfs_info *info;
70 list_for_each_entry(info, &dvfs_info_list, list_head) {
71 if (cpumask_test_cpu(cpu, &info->cpus))
78 static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
81 const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
82 struct regulator *proc_reg = info->proc_reg;
83 struct regulator *sram_reg = info->sram_reg;
84 int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
85 int retry = info->vtrack_max;
87 pre_vproc = regulator_get_voltage(proc_reg);
89 dev_err(info->cpu_dev,
90 "invalid Vproc value: %d\n", pre_vproc);
94 pre_vsram = regulator_get_voltage(sram_reg);
96 dev_err(info->cpu_dev, "invalid Vsram value: %d\n", pre_vsram);
100 new_vsram = clamp(new_vproc + soc_data->min_volt_shift,
101 soc_data->sram_min_volt, soc_data->sram_max_volt);
104 if (pre_vproc <= new_vproc) {
105 vsram = clamp(pre_vproc + soc_data->max_volt_shift,
106 soc_data->sram_min_volt, new_vsram);
107 ret = regulator_set_voltage(sram_reg, vsram,
108 soc_data->sram_max_volt);
113 if (vsram == soc_data->sram_max_volt ||
114 new_vsram == soc_data->sram_min_volt)
117 vproc = vsram - soc_data->min_volt_shift;
119 ret = regulator_set_voltage(proc_reg, vproc,
120 soc_data->proc_max_volt);
122 regulator_set_voltage(sram_reg, pre_vsram,
123 soc_data->sram_max_volt);
126 } else if (pre_vproc > new_vproc) {
127 vproc = max(new_vproc,
128 pre_vsram - soc_data->max_volt_shift);
129 ret = regulator_set_voltage(proc_reg, vproc,
130 soc_data->proc_max_volt);
134 if (vproc == new_vproc)
137 vsram = max(new_vsram,
138 vproc + soc_data->min_volt_shift);
140 ret = regulator_set_voltage(sram_reg, vsram,
141 soc_data->sram_max_volt);
143 regulator_set_voltage(proc_reg, pre_vproc,
144 soc_data->proc_max_volt);
153 dev_err(info->cpu_dev,
154 "over loop count, failed to set voltage\n");
157 } while (vproc != new_vproc || vsram != new_vsram);
162 static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
164 const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
167 if (info->need_voltage_tracking)
168 ret = mtk_cpufreq_voltage_tracking(info, vproc);
170 ret = regulator_set_voltage(info->proc_reg, vproc,
171 soc_data->proc_max_volt);
173 info->pre_vproc = vproc;
178 static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info *info)
180 struct device_link *sup_link;
182 if (info->ccifreq_bound)
185 sup_link = device_link_add(info->cpu_dev, info->cci_dev,
186 DL_FLAG_AUTOREMOVE_CONSUMER);
188 dev_err(info->cpu_dev, "cpu%d: sup_link is NULL\n", info->opp_cpu);
192 if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND)
195 info->ccifreq_bound = true;
200 static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
203 struct cpufreq_frequency_table *freq_table = policy->freq_table;
204 struct clk *cpu_clk = policy->clk;
205 struct clk *armpll = clk_get_parent(cpu_clk);
206 struct mtk_cpu_dvfs_info *info = policy->driver_data;
207 struct device *cpu_dev = info->cpu_dev;
208 struct dev_pm_opp *opp;
209 long freq_hz, pre_freq_hz;
210 int vproc, pre_vproc, inter_vproc, target_vproc, ret;
212 inter_vproc = info->intermediate_voltage;
214 pre_freq_hz = clk_get_rate(cpu_clk);
216 mutex_lock(&info->reg_lock);
218 if (unlikely(info->pre_vproc <= 0))
219 pre_vproc = regulator_get_voltage(info->proc_reg);
221 pre_vproc = info->pre_vproc;
224 dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc);
229 freq_hz = freq_table[index].frequency * 1000;
231 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
233 dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n",
234 policy->cpu, freq_hz);
238 vproc = dev_pm_opp_get_voltage(opp);
242 * If MediaTek cci is supported but is not ready, we will use the value
243 * of max(target cpu voltage, booting voltage) to prevent high freqeuncy
246 if (info->soc_data->ccifreq_supported && !is_ccifreq_ready(info))
247 vproc = max(vproc, info->vproc_on_boot);
250 * If the new voltage or the intermediate voltage is higher than the
251 * current voltage, scale up voltage first.
253 target_vproc = max(inter_vproc, vproc);
254 if (pre_vproc <= target_vproc) {
255 ret = mtk_cpufreq_set_voltage(info, target_vproc);
258 "cpu%d: failed to scale up voltage!\n", policy->cpu);
259 mtk_cpufreq_set_voltage(info, pre_vproc);
264 /* Reparent the CPU clock to intermediate clock. */
265 ret = clk_set_parent(cpu_clk, info->inter_clk);
268 "cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
269 mtk_cpufreq_set_voltage(info, pre_vproc);
273 /* Set the original PLL to target rate. */
274 ret = clk_set_rate(armpll, freq_hz);
277 "cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
278 clk_set_parent(cpu_clk, armpll);
279 mtk_cpufreq_set_voltage(info, pre_vproc);
283 /* Set parent of CPU clock back to the original PLL. */
284 ret = clk_set_parent(cpu_clk, armpll);
287 "cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
288 mtk_cpufreq_set_voltage(info, inter_vproc);
293 * If the new voltage is lower than the intermediate voltage or the
294 * original voltage, scale down to the new voltage.
296 if (vproc < inter_vproc || vproc < pre_vproc) {
297 ret = mtk_cpufreq_set_voltage(info, vproc);
300 "cpu%d: failed to scale down voltage!\n", policy->cpu);
301 clk_set_parent(cpu_clk, info->inter_clk);
302 clk_set_rate(armpll, pre_freq_hz);
303 clk_set_parent(cpu_clk, armpll);
308 info->current_freq = freq_hz;
311 mutex_unlock(&info->reg_lock);
316 #define DYNAMIC_POWER "dynamic-power-coefficient"
318 static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
319 unsigned long event, void *data)
321 struct dev_pm_opp *opp = data;
322 struct dev_pm_opp *new_opp;
323 struct mtk_cpu_dvfs_info *info;
324 unsigned long freq, volt;
325 struct cpufreq_policy *policy;
328 info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
330 if (event == OPP_EVENT_ADJUST_VOLTAGE) {
331 freq = dev_pm_opp_get_freq(opp);
333 mutex_lock(&info->reg_lock);
334 if (info->current_freq == freq) {
335 volt = dev_pm_opp_get_voltage(opp);
336 ret = mtk_cpufreq_set_voltage(info, volt);
338 dev_err(info->cpu_dev,
339 "failed to scale voltage: %d\n", ret);
341 mutex_unlock(&info->reg_lock);
342 } else if (event == OPP_EVENT_DISABLE) {
343 freq = dev_pm_opp_get_freq(opp);
345 /* case of current opp item is disabled */
346 if (info->current_freq == freq) {
348 new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev,
350 if (IS_ERR(new_opp)) {
351 dev_err(info->cpu_dev,
352 "all opp items are disabled\n");
353 ret = PTR_ERR(new_opp);
354 return notifier_from_errno(ret);
357 dev_pm_opp_put(new_opp);
358 policy = cpufreq_cpu_get(info->opp_cpu);
360 cpufreq_driver_target(policy, freq / 1000,
362 cpufreq_cpu_put(policy);
367 return notifier_from_errno(ret);
370 static struct device *of_get_cci(struct device *cpu_dev)
372 struct device_node *np;
373 struct platform_device *pdev;
375 np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0);
376 if (IS_ERR_OR_NULL(np))
379 pdev = of_find_device_by_node(np);
381 if (IS_ERR_OR_NULL(pdev))
387 static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
389 struct device *cpu_dev;
390 struct dev_pm_opp *opp;
394 cpu_dev = get_cpu_device(cpu);
396 dev_err(cpu_dev, "failed to get cpu%d device\n", cpu);
399 info->cpu_dev = cpu_dev;
401 info->ccifreq_bound = false;
402 if (info->soc_data->ccifreq_supported) {
403 info->cci_dev = of_get_cci(info->cpu_dev);
404 if (IS_ERR_OR_NULL(info->cci_dev)) {
405 ret = PTR_ERR(info->cci_dev);
406 dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu);
411 info->cpu_clk = clk_get(cpu_dev, "cpu");
412 if (IS_ERR(info->cpu_clk)) {
413 ret = PTR_ERR(info->cpu_clk);
414 return dev_err_probe(cpu_dev, ret,
415 "cpu%d: failed to get cpu clk\n", cpu);
418 info->inter_clk = clk_get(cpu_dev, "intermediate");
419 if (IS_ERR(info->inter_clk)) {
420 ret = PTR_ERR(info->inter_clk);
421 dev_err_probe(cpu_dev, ret,
422 "cpu%d: failed to get intermediate clk\n", cpu);
423 goto out_free_resources;
426 info->proc_reg = regulator_get_optional(cpu_dev, "proc");
427 if (IS_ERR(info->proc_reg)) {
428 ret = PTR_ERR(info->proc_reg);
429 dev_err_probe(cpu_dev, ret,
430 "cpu%d: failed to get proc regulator\n", cpu);
431 goto out_free_resources;
434 ret = regulator_enable(info->proc_reg);
436 dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu);
437 goto out_free_resources;
440 /* Both presence and absence of sram regulator are valid cases. */
441 info->sram_reg = regulator_get_optional(cpu_dev, "sram");
442 if (IS_ERR(info->sram_reg)) {
443 ret = PTR_ERR(info->sram_reg);
444 if (ret == -EPROBE_DEFER)
445 goto out_free_resources;
447 info->sram_reg = NULL;
449 ret = regulator_enable(info->sram_reg);
451 dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu);
452 goto out_free_resources;
456 /* Get OPP-sharing information from "operating-points-v2" bindings */
457 ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus);
460 "cpu%d: failed to get OPP-sharing information\n", cpu);
461 goto out_free_resources;
464 ret = dev_pm_opp_of_cpumask_add_table(&info->cpus);
466 dev_warn(cpu_dev, "cpu%d: no OPP table\n", cpu);
467 goto out_free_resources;
470 ret = clk_prepare_enable(info->cpu_clk);
472 goto out_free_opp_table;
474 ret = clk_prepare_enable(info->inter_clk);
476 goto out_disable_mux_clock;
478 if (info->soc_data->ccifreq_supported) {
479 info->vproc_on_boot = regulator_get_voltage(info->proc_reg);
480 if (info->vproc_on_boot < 0) {
481 dev_err(info->cpu_dev,
482 "invalid Vproc value: %d\n", info->vproc_on_boot);
483 goto out_disable_inter_clock;
487 /* Search a safe voltage for intermediate frequency. */
488 rate = clk_get_rate(info->inter_clk);
489 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
491 dev_err(cpu_dev, "cpu%d: failed to get intermediate opp\n", cpu);
493 goto out_disable_inter_clock;
495 info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
498 mutex_init(&info->reg_lock);
499 info->current_freq = clk_get_rate(info->cpu_clk);
502 info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
503 ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
505 dev_err(cpu_dev, "cpu%d: failed to register opp notifier\n", cpu);
506 goto out_disable_inter_clock;
510 * If SRAM regulator is present, software "voltage tracking" is needed
511 * for this CPU power domain.
513 info->need_voltage_tracking = (info->sram_reg != NULL);
516 * We assume min voltage is 0 and tracking target voltage using
517 * min_volt_shift for each iteration.
518 * The vtrack_max is 3 times of expeted iteration count.
520 info->vtrack_max = 3 * DIV_ROUND_UP(max(info->soc_data->sram_max_volt,
521 info->soc_data->proc_max_volt),
522 info->soc_data->min_volt_shift);
526 out_disable_inter_clock:
527 clk_disable_unprepare(info->inter_clk);
529 out_disable_mux_clock:
530 clk_disable_unprepare(info->cpu_clk);
533 dev_pm_opp_of_cpumask_remove_table(&info->cpus);
536 if (regulator_is_enabled(info->proc_reg))
537 regulator_disable(info->proc_reg);
538 if (info->sram_reg && regulator_is_enabled(info->sram_reg))
539 regulator_disable(info->sram_reg);
541 if (!IS_ERR(info->proc_reg))
542 regulator_put(info->proc_reg);
543 if (!IS_ERR(info->sram_reg))
544 regulator_put(info->sram_reg);
545 if (!IS_ERR(info->cpu_clk))
546 clk_put(info->cpu_clk);
547 if (!IS_ERR(info->inter_clk))
548 clk_put(info->inter_clk);
553 static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
555 if (!IS_ERR(info->proc_reg)) {
556 regulator_disable(info->proc_reg);
557 regulator_put(info->proc_reg);
559 if (!IS_ERR(info->sram_reg)) {
560 regulator_disable(info->sram_reg);
561 regulator_put(info->sram_reg);
563 if (!IS_ERR(info->cpu_clk)) {
564 clk_disable_unprepare(info->cpu_clk);
565 clk_put(info->cpu_clk);
567 if (!IS_ERR(info->inter_clk)) {
568 clk_disable_unprepare(info->inter_clk);
569 clk_put(info->inter_clk);
572 dev_pm_opp_of_cpumask_remove_table(&info->cpus);
573 dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
576 static int mtk_cpufreq_init(struct cpufreq_policy *policy)
578 struct mtk_cpu_dvfs_info *info;
579 struct cpufreq_frequency_table *freq_table;
582 info = mtk_cpu_dvfs_info_lookup(policy->cpu);
584 pr_err("dvfs info for cpu%d is not initialized.\n",
589 ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table);
591 dev_err(info->cpu_dev,
592 "failed to init cpufreq table for cpu%d: %d\n",
597 cpumask_copy(policy->cpus, &info->cpus);
598 policy->freq_table = freq_table;
599 policy->driver_data = info;
600 policy->clk = info->cpu_clk;
605 static int mtk_cpufreq_exit(struct cpufreq_policy *policy)
607 struct mtk_cpu_dvfs_info *info = policy->driver_data;
609 dev_pm_opp_free_cpufreq_table(info->cpu_dev, &policy->freq_table);
614 static struct cpufreq_driver mtk_cpufreq_driver = {
615 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
616 CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
617 CPUFREQ_IS_COOLING_DEV,
618 .verify = cpufreq_generic_frequency_table_verify,
619 .target_index = mtk_cpufreq_set_target,
620 .get = cpufreq_generic_get,
621 .init = mtk_cpufreq_init,
622 .exit = mtk_cpufreq_exit,
623 .register_em = cpufreq_register_em_with_opp,
624 .name = "mtk-cpufreq",
625 .attr = cpufreq_generic_attr,
628 static int mtk_cpufreq_probe(struct platform_device *pdev)
630 const struct mtk_cpufreq_platform_data *data;
631 struct mtk_cpu_dvfs_info *info, *tmp;
634 data = dev_get_platdata(&pdev->dev);
637 "failed to get mtk cpufreq platform data\n");
641 for_each_possible_cpu(cpu) {
642 info = mtk_cpu_dvfs_info_lookup(cpu);
646 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
649 goto release_dvfs_info_list;
652 info->soc_data = data;
653 ret = mtk_cpu_dvfs_info_init(info, cpu);
656 "failed to initialize dvfs info for cpu%d\n",
658 goto release_dvfs_info_list;
661 list_add(&info->list_head, &dvfs_info_list);
664 ret = cpufreq_register_driver(&mtk_cpufreq_driver);
666 dev_err(&pdev->dev, "failed to register mtk cpufreq driver\n");
667 goto release_dvfs_info_list;
672 release_dvfs_info_list:
673 list_for_each_entry_safe(info, tmp, &dvfs_info_list, list_head) {
674 mtk_cpu_dvfs_info_release(info);
675 list_del(&info->list_head);
681 static struct platform_driver mtk_cpufreq_platdrv = {
683 .name = "mtk-cpufreq",
685 .probe = mtk_cpufreq_probe,
688 static const struct mtk_cpufreq_platform_data mt2701_platform_data = {
689 .min_volt_shift = 100000,
690 .max_volt_shift = 200000,
691 .proc_max_volt = 1150000,
693 .sram_max_volt = 1150000,
694 .ccifreq_supported = false,
697 static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
698 .min_volt_shift = 100000,
699 .max_volt_shift = 200000,
700 .proc_max_volt = 1150000,
702 .sram_max_volt = 1150000,
703 .ccifreq_supported = true,
706 static const struct mtk_cpufreq_platform_data mt8186_platform_data = {
707 .min_volt_shift = 100000,
708 .max_volt_shift = 250000,
709 .proc_max_volt = 1118750,
710 .sram_min_volt = 850000,
711 .sram_max_volt = 1118750,
712 .ccifreq_supported = true,
715 /* List of machines supported by this driver */
716 static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
717 { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
718 { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
719 { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data },
720 { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data },
721 { .compatible = "mediatek,mt8167", .data = &mt2701_platform_data },
722 { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
723 { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
724 { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
725 { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
726 { .compatible = "mediatek,mt8186", .data = &mt8186_platform_data },
727 { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
728 { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
731 MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines);
733 static int __init mtk_cpufreq_driver_init(void)
735 struct device_node *np;
736 const struct of_device_id *match;
737 const struct mtk_cpufreq_platform_data *data;
740 np = of_find_node_by_path("/");
744 match = of_match_node(mtk_cpufreq_machines, np);
747 pr_debug("Machine is not compatible with mtk-cpufreq\n");
752 err = platform_driver_register(&mtk_cpufreq_platdrv);
757 * Since there's no place to hold device registration code and no
758 * device tree based way to match cpufreq driver yet, both the driver
759 * and the device registration codes are put here to handle defer
762 cpufreq_pdev = platform_device_register_data(NULL, "mtk-cpufreq", -1,
763 data, sizeof(*data));
764 if (IS_ERR(cpufreq_pdev)) {
765 pr_err("failed to register mtk-cpufreq platform device\n");
766 platform_driver_unregister(&mtk_cpufreq_platdrv);
767 return PTR_ERR(cpufreq_pdev);
772 module_init(mtk_cpufreq_driver_init)
774 static void __exit mtk_cpufreq_driver_exit(void)
776 platform_device_unregister(cpufreq_pdev);
777 platform_driver_unregister(&mtk_cpufreq_platdrv);
779 module_exit(mtk_cpufreq_driver_exit)
781 MODULE_DESCRIPTION("MediaTek CPUFreq driver");
782 MODULE_AUTHOR("Pi-Cheng Chen <pi-cheng.chen@linaro.org>");
783 MODULE_LICENSE("GPL v2");