1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel_pstate.c: Native P state management for Intel processors
5 * (C) Copyright 2012 Intel Corporation
6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/kernel.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/module.h>
14 #include <linux/ktime.h>
15 #include <linux/hrtimer.h>
16 #include <linux/tick.h>
17 #include <linux/slab.h>
18 #include <linux/sched/cpufreq.h>
19 #include <linux/list.h>
20 #include <linux/cpu.h>
21 #include <linux/cpufreq.h>
22 #include <linux/sysfs.h>
23 #include <linux/types.h>
25 #include <linux/acpi.h>
26 #include <linux/vmalloc.h>
27 #include <linux/pm_qos.h>
28 #include <trace/events/power.h>
31 #include <asm/div64.h>
33 #include <asm/cpu_device_id.h>
34 #include <asm/cpufeature.h>
35 #include <asm/intel-family.h>
36 #include "../drivers/thermal/intel/thermal_interrupt.h"
38 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
40 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
41 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000
42 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
45 #include <acpi/processor.h>
46 #include <acpi/cppc_acpi.h>
50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
51 #define fp_toint(X) ((X) >> FRAC_BITS)
53 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
60 static inline int32_t mul_fp(int32_t x, int32_t y)
62 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
65 static inline int32_t div_fp(s64 x, s64 y)
67 return div64_s64((int64_t)x << FRAC_BITS, y);
70 static inline int ceiling_fp(int32_t x)
75 mask = (1 << FRAC_BITS) - 1;
81 static inline u64 mul_ext_fp(u64 x, u64 y)
83 return (x * y) >> EXT_FRAC_BITS;
86 static inline u64 div_ext_fp(u64 x, u64 y)
88 return div64_u64(x << EXT_FRAC_BITS, y);
92 * struct sample - Store performance sample
93 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
94 * performance during last sample period
95 * @busy_scaled: Scaled busy value which is used to calculate next
96 * P state. This can be different than core_avg_perf
97 * to account for cpu idle period
98 * @aperf: Difference of actual performance frequency clock count
99 * read from APERF MSR between last and current sample
100 * @mperf: Difference of maximum performance frequency clock count
101 * read from MPERF MSR between last and current sample
102 * @tsc: Difference of time stamp counter between last and
104 * @time: Current time from scheduler
106 * This structure is used in the cpudata structure to store performance sample
107 * data for choosing next P State.
110 int32_t core_avg_perf;
119 * struct pstate_data - Store P state data
120 * @current_pstate: Current requested P state
121 * @min_pstate: Min P state possible for this platform
122 * @max_pstate: Max P state possible for this platform
123 * @max_pstate_physical:This is physical Max P state for a processor
124 * This can be higher than the max_pstate which can
125 * be limited by platform thermal design power limits
126 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor
127 * @scaling: Scaling factor between performance and frequency
128 * @turbo_pstate: Max Turbo P state possible for this platform
129 * @min_freq: @min_pstate frequency in cpufreq units
130 * @max_freq: @max_pstate frequency in cpufreq units
131 * @turbo_freq: @turbo_pstate frequency in cpufreq units
133 * Stores the per cpu model P state limits and current P state.
139 int max_pstate_physical;
140 int perf_ctl_scaling;
143 unsigned int min_freq;
144 unsigned int max_freq;
145 unsigned int turbo_freq;
149 * struct vid_data - Stores voltage information data
150 * @min: VID data for this platform corresponding to
152 * @max: VID data corresponding to the highest P State.
153 * @turbo: VID data for turbo P state
154 * @ratio: Ratio of (vid max - vid min) /
155 * (max P state - Min P State)
157 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
158 * This data is used in Atom platforms, where in addition to target P state,
159 * the voltage data needs to be specified to select next P State.
169 * struct global_params - Global parameters, mostly tunable via sysfs.
170 * @no_turbo: Whether or not to use turbo P-states.
171 * @turbo_disabled: Whether or not turbo P-states are available at all,
172 * based on the MSR_IA32_MISC_ENABLE value and whether or
173 * not the maximum reported turbo P-state is different from
174 * the maximum reported non-turbo one.
175 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq.
176 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
178 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
181 struct global_params {
184 bool turbo_disabled_mf;
190 * struct cpudata - Per CPU instance data storage
191 * @cpu: CPU number for this instance data
192 * @policy: CPUFreq policy value
193 * @update_util: CPUFreq utility callback information
194 * @update_util_set: CPUFreq utility callback is set
195 * @iowait_boost: iowait-related boost fraction
196 * @last_update: Time of the last update.
197 * @pstate: Stores P state limits for this CPU
198 * @vid: Stores VID limits for this CPU
199 * @last_sample_time: Last Sample time
200 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference
201 * @prev_aperf: Last APERF value read from APERF MSR
202 * @prev_mperf: Last MPERF value read from MPERF MSR
203 * @prev_tsc: Last timestamp counter (TSC) value
204 * @prev_cummulative_iowait: IO Wait time difference from last and
206 * @sample: Storage for storing last Sample data
207 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
208 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
209 * @acpi_perf_data: Stores ACPI perf information read from _PSS
210 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
211 * @epp_powersave: Last saved HWP energy performance preference
212 * (EPP) or energy performance bias (EPB),
213 * when policy switched to performance
214 * @epp_policy: Last saved policy used to set EPP/EPB
215 * @epp_default: Power on default HWP energy performance
217 * @epp_cached Cached HWP energy-performance preference value
218 * @hwp_req_cached: Cached value of the last HWP Request MSR
219 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
220 * @last_io_update: Last time when IO wake flag was set
221 * @sched_flags: Store scheduler flags for possible cross CPU update
222 * @hwp_boost_min: Last HWP boosted min performance
223 * @suspended: Whether or not the driver has been suspended.
224 * @hwp_notify_work: workqueue for HWP notifications.
226 * This structure stores per CPU instance data for all CPUs.
232 struct update_util_data update_util;
233 bool update_util_set;
235 struct pstate_data pstate;
239 u64 last_sample_time;
240 u64 aperf_mperf_shift;
244 u64 prev_cummulative_iowait;
245 struct sample sample;
246 int32_t min_perf_ratio;
247 int32_t max_perf_ratio;
249 struct acpi_processor_performance acpi_perf_data;
250 bool valid_pss_table;
252 unsigned int iowait_boost;
260 unsigned int sched_flags;
263 struct delayed_work hwp_notify_work;
266 static struct cpudata **all_cpu_data;
269 * struct pstate_funcs - Per CPU model specific callbacks
270 * @get_max: Callback to get maximum non turbo effective P state
271 * @get_max_physical: Callback to get maximum non turbo physical P state
272 * @get_min: Callback to get minimum P state
273 * @get_turbo: Callback to get turbo P state
274 * @get_scaling: Callback to get frequency scaling factor
275 * @get_cpu_scaling: Get frequency scaling factor for a given cpu
276 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
277 * @get_val: Callback to convert P state to actual MSR write value
278 * @get_vid: Callback to get VID data for Atom platforms
280 * Core and Atom CPU models have different way to get P State limits. This
281 * structure is used to store those callbacks.
283 struct pstate_funcs {
284 int (*get_max)(int cpu);
285 int (*get_max_physical)(int cpu);
286 int (*get_min)(int cpu);
287 int (*get_turbo)(int cpu);
288 int (*get_scaling)(void);
289 int (*get_cpu_scaling)(int cpu);
290 int (*get_aperf_mperf_shift)(void);
291 u64 (*get_val)(struct cpudata*, int pstate);
292 void (*get_vid)(struct cpudata *);
295 static struct pstate_funcs pstate_funcs __read_mostly;
297 static int hwp_active __read_mostly;
298 static int hwp_mode_bdw __read_mostly;
299 static bool per_cpu_limits __read_mostly;
300 static bool hwp_boost __read_mostly;
301 static bool hwp_forced __read_mostly;
303 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
305 #define HYBRID_SCALING_FACTOR 78741
306 #define HYBRID_SCALING_FACTOR_MTL 80000
308 static int hybrid_scaling_factor = HYBRID_SCALING_FACTOR;
310 static inline int core_get_scaling(void)
316 static bool acpi_ppc;
319 static struct global_params global;
321 static DEFINE_MUTEX(intel_pstate_driver_lock);
322 static DEFINE_MUTEX(intel_pstate_limits_lock);
326 static bool intel_pstate_acpi_pm_profile_server(void)
328 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
329 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
335 static bool intel_pstate_get_ppc_enable_status(void)
337 if (intel_pstate_acpi_pm_profile_server())
343 #ifdef CONFIG_ACPI_CPPC_LIB
345 /* The work item is needed to avoid CPU hotplug locking issues */
346 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
348 sched_set_itmt_support();
351 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
353 #define CPPC_MAX_PERF U8_MAX
355 static void intel_pstate_set_itmt_prio(int cpu)
357 struct cppc_perf_caps cppc_perf;
358 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
361 ret = cppc_get_perf_caps(cpu, &cppc_perf);
366 * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff.
367 * In this case we can't use CPPC.highest_perf to enable ITMT.
368 * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide.
370 if (cppc_perf.highest_perf == CPPC_MAX_PERF)
371 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
374 * The priorities can be set regardless of whether or not
375 * sched_set_itmt_support(true) has been called and it is valid to
376 * update them at any time after it has been called.
378 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
380 if (max_highest_perf <= min_highest_perf) {
381 if (cppc_perf.highest_perf > max_highest_perf)
382 max_highest_perf = cppc_perf.highest_perf;
384 if (cppc_perf.highest_perf < min_highest_perf)
385 min_highest_perf = cppc_perf.highest_perf;
387 if (max_highest_perf > min_highest_perf) {
389 * This code can be run during CPU online under the
390 * CPU hotplug locks, so sched_set_itmt_support()
391 * cannot be called from here. Queue up a work item
394 schedule_work(&sched_itmt_work);
399 static int intel_pstate_get_cppc_guaranteed(int cpu)
401 struct cppc_perf_caps cppc_perf;
404 ret = cppc_get_perf_caps(cpu, &cppc_perf);
408 if (cppc_perf.guaranteed_perf)
409 return cppc_perf.guaranteed_perf;
411 return cppc_perf.nominal_perf;
414 static int intel_pstate_cppc_get_scaling(int cpu)
416 struct cppc_perf_caps cppc_perf;
419 ret = cppc_get_perf_caps(cpu, &cppc_perf);
422 * If the nominal frequency and the nominal performance are not
423 * zero and the ratio between them is not 100, return the hybrid
426 if (!ret && cppc_perf.nominal_perf && cppc_perf.nominal_freq &&
427 cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq)
428 return hybrid_scaling_factor;
430 return core_get_scaling();
433 #else /* CONFIG_ACPI_CPPC_LIB */
434 static inline void intel_pstate_set_itmt_prio(int cpu)
437 #endif /* CONFIG_ACPI_CPPC_LIB */
439 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
446 intel_pstate_set_itmt_prio(policy->cpu);
450 if (!intel_pstate_get_ppc_enable_status())
453 cpu = all_cpu_data[policy->cpu];
455 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
461 * Check if the control value in _PSS is for PERF_CTL MSR, which should
462 * guarantee that the states returned by it map to the states in our
465 if (cpu->acpi_perf_data.control_register.space_id !=
466 ACPI_ADR_SPACE_FIXED_HARDWARE)
470 * If there is only one entry _PSS, simply ignore _PSS and continue as
471 * usual without taking _PSS into account
473 if (cpu->acpi_perf_data.state_count < 2)
476 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
477 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
478 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
479 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
480 (u32) cpu->acpi_perf_data.states[i].core_frequency,
481 (u32) cpu->acpi_perf_data.states[i].power,
482 (u32) cpu->acpi_perf_data.states[i].control);
485 cpu->valid_pss_table = true;
486 pr_debug("_PPC limits will be enforced\n");
491 cpu->valid_pss_table = false;
492 acpi_processor_unregister_performance(policy->cpu);
495 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
499 cpu = all_cpu_data[policy->cpu];
500 if (!cpu->valid_pss_table)
503 acpi_processor_unregister_performance(policy->cpu);
505 #else /* CONFIG_ACPI */
506 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
510 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
514 static inline bool intel_pstate_acpi_pm_profile_server(void)
518 #endif /* CONFIG_ACPI */
520 #ifndef CONFIG_ACPI_CPPC_LIB
521 static inline int intel_pstate_get_cppc_guaranteed(int cpu)
526 static int intel_pstate_cppc_get_scaling(int cpu)
528 return core_get_scaling();
530 #endif /* CONFIG_ACPI_CPPC_LIB */
532 static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq,
533 unsigned int relation)
535 if (freq == cpu->pstate.turbo_freq)
536 return cpu->pstate.turbo_pstate;
538 if (freq == cpu->pstate.max_freq)
539 return cpu->pstate.max_pstate;
542 case CPUFREQ_RELATION_H:
543 return freq / cpu->pstate.scaling;
544 case CPUFREQ_RELATION_C:
545 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling);
548 return DIV_ROUND_UP(freq, cpu->pstate.scaling);
551 static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq)
553 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L);
557 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
560 * On hybrid processors, HWP may expose more performance levels than there are
561 * P-states accessible through the PERF_CTL interface. If that happens, the
562 * scaling factor between HWP performance levels and CPU frequency will be less
563 * than the scaling factor between P-state values and CPU frequency.
565 * In that case, adjust the CPU parameters used in computations accordingly.
567 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
569 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
570 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
571 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu);
572 int scaling = cpu->pstate.scaling;
575 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
576 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo);
577 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling);
578 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
579 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
580 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
582 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
584 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
587 freq = perf_ctl_max_phys * perf_ctl_scaling;
588 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq);
590 freq = cpu->pstate.min_pstate * perf_ctl_scaling;
591 cpu->pstate.min_freq = freq;
593 * Cast the min P-state value retrieved via pstate_funcs.get_min() to
594 * the effective range of HWP performance levels.
596 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq);
599 static inline void update_turbo_state(void)
603 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
604 global.turbo_disabled = misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE;
607 static int min_perf_pct_min(void)
609 struct cpudata *cpu = all_cpu_data[0];
610 int turbo_pstate = cpu->pstate.turbo_pstate;
612 return turbo_pstate ?
613 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
616 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
621 if (!boot_cpu_has(X86_FEATURE_EPB))
624 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
628 return (s16)(epb & 0x0f);
631 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
635 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
637 * When hwp_req_data is 0, means that caller didn't read
638 * MSR_HWP_REQUEST, so need to read and get EPP.
641 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
646 epp = (hwp_req_data >> 24) & 0xff;
648 /* When there is no EPP present, HWP uses EPB settings */
649 epp = intel_pstate_get_epb(cpu_data);
655 static int intel_pstate_set_epb(int cpu, s16 pref)
660 if (!boot_cpu_has(X86_FEATURE_EPB))
663 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
667 epb = (epb & ~0x0f) | pref;
668 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
674 * EPP/EPB display strings corresponding to EPP index in the
675 * energy_perf_strings[]
677 *-------------------------------------
680 * 2 balance_performance
685 enum energy_perf_value_index {
686 EPP_INDEX_DEFAULT = 0,
687 EPP_INDEX_PERFORMANCE,
688 EPP_INDEX_BALANCE_PERFORMANCE,
689 EPP_INDEX_BALANCE_POWERSAVE,
693 static const char * const energy_perf_strings[] = {
694 [EPP_INDEX_DEFAULT] = "default",
695 [EPP_INDEX_PERFORMANCE] = "performance",
696 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
697 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
698 [EPP_INDEX_POWERSAVE] = "power",
701 static unsigned int epp_values[] = {
702 [EPP_INDEX_DEFAULT] = 0, /* Unused index */
703 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
704 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
705 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
706 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
709 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
715 epp = intel_pstate_get_epp(cpu_data, 0);
719 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
720 if (epp == epp_values[EPP_INDEX_PERFORMANCE])
721 return EPP_INDEX_PERFORMANCE;
722 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
723 return EPP_INDEX_BALANCE_PERFORMANCE;
724 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
725 return EPP_INDEX_BALANCE_POWERSAVE;
726 if (epp == epp_values[EPP_INDEX_POWERSAVE])
727 return EPP_INDEX_POWERSAVE;
730 } else if (boot_cpu_has(X86_FEATURE_EPB)) {
733 * 0x00-0x03 : Performance
734 * 0x04-0x07 : Balance performance
735 * 0x08-0x0B : Balance power
737 * The EPB is a 4 bit value, but our ranges restrict the
738 * value which can be set. Here only using top two bits
741 index = (epp >> 2) + 1;
747 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
752 * Use the cached HWP Request MSR value, because in the active mode the
753 * register itself may be updated by intel_pstate_hwp_boost_up() or
754 * intel_pstate_hwp_boost_down() at any time.
756 u64 value = READ_ONCE(cpu->hwp_req_cached);
758 value &= ~GENMASK_ULL(31, 24);
759 value |= (u64)epp << 24;
761 * The only other updater of hwp_req_cached in the active mode,
762 * intel_pstate_hwp_set(), is called under the same lock as this
763 * function, so it cannot run in parallel with the update below.
765 WRITE_ONCE(cpu->hwp_req_cached, value);
766 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
768 cpu->epp_cached = epp;
773 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
774 int pref_index, bool use_raw,
781 epp = cpu_data->epp_default;
783 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
786 else if (epp == -EINVAL)
787 epp = epp_values[pref_index];
790 * To avoid confusion, refuse to set EPP to any values different
791 * from 0 (performance) if the current policy is "performance",
792 * because those values would be overridden.
794 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
797 ret = intel_pstate_set_epp(cpu_data, epp);
800 epp = (pref_index - 1) << 2;
801 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
807 static ssize_t show_energy_performance_available_preferences(
808 struct cpufreq_policy *policy, char *buf)
813 while (energy_perf_strings[i] != NULL)
814 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
816 ret += sprintf(&buf[ret], "\n");
821 cpufreq_freq_attr_ro(energy_performance_available_preferences);
823 static struct cpufreq_driver intel_pstate;
825 static ssize_t store_energy_performance_preference(
826 struct cpufreq_policy *policy, const char *buf, size_t count)
828 struct cpudata *cpu = all_cpu_data[policy->cpu];
829 char str_preference[21];
834 ret = sscanf(buf, "%20s", str_preference);
838 ret = match_string(energy_perf_strings, -1, str_preference);
840 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
843 ret = kstrtouint(buf, 10, &epp);
854 * This function runs with the policy R/W semaphore held, which
855 * guarantees that the driver pointer will not change while it is
858 if (!intel_pstate_driver)
861 mutex_lock(&intel_pstate_limits_lock);
863 if (intel_pstate_driver == &intel_pstate) {
864 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
867 * In the passive mode the governor needs to be stopped on the
868 * target CPU before the EPP update and restarted after it,
869 * which is super-heavy-weight, so make sure it is worth doing
873 epp = ret ? epp_values[ret] : cpu->epp_default;
875 if (cpu->epp_cached != epp) {
878 cpufreq_stop_governor(policy);
879 ret = intel_pstate_set_epp(cpu, epp);
880 err = cpufreq_start_governor(policy);
888 mutex_unlock(&intel_pstate_limits_lock);
893 static ssize_t show_energy_performance_preference(
894 struct cpufreq_policy *policy, char *buf)
896 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
897 int preference, raw_epp;
899 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
904 return sprintf(buf, "%d\n", raw_epp);
906 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
909 cpufreq_freq_attr_rw(energy_performance_preference);
911 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
913 struct cpudata *cpu = all_cpu_data[policy->cpu];
916 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu);
920 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
921 ratio = HWP_GUARANTEED_PERF(cap);
924 freq = ratio * cpu->pstate.scaling;
925 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
926 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
928 return sprintf(buf, "%d\n", freq);
931 cpufreq_freq_attr_ro(base_frequency);
933 static struct freq_attr *hwp_cpufreq_attrs[] = {
934 &energy_performance_preference,
935 &energy_performance_available_preferences,
940 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
944 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
945 WRITE_ONCE(cpu->hwp_cap_cached, cap);
946 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
947 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
950 static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
952 int scaling = cpu->pstate.scaling;
954 __intel_pstate_get_hwp_cap(cpu);
956 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
957 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
958 if (scaling != cpu->pstate.perf_ctl_scaling) {
959 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
961 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
963 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
968 static void intel_pstate_hwp_set(unsigned int cpu)
970 struct cpudata *cpu_data = all_cpu_data[cpu];
975 max = cpu_data->max_perf_ratio;
976 min = cpu_data->min_perf_ratio;
978 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
981 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
983 value &= ~HWP_MIN_PERF(~0L);
984 value |= HWP_MIN_PERF(min);
986 value &= ~HWP_MAX_PERF(~0L);
987 value |= HWP_MAX_PERF(max);
989 if (cpu_data->epp_policy == cpu_data->policy)
992 cpu_data->epp_policy = cpu_data->policy;
994 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
995 epp = intel_pstate_get_epp(cpu_data, value);
996 cpu_data->epp_powersave = epp;
997 /* If EPP read was failed, then don't try to write */
1003 /* skip setting EPP, when saved value is invalid */
1004 if (cpu_data->epp_powersave < 0)
1008 * No need to restore EPP when it is not zero. This
1010 * - Policy is not changed
1011 * - user has manually changed
1012 * - Error reading EPB
1014 epp = intel_pstate_get_epp(cpu_data, value);
1018 epp = cpu_data->epp_powersave;
1020 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1021 value &= ~GENMASK_ULL(31, 24);
1022 value |= (u64)epp << 24;
1024 intel_pstate_set_epb(cpu, epp);
1027 WRITE_ONCE(cpu_data->hwp_req_cached, value);
1028 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
1031 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
1033 static void intel_pstate_hwp_offline(struct cpudata *cpu)
1035 u64 value = READ_ONCE(cpu->hwp_req_cached);
1038 intel_pstate_disable_hwp_interrupt(cpu);
1040 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1042 * In case the EPP has been set to "performance" by the
1043 * active mode "performance" scaling algorithm, replace that
1044 * temporary value with the cached EPP one.
1046 value &= ~GENMASK_ULL(31, 24);
1047 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
1049 * However, make sure that EPP will be set to "performance" when
1050 * the CPU is brought back online again and the "performance"
1051 * scaling algorithm is still in effect.
1053 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
1057 * Clear the desired perf field in the cached HWP request value to
1058 * prevent nonzero desired values from being leaked into the active
1061 value &= ~HWP_DESIRED_PERF(~0L);
1062 WRITE_ONCE(cpu->hwp_req_cached, value);
1064 value &= ~GENMASK_ULL(31, 0);
1065 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1067 /* Set hwp_max = hwp_min */
1068 value |= HWP_MAX_PERF(min_perf);
1069 value |= HWP_MIN_PERF(min_perf);
1071 /* Set EPP to min */
1072 if (boot_cpu_has(X86_FEATURE_HWP_EPP))
1073 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1075 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
1078 #define POWER_CTL_EE_ENABLE 1
1079 #define POWER_CTL_EE_DISABLE 2
1081 static int power_ctl_ee_state;
1083 static void set_power_ctl_ee_state(bool input)
1087 mutex_lock(&intel_pstate_driver_lock);
1088 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1090 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1091 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1093 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1094 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1096 wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
1097 mutex_unlock(&intel_pstate_driver_lock);
1100 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1102 static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1104 intel_pstate_hwp_enable(cpu);
1105 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1108 static int intel_pstate_suspend(struct cpufreq_policy *policy)
1110 struct cpudata *cpu = all_cpu_data[policy->cpu];
1112 pr_debug("CPU %d suspending\n", cpu->cpu);
1114 cpu->suspended = true;
1116 /* disable HWP interrupt and cancel any pending work */
1117 intel_pstate_disable_hwp_interrupt(cpu);
1122 static int intel_pstate_resume(struct cpufreq_policy *policy)
1124 struct cpudata *cpu = all_cpu_data[policy->cpu];
1126 pr_debug("CPU %d resuming\n", cpu->cpu);
1128 /* Only restore if the system default is changed */
1129 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1130 set_power_ctl_ee_state(true);
1131 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1132 set_power_ctl_ee_state(false);
1134 if (cpu->suspended && hwp_active) {
1135 mutex_lock(&intel_pstate_limits_lock);
1137 /* Re-enable HWP, because "online" has not done that. */
1138 intel_pstate_hwp_reenable(cpu);
1140 mutex_unlock(&intel_pstate_limits_lock);
1143 cpu->suspended = false;
1148 static void intel_pstate_update_policies(void)
1152 for_each_possible_cpu(cpu)
1153 cpufreq_update_policy(cpu);
1156 static void __intel_pstate_update_max_freq(struct cpudata *cpudata,
1157 struct cpufreq_policy *policy)
1159 policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
1160 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1161 refresh_frequency_limits(policy);
1164 static void intel_pstate_update_max_freq(unsigned int cpu)
1166 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1171 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy);
1173 cpufreq_cpu_release(policy);
1176 static void intel_pstate_update_limits(unsigned int cpu)
1178 mutex_lock(&intel_pstate_driver_lock);
1180 update_turbo_state();
1182 * If turbo has been turned on or off globally, policy limits for
1183 * all CPUs need to be updated to reflect that.
1185 if (global.turbo_disabled_mf != global.turbo_disabled) {
1186 global.turbo_disabled_mf = global.turbo_disabled;
1187 arch_set_max_freq_ratio(global.turbo_disabled);
1188 for_each_possible_cpu(cpu)
1189 intel_pstate_update_max_freq(cpu);
1191 cpufreq_update_policy(cpu);
1194 mutex_unlock(&intel_pstate_driver_lock);
1197 /************************** sysfs begin ************************/
1198 #define show_one(file_name, object) \
1199 static ssize_t show_##file_name \
1200 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \
1202 return sprintf(buf, "%u\n", global.object); \
1205 static ssize_t intel_pstate_show_status(char *buf);
1206 static int intel_pstate_update_status(const char *buf, size_t size);
1208 static ssize_t show_status(struct kobject *kobj,
1209 struct kobj_attribute *attr, char *buf)
1213 mutex_lock(&intel_pstate_driver_lock);
1214 ret = intel_pstate_show_status(buf);
1215 mutex_unlock(&intel_pstate_driver_lock);
1220 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1221 const char *buf, size_t count)
1223 char *p = memchr(buf, '\n', count);
1226 mutex_lock(&intel_pstate_driver_lock);
1227 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1228 mutex_unlock(&intel_pstate_driver_lock);
1230 return ret < 0 ? ret : count;
1233 static ssize_t show_turbo_pct(struct kobject *kobj,
1234 struct kobj_attribute *attr, char *buf)
1236 struct cpudata *cpu;
1237 int total, no_turbo, turbo_pct;
1240 mutex_lock(&intel_pstate_driver_lock);
1242 if (!intel_pstate_driver) {
1243 mutex_unlock(&intel_pstate_driver_lock);
1247 cpu = all_cpu_data[0];
1249 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1250 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1251 turbo_fp = div_fp(no_turbo, total);
1252 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1254 mutex_unlock(&intel_pstate_driver_lock);
1256 return sprintf(buf, "%u\n", turbo_pct);
1259 static ssize_t show_num_pstates(struct kobject *kobj,
1260 struct kobj_attribute *attr, char *buf)
1262 struct cpudata *cpu;
1265 mutex_lock(&intel_pstate_driver_lock);
1267 if (!intel_pstate_driver) {
1268 mutex_unlock(&intel_pstate_driver_lock);
1272 cpu = all_cpu_data[0];
1273 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1275 mutex_unlock(&intel_pstate_driver_lock);
1277 return sprintf(buf, "%u\n", total);
1280 static ssize_t show_no_turbo(struct kobject *kobj,
1281 struct kobj_attribute *attr, char *buf)
1285 mutex_lock(&intel_pstate_driver_lock);
1287 if (!intel_pstate_driver) {
1288 mutex_unlock(&intel_pstate_driver_lock);
1292 update_turbo_state();
1293 if (global.turbo_disabled)
1294 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1296 ret = sprintf(buf, "%u\n", global.no_turbo);
1298 mutex_unlock(&intel_pstate_driver_lock);
1303 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1304 const char *buf, size_t count)
1309 ret = sscanf(buf, "%u", &input);
1313 mutex_lock(&intel_pstate_driver_lock);
1315 if (!intel_pstate_driver) {
1316 mutex_unlock(&intel_pstate_driver_lock);
1320 mutex_lock(&intel_pstate_limits_lock);
1322 update_turbo_state();
1323 if (global.turbo_disabled) {
1324 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
1325 mutex_unlock(&intel_pstate_limits_lock);
1326 mutex_unlock(&intel_pstate_driver_lock);
1330 global.no_turbo = clamp_t(int, input, 0, 1);
1332 if (global.no_turbo) {
1333 struct cpudata *cpu = all_cpu_data[0];
1334 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1336 /* Squash the global minimum into the permitted range. */
1337 if (global.min_perf_pct > pct)
1338 global.min_perf_pct = pct;
1341 mutex_unlock(&intel_pstate_limits_lock);
1343 intel_pstate_update_policies();
1344 arch_set_max_freq_ratio(global.no_turbo);
1346 mutex_unlock(&intel_pstate_driver_lock);
1351 static void update_qos_request(enum freq_qos_req_type type)
1353 struct freq_qos_request *req;
1354 struct cpufreq_policy *policy;
1357 for_each_possible_cpu(i) {
1358 struct cpudata *cpu = all_cpu_data[i];
1359 unsigned int freq, perf_pct;
1361 policy = cpufreq_cpu_get(i);
1365 req = policy->driver_data;
1366 cpufreq_cpu_put(policy);
1372 intel_pstate_get_hwp_cap(cpu);
1374 if (type == FREQ_QOS_MIN) {
1375 perf_pct = global.min_perf_pct;
1378 perf_pct = global.max_perf_pct;
1381 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100);
1383 if (freq_qos_update_request(req, freq) < 0)
1384 pr_warn("Failed to update freq constraint: CPU%d\n", i);
1388 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1389 const char *buf, size_t count)
1394 ret = sscanf(buf, "%u", &input);
1398 mutex_lock(&intel_pstate_driver_lock);
1400 if (!intel_pstate_driver) {
1401 mutex_unlock(&intel_pstate_driver_lock);
1405 mutex_lock(&intel_pstate_limits_lock);
1407 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1409 mutex_unlock(&intel_pstate_limits_lock);
1411 if (intel_pstate_driver == &intel_pstate)
1412 intel_pstate_update_policies();
1414 update_qos_request(FREQ_QOS_MAX);
1416 mutex_unlock(&intel_pstate_driver_lock);
1421 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1422 const char *buf, size_t count)
1427 ret = sscanf(buf, "%u", &input);
1431 mutex_lock(&intel_pstate_driver_lock);
1433 if (!intel_pstate_driver) {
1434 mutex_unlock(&intel_pstate_driver_lock);
1438 mutex_lock(&intel_pstate_limits_lock);
1440 global.min_perf_pct = clamp_t(int, input,
1441 min_perf_pct_min(), global.max_perf_pct);
1443 mutex_unlock(&intel_pstate_limits_lock);
1445 if (intel_pstate_driver == &intel_pstate)
1446 intel_pstate_update_policies();
1448 update_qos_request(FREQ_QOS_MIN);
1450 mutex_unlock(&intel_pstate_driver_lock);
1455 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1456 struct kobj_attribute *attr, char *buf)
1458 return sprintf(buf, "%u\n", hwp_boost);
1461 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1462 struct kobj_attribute *b,
1463 const char *buf, size_t count)
1468 ret = kstrtouint(buf, 10, &input);
1472 mutex_lock(&intel_pstate_driver_lock);
1473 hwp_boost = !!input;
1474 intel_pstate_update_policies();
1475 mutex_unlock(&intel_pstate_driver_lock);
1480 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1486 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1487 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1488 return sprintf(buf, "%d\n", !enable);
1491 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1492 const char *buf, size_t count)
1497 ret = kstrtobool(buf, &input);
1501 set_power_ctl_ee_state(input);
1506 show_one(max_perf_pct, max_perf_pct);
1507 show_one(min_perf_pct, min_perf_pct);
1509 define_one_global_rw(status);
1510 define_one_global_rw(no_turbo);
1511 define_one_global_rw(max_perf_pct);
1512 define_one_global_rw(min_perf_pct);
1513 define_one_global_ro(turbo_pct);
1514 define_one_global_ro(num_pstates);
1515 define_one_global_rw(hwp_dynamic_boost);
1516 define_one_global_rw(energy_efficiency);
1518 static struct attribute *intel_pstate_attributes[] = {
1524 static const struct attribute_group intel_pstate_attr_group = {
1525 .attrs = intel_pstate_attributes,
1528 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1530 static struct kobject *intel_pstate_kobject;
1532 static void __init intel_pstate_sysfs_expose_params(void)
1534 struct device *dev_root = bus_get_dev_root(&cpu_subsys);
1538 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj);
1539 put_device(dev_root);
1541 if (WARN_ON(!intel_pstate_kobject))
1544 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1548 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1549 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr);
1552 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr);
1557 * If per cpu limits are enforced there are no global limits, so
1558 * return without creating max/min_perf_pct attributes
1563 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1566 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1569 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1570 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1575 static void __init intel_pstate_sysfs_remove(void)
1577 if (!intel_pstate_kobject)
1580 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1582 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1583 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr);
1584 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr);
1587 if (!per_cpu_limits) {
1588 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1589 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1591 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1592 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1595 kobject_put(intel_pstate_kobject);
1598 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1605 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1609 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1614 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1617 /************************** sysfs end ************************/
1619 static void intel_pstate_notify_work(struct work_struct *work)
1621 struct cpudata *cpudata =
1622 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
1623 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu);
1626 intel_pstate_get_hwp_cap(cpudata);
1627 __intel_pstate_update_max_freq(cpudata, policy);
1629 cpufreq_cpu_release(policy);
1632 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1635 static DEFINE_SPINLOCK(hwp_notify_lock);
1636 static cpumask_t hwp_intr_enable_mask;
1638 void notify_hwp_interrupt(void)
1640 unsigned int this_cpu = smp_processor_id();
1641 struct cpudata *cpudata;
1642 unsigned long flags;
1645 if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1648 rdmsrl_safe(MSR_HWP_STATUS, &value);
1649 if (!(value & 0x01))
1652 spin_lock_irqsave(&hwp_notify_lock, flags);
1654 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
1658 * Currently we never free all_cpu_data. And we can't reach here
1659 * without this allocated. But for safety for future changes, added
1662 if (unlikely(!READ_ONCE(all_cpu_data)))
1666 * The free is done during cleanup, when cpufreq registry is failed.
1667 * We wouldn't be here if it fails on init or switch status. But for
1668 * future changes, added check.
1670 cpudata = READ_ONCE(all_cpu_data[this_cpu]);
1671 if (unlikely(!cpudata))
1674 schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10));
1676 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1681 wrmsrl_safe(MSR_HWP_STATUS, 0);
1682 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1685 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1687 unsigned long flags;
1689 if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1692 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1693 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1695 spin_lock_irqsave(&hwp_notify_lock, flags);
1696 if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask))
1697 cancel_delayed_work(&cpudata->hwp_notify_work);
1698 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1701 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1703 /* Enable HWP notification interrupt for guaranteed performance change */
1704 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1705 unsigned long flags;
1707 spin_lock_irqsave(&hwp_notify_lock, flags);
1708 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1709 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1710 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1712 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1713 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
1714 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1718 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
1720 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1723 * If the EPP is set by firmware, which means that firmware enabled HWP
1724 * - Is equal or less than 0x80 (default balance_perf EPP)
1725 * - But less performance oriented than performance EPP
1726 * then use this as new balance_perf EPP.
1728 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE &&
1729 cpudata->epp_default > HWP_EPP_PERFORMANCE) {
1730 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
1735 * If this CPU gen doesn't call for change in balance_perf
1738 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
1742 * Use hard coded value per gen to update the balance_perf
1745 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
1746 intel_pstate_set_epp(cpudata, cpudata->epp_default);
1749 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1751 /* First disable HWP notification interrupt till we activate again */
1752 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1753 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1755 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1757 intel_pstate_enable_hwp_interrupt(cpudata);
1759 if (cpudata->epp_default >= 0)
1762 intel_pstate_update_epp_defaults(cpudata);
1765 static int atom_get_min_pstate(int not_used)
1769 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1770 return (value >> 8) & 0x7F;
1773 static int atom_get_max_pstate(int not_used)
1777 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1778 return (value >> 16) & 0x7F;
1781 static int atom_get_turbo_pstate(int not_used)
1785 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1786 return value & 0x7F;
1789 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1795 val = (u64)pstate << 8;
1796 if (global.no_turbo && !global.turbo_disabled)
1797 val |= (u64)1 << 32;
1799 vid_fp = cpudata->vid.min + mul_fp(
1800 int_tofp(pstate - cpudata->pstate.min_pstate),
1801 cpudata->vid.ratio);
1803 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1804 vid = ceiling_fp(vid_fp);
1806 if (pstate > cpudata->pstate.max_pstate)
1807 vid = cpudata->vid.turbo;
1812 static int silvermont_get_scaling(void)
1816 /* Defined in Table 35-6 from SDM (Sept 2015) */
1817 static int silvermont_freq_table[] = {
1818 83300, 100000, 133300, 116700, 80000};
1820 rdmsrl(MSR_FSB_FREQ, value);
1824 return silvermont_freq_table[i];
1827 static int airmont_get_scaling(void)
1831 /* Defined in Table 35-10 from SDM (Sept 2015) */
1832 static int airmont_freq_table[] = {
1833 83300, 100000, 133300, 116700, 80000,
1834 93300, 90000, 88900, 87500};
1836 rdmsrl(MSR_FSB_FREQ, value);
1840 return airmont_freq_table[i];
1843 static void atom_get_vid(struct cpudata *cpudata)
1847 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1848 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1849 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1850 cpudata->vid.ratio = div_fp(
1851 cpudata->vid.max - cpudata->vid.min,
1852 int_tofp(cpudata->pstate.max_pstate -
1853 cpudata->pstate.min_pstate));
1855 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1856 cpudata->vid.turbo = value & 0x7f;
1859 static int core_get_min_pstate(int cpu)
1863 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1864 return (value >> 40) & 0xFF;
1867 static int core_get_max_pstate_physical(int cpu)
1871 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1872 return (value >> 8) & 0xFF;
1875 static int core_get_tdp_ratio(int cpu, u64 plat_info)
1877 /* Check how many TDP levels present */
1878 if (plat_info & 0x600000000) {
1884 /* Get the TDP level (0, 1, 2) to get ratios */
1885 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1889 /* TDP MSR are continuous starting at 0x648 */
1890 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1891 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio);
1895 /* For level 1 and 2, bits[23:16] contain the ratio */
1896 if (tdp_ctrl & 0x03)
1899 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1900 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1902 return (int)tdp_ratio;
1908 static int core_get_max_pstate(int cpu)
1916 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
1917 max_pstate = (plat_info >> 8) & 0xFF;
1919 tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
1924 /* Turbo activation ratio is not used on HWP platforms */
1928 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar);
1932 /* Do some sanity checking for safety */
1933 tar_levels = tar & 0xff;
1934 if (tdp_ratio - 1 == tar_levels) {
1935 max_pstate = tar_levels;
1936 pr_debug("max_pstate=TAC %x\n", max_pstate);
1943 static int core_get_turbo_pstate(int cpu)
1948 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1949 nont = core_get_max_pstate(cpu);
1950 ret = (value) & 255;
1956 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1960 val = (u64)pstate << 8;
1961 if (global.no_turbo && !global.turbo_disabled)
1962 val |= (u64)1 << 32;
1967 static int knl_get_aperf_mperf_shift(void)
1972 static int knl_get_turbo_pstate(int cpu)
1977 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1978 nont = core_get_max_pstate(cpu);
1979 ret = (((value) >> 8) & 0xFF);
1985 static void hybrid_get_type(void *data)
1987 u8 *cpu_type = data;
1989 *cpu_type = get_this_hybrid_cpu_type();
1992 static int hwp_get_cpu_scaling(int cpu)
1996 smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1);
1997 /* P-cores have a smaller perf level-to-freqency scaling factor. */
1998 if (cpu_type == 0x40)
1999 return hybrid_scaling_factor;
2001 /* Use default core scaling for E-cores */
2002 if (cpu_type == 0x20)
2003 return core_get_scaling();
2006 * If reached here, this system is either non-hybrid (like Tiger
2007 * Lake) or hybrid-capable (like Alder Lake or Raptor Lake) with
2008 * no E cores (in which case CPUID for hybrid support is 0).
2010 * The CPPC nominal_frequency field is 0 for non-hybrid systems,
2011 * so the default core scaling will be used for them.
2013 return intel_pstate_cppc_get_scaling(cpu);
2016 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
2018 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
2019 cpu->pstate.current_pstate = pstate;
2021 * Generally, there is no guarantee that this code will always run on
2022 * the CPU being updated, so force the register update to run on the
2025 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2026 pstate_funcs.get_val(cpu, pstate));
2029 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
2031 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
2034 static void intel_pstate_max_within_limits(struct cpudata *cpu)
2036 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
2038 update_turbo_state();
2039 intel_pstate_set_pstate(cpu, pstate);
2042 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
2044 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu);
2045 int perf_ctl_scaling = pstate_funcs.get_scaling();
2047 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu);
2048 cpu->pstate.max_pstate_physical = perf_ctl_max_phys;
2049 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
2051 if (hwp_active && !hwp_mode_bdw) {
2052 __intel_pstate_get_hwp_cap(cpu);
2054 if (pstate_funcs.get_cpu_scaling) {
2055 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
2056 if (cpu->pstate.scaling != perf_ctl_scaling)
2057 intel_pstate_hybrid_hwp_adjust(cpu);
2059 cpu->pstate.scaling = perf_ctl_scaling;
2062 cpu->pstate.scaling = perf_ctl_scaling;
2063 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu);
2064 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu);
2067 if (cpu->pstate.scaling == perf_ctl_scaling) {
2068 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2069 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2070 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2073 if (pstate_funcs.get_aperf_mperf_shift)
2074 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2076 if (pstate_funcs.get_vid)
2077 pstate_funcs.get_vid(cpu);
2079 intel_pstate_set_min_pstate(cpu);
2083 * Long hold time will keep high perf limits for long time,
2084 * which negatively impacts perf/watt for some workloads,
2085 * like specpower. 3ms is based on experiements on some
2088 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2090 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2092 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
2093 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2094 u32 max_limit = (hwp_req & 0xff00) >> 8;
2095 u32 min_limit = (hwp_req & 0xff);
2099 * Cases to consider (User changes via sysfs or boot time):
2100 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2102 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2103 * Should result in one level boost only for P0.
2104 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2105 * Should result in two level boost:
2106 * (min + p1)/2 and P1.
2107 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2108 * Should result in three level boost:
2109 * (min + p1)/2, P1 and P0.
2112 /* If max and min are equal or already at max, nothing to boost */
2113 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2116 if (!cpu->hwp_boost_min)
2117 cpu->hwp_boost_min = min_limit;
2119 /* level at half way mark between min and guranteed */
2120 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
2122 if (cpu->hwp_boost_min < boost_level1)
2123 cpu->hwp_boost_min = boost_level1;
2124 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2125 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2126 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2127 max_limit != HWP_GUARANTEED_PERF(hwp_cap))
2128 cpu->hwp_boost_min = max_limit;
2132 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2133 wrmsrl(MSR_HWP_REQUEST, hwp_req);
2134 cpu->last_update = cpu->sample.time;
2137 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2139 if (cpu->hwp_boost_min) {
2142 /* Check if we are idle for hold time to boost down */
2143 expired = time_after64(cpu->sample.time, cpu->last_update +
2144 hwp_boost_hold_time_ns);
2146 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
2147 cpu->hwp_boost_min = 0;
2150 cpu->last_update = cpu->sample.time;
2153 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2156 cpu->sample.time = time;
2158 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2161 cpu->sched_flags = 0;
2163 * Set iowait_boost flag and update time. Since IO WAIT flag
2164 * is set all the time, we can't just conclude that there is
2165 * some IO bound activity is scheduled on this CPU with just
2166 * one occurrence. If we receive at least two in two
2167 * consecutive ticks, then we treat as boost candidate.
2169 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2172 cpu->last_io_update = time;
2175 intel_pstate_hwp_boost_up(cpu);
2178 intel_pstate_hwp_boost_down(cpu);
2182 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2183 u64 time, unsigned int flags)
2185 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2187 cpu->sched_flags |= flags;
2189 if (smp_processor_id() == cpu->cpu)
2190 intel_pstate_update_util_hwp_local(cpu, time);
2193 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
2195 struct sample *sample = &cpu->sample;
2197 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
2200 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
2203 unsigned long flags;
2206 local_irq_save(flags);
2207 rdmsrl(MSR_IA32_APERF, aperf);
2208 rdmsrl(MSR_IA32_MPERF, mperf);
2210 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
2211 local_irq_restore(flags);
2214 local_irq_restore(flags);
2216 cpu->last_sample_time = cpu->sample.time;
2217 cpu->sample.time = time;
2218 cpu->sample.aperf = aperf;
2219 cpu->sample.mperf = mperf;
2220 cpu->sample.tsc = tsc;
2221 cpu->sample.aperf -= cpu->prev_aperf;
2222 cpu->sample.mperf -= cpu->prev_mperf;
2223 cpu->sample.tsc -= cpu->prev_tsc;
2225 cpu->prev_aperf = aperf;
2226 cpu->prev_mperf = mperf;
2227 cpu->prev_tsc = tsc;
2229 * First time this function is invoked in a given cycle, all of the
2230 * previous sample data fields are equal to zero or stale and they must
2231 * be populated with meaningful numbers for things to work, so assume
2232 * that sample.time will always be reset before setting the utilization
2233 * update hook and make the caller skip the sample then.
2235 if (cpu->last_sample_time) {
2236 intel_pstate_calc_avg_perf(cpu);
2242 static inline int32_t get_avg_frequency(struct cpudata *cpu)
2244 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
2247 static inline int32_t get_avg_pstate(struct cpudata *cpu)
2249 return mul_ext_fp(cpu->pstate.max_pstate_physical,
2250 cpu->sample.core_avg_perf);
2253 static inline int32_t get_target_pstate(struct cpudata *cpu)
2255 struct sample *sample = &cpu->sample;
2257 int target, avg_pstate;
2259 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
2262 if (busy_frac < cpu->iowait_boost)
2263 busy_frac = cpu->iowait_boost;
2265 sample->busy_scaled = busy_frac * 100;
2267 target = global.no_turbo || global.turbo_disabled ?
2268 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2269 target += target >> 2;
2270 target = mul_fp(target, busy_frac);
2271 if (target < cpu->pstate.min_pstate)
2272 target = cpu->pstate.min_pstate;
2275 * If the average P-state during the previous cycle was higher than the
2276 * current target, add 50% of the difference to the target to reduce
2277 * possible performance oscillations and offset possible performance
2278 * loss related to moving the workload from one CPU to another within
2281 avg_pstate = get_avg_pstate(cpu);
2282 if (avg_pstate > target)
2283 target += (avg_pstate - target) >> 1;
2288 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
2290 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2291 int max_pstate = max(min_pstate, cpu->max_perf_ratio);
2293 return clamp_t(int, pstate, min_pstate, max_pstate);
2296 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2298 if (pstate == cpu->pstate.current_pstate)
2301 cpu->pstate.current_pstate = pstate;
2302 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
2305 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
2307 int from = cpu->pstate.current_pstate;
2308 struct sample *sample;
2311 update_turbo_state();
2313 target_pstate = get_target_pstate(cpu);
2314 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2315 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
2316 intel_pstate_update_pstate(cpu, target_pstate);
2318 sample = &cpu->sample;
2319 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
2320 fp_toint(sample->busy_scaled),
2322 cpu->pstate.current_pstate,
2326 get_avg_frequency(cpu),
2327 fp_toint(cpu->iowait_boost * 100));
2330 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
2333 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2336 /* Don't allow remote callbacks */
2337 if (smp_processor_id() != cpu->cpu)
2340 delta_ns = time - cpu->last_update;
2341 if (flags & SCHED_CPUFREQ_IOWAIT) {
2342 /* Start over if the CPU may have been idle. */
2343 if (delta_ns > TICK_NSEC) {
2344 cpu->iowait_boost = ONE_EIGHTH_FP;
2345 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2346 cpu->iowait_boost <<= 1;
2347 if (cpu->iowait_boost > int_tofp(1))
2348 cpu->iowait_boost = int_tofp(1);
2350 cpu->iowait_boost = ONE_EIGHTH_FP;
2352 } else if (cpu->iowait_boost) {
2353 /* Clear iowait_boost if the CPU may have been idle. */
2354 if (delta_ns > TICK_NSEC)
2355 cpu->iowait_boost = 0;
2357 cpu->iowait_boost >>= 1;
2359 cpu->last_update = time;
2360 delta_ns = time - cpu->sample.time;
2361 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2364 if (intel_pstate_sample(cpu, time))
2365 intel_pstate_adjust_pstate(cpu);
2368 static struct pstate_funcs core_funcs = {
2369 .get_max = core_get_max_pstate,
2370 .get_max_physical = core_get_max_pstate_physical,
2371 .get_min = core_get_min_pstate,
2372 .get_turbo = core_get_turbo_pstate,
2373 .get_scaling = core_get_scaling,
2374 .get_val = core_get_val,
2377 static const struct pstate_funcs silvermont_funcs = {
2378 .get_max = atom_get_max_pstate,
2379 .get_max_physical = atom_get_max_pstate,
2380 .get_min = atom_get_min_pstate,
2381 .get_turbo = atom_get_turbo_pstate,
2382 .get_val = atom_get_val,
2383 .get_scaling = silvermont_get_scaling,
2384 .get_vid = atom_get_vid,
2387 static const struct pstate_funcs airmont_funcs = {
2388 .get_max = atom_get_max_pstate,
2389 .get_max_physical = atom_get_max_pstate,
2390 .get_min = atom_get_min_pstate,
2391 .get_turbo = atom_get_turbo_pstate,
2392 .get_val = atom_get_val,
2393 .get_scaling = airmont_get_scaling,
2394 .get_vid = atom_get_vid,
2397 static const struct pstate_funcs knl_funcs = {
2398 .get_max = core_get_max_pstate,
2399 .get_max_physical = core_get_max_pstate_physical,
2400 .get_min = core_get_min_pstate,
2401 .get_turbo = knl_get_turbo_pstate,
2402 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2403 .get_scaling = core_get_scaling,
2404 .get_val = core_get_val,
2407 #define X86_MATCH(model, policy) \
2408 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
2409 X86_FEATURE_APERFMPERF, &policy)
2411 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2412 X86_MATCH(SANDYBRIDGE, core_funcs),
2413 X86_MATCH(SANDYBRIDGE_X, core_funcs),
2414 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs),
2415 X86_MATCH(IVYBRIDGE, core_funcs),
2416 X86_MATCH(HASWELL, core_funcs),
2417 X86_MATCH(BROADWELL, core_funcs),
2418 X86_MATCH(IVYBRIDGE_X, core_funcs),
2419 X86_MATCH(HASWELL_X, core_funcs),
2420 X86_MATCH(HASWELL_L, core_funcs),
2421 X86_MATCH(HASWELL_G, core_funcs),
2422 X86_MATCH(BROADWELL_G, core_funcs),
2423 X86_MATCH(ATOM_AIRMONT, airmont_funcs),
2424 X86_MATCH(SKYLAKE_L, core_funcs),
2425 X86_MATCH(BROADWELL_X, core_funcs),
2426 X86_MATCH(SKYLAKE, core_funcs),
2427 X86_MATCH(BROADWELL_D, core_funcs),
2428 X86_MATCH(XEON_PHI_KNL, knl_funcs),
2429 X86_MATCH(XEON_PHI_KNM, knl_funcs),
2430 X86_MATCH(ATOM_GOLDMONT, core_funcs),
2431 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs),
2432 X86_MATCH(SKYLAKE_X, core_funcs),
2433 X86_MATCH(COMETLAKE, core_funcs),
2434 X86_MATCH(ICELAKE_X, core_funcs),
2435 X86_MATCH(TIGERLAKE, core_funcs),
2436 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs),
2437 X86_MATCH(EMERALDRAPIDS_X, core_funcs),
2440 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2442 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2443 X86_MATCH(BROADWELL_D, core_funcs),
2444 X86_MATCH(BROADWELL_X, core_funcs),
2445 X86_MATCH(SKYLAKE_X, core_funcs),
2446 X86_MATCH(ICELAKE_X, core_funcs),
2447 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs),
2451 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2452 X86_MATCH(KABYLAKE, core_funcs),
2456 static int intel_pstate_init_cpu(unsigned int cpunum)
2458 struct cpudata *cpu;
2460 cpu = all_cpu_data[cpunum];
2463 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2467 WRITE_ONCE(all_cpu_data[cpunum], cpu);
2471 cpu->epp_default = -EINVAL;
2474 intel_pstate_hwp_enable(cpu);
2476 if (intel_pstate_acpi_pm_profile_server())
2479 } else if (hwp_active) {
2481 * Re-enable HWP in case this happens after a resume from ACPI
2482 * S3 if the CPU was offline during the whole system/resume
2485 intel_pstate_hwp_reenable(cpu);
2488 cpu->epp_powersave = -EINVAL;
2489 cpu->epp_policy = 0;
2491 intel_pstate_get_cpu_pstates(cpu);
2493 pr_debug("controlling: cpu %d\n", cpunum);
2498 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2500 struct cpudata *cpu = all_cpu_data[cpu_num];
2502 if (hwp_active && !hwp_boost)
2505 if (cpu->update_util_set)
2508 /* Prevent intel_pstate_update_util() from using stale data. */
2509 cpu->sample.time = 0;
2510 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2512 intel_pstate_update_util_hwp :
2513 intel_pstate_update_util));
2514 cpu->update_util_set = true;
2517 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2519 struct cpudata *cpu_data = all_cpu_data[cpu];
2521 if (!cpu_data->update_util_set)
2524 cpufreq_remove_update_util_hook(cpu);
2525 cpu_data->update_util_set = false;
2529 static int intel_pstate_get_max_freq(struct cpudata *cpu)
2531 return global.turbo_disabled || global.no_turbo ?
2532 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2535 static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2536 unsigned int policy_min,
2537 unsigned int policy_max)
2539 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
2540 int32_t max_policy_perf, min_policy_perf;
2542 max_policy_perf = policy_max / perf_ctl_scaling;
2543 if (policy_max == policy_min) {
2544 min_policy_perf = max_policy_perf;
2546 min_policy_perf = policy_min / perf_ctl_scaling;
2547 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2548 0, max_policy_perf);
2552 * HWP needs some special consideration, because HWP_REQUEST uses
2553 * abstract values to represent performance rather than pure ratios.
2555 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
2558 freq = max_policy_perf * perf_ctl_scaling;
2559 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2560 freq = min_policy_perf * perf_ctl_scaling;
2561 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2564 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2565 cpu->cpu, min_policy_perf, max_policy_perf);
2567 /* Normalize user input to [min_perf, max_perf] */
2568 if (per_cpu_limits) {
2569 cpu->min_perf_ratio = min_policy_perf;
2570 cpu->max_perf_ratio = max_policy_perf;
2572 int turbo_max = cpu->pstate.turbo_pstate;
2573 int32_t global_min, global_max;
2575 /* Global limits are in percent of the maximum turbo P-state. */
2576 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2577 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2578 global_min = clamp_t(int32_t, global_min, 0, global_max);
2580 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2581 global_min, global_max);
2583 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2584 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2585 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2586 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2588 /* Make sure min_perf <= max_perf */
2589 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2590 cpu->max_perf_ratio);
2593 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2594 cpu->max_perf_ratio,
2595 cpu->min_perf_ratio);
2598 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2600 struct cpudata *cpu;
2602 if (!policy->cpuinfo.max_freq)
2605 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2606 policy->cpuinfo.max_freq, policy->max);
2608 cpu = all_cpu_data[policy->cpu];
2609 cpu->policy = policy->policy;
2611 mutex_lock(&intel_pstate_limits_lock);
2613 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2615 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2617 * NOHZ_FULL CPUs need this as the governor callback may not
2618 * be invoked on them.
2620 intel_pstate_clear_update_util_hook(policy->cpu);
2621 intel_pstate_max_within_limits(cpu);
2623 intel_pstate_set_update_util_hook(policy->cpu);
2628 * When hwp_boost was active before and dynamically it
2629 * was turned off, in that case we need to clear the
2633 intel_pstate_clear_update_util_hook(policy->cpu);
2634 intel_pstate_hwp_set(policy->cpu);
2637 * policy->cur is never updated with the intel_pstate driver, but it
2638 * is used as a stale frequency value. So, keep it within limits.
2640 policy->cur = policy->min;
2642 mutex_unlock(&intel_pstate_limits_lock);
2647 static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2648 struct cpufreq_policy_data *policy)
2651 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2652 policy->max < policy->cpuinfo.max_freq &&
2653 policy->max > cpu->pstate.max_freq) {
2654 pr_debug("policy->max > max non turbo frequency\n");
2655 policy->max = policy->cpuinfo.max_freq;
2659 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2660 struct cpufreq_policy_data *policy)
2664 update_turbo_state();
2666 intel_pstate_get_hwp_cap(cpu);
2667 max_freq = global.no_turbo || global.turbo_disabled ?
2668 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2670 max_freq = intel_pstate_get_max_freq(cpu);
2672 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2674 intel_pstate_adjust_policy_max(cpu, policy);
2677 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2679 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2684 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
2686 struct cpudata *cpu = all_cpu_data[policy->cpu];
2688 pr_debug("CPU %d going offline\n", cpu->cpu);
2694 * If the CPU is an SMT thread and it goes offline with the performance
2695 * settings different from the minimum, it will prevent its sibling
2696 * from getting to lower performance levels, so force the minimum
2697 * performance on CPU offline to prevent that from happening.
2700 intel_pstate_hwp_offline(cpu);
2702 intel_pstate_set_min_pstate(cpu);
2704 intel_pstate_exit_perf_limits(policy);
2709 static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2711 struct cpudata *cpu = all_cpu_data[policy->cpu];
2713 pr_debug("CPU %d going online\n", cpu->cpu);
2715 intel_pstate_init_acpi_perf_limits(policy);
2719 * Re-enable HWP and clear the "suspended" flag to let "resume"
2720 * know that it need not do that.
2722 intel_pstate_hwp_reenable(cpu);
2723 cpu->suspended = false;
2729 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2731 intel_pstate_clear_update_util_hook(policy->cpu);
2733 return intel_cpufreq_cpu_offline(policy);
2736 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2738 pr_debug("CPU %d exiting\n", policy->cpu);
2740 policy->fast_switch_possible = false;
2745 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2747 struct cpudata *cpu;
2750 rc = intel_pstate_init_cpu(policy->cpu);
2754 cpu = all_cpu_data[policy->cpu];
2756 cpu->max_perf_ratio = 0xFF;
2757 cpu->min_perf_ratio = 0;
2759 /* cpuinfo and default policy values */
2760 policy->cpuinfo.min_freq = cpu->pstate.min_freq;
2761 update_turbo_state();
2762 global.turbo_disabled_mf = global.turbo_disabled;
2763 policy->cpuinfo.max_freq = global.turbo_disabled ?
2764 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2766 policy->min = policy->cpuinfo.min_freq;
2767 policy->max = policy->cpuinfo.max_freq;
2769 intel_pstate_init_acpi_perf_limits(policy);
2771 policy->fast_switch_possible = true;
2776 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2778 int ret = __intel_pstate_cpu_init(policy);
2784 * Set the policy to powersave to provide a valid fallback value in case
2785 * the default cpufreq governor is neither powersave nor performance.
2787 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2790 struct cpudata *cpu = all_cpu_data[policy->cpu];
2792 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
2798 static struct cpufreq_driver intel_pstate = {
2799 .flags = CPUFREQ_CONST_LOOPS,
2800 .verify = intel_pstate_verify_policy,
2801 .setpolicy = intel_pstate_set_policy,
2802 .suspend = intel_pstate_suspend,
2803 .resume = intel_pstate_resume,
2804 .init = intel_pstate_cpu_init,
2805 .exit = intel_pstate_cpu_exit,
2806 .offline = intel_pstate_cpu_offline,
2807 .online = intel_pstate_cpu_online,
2808 .update_limits = intel_pstate_update_limits,
2809 .name = "intel_pstate",
2812 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
2814 struct cpudata *cpu = all_cpu_data[policy->cpu];
2816 intel_pstate_verify_cpu_policy(cpu, policy);
2817 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2822 /* Use of trace in passive mode:
2824 * In passive mode the trace core_busy field (also known as the
2825 * performance field, and lablelled as such on the graphs; also known as
2826 * core_avg_perf) is not needed and so is re-assigned to indicate if the
2827 * driver call was via the normal or fast switch path. Various graphs
2828 * output from the intel_pstate_tracer.py utility that include core_busy
2829 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2830 * so we use 10 to indicate the normal path through the driver, and
2831 * 90 to indicate the fast switch path through the driver.
2832 * The scaled_busy field is not used, and is set to 0.
2835 #define INTEL_PSTATE_TRACE_TARGET 10
2836 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2838 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2840 struct sample *sample;
2842 if (!trace_pstate_sample_enabled())
2845 if (!intel_pstate_sample(cpu, ktime_get()))
2848 sample = &cpu->sample;
2849 trace_pstate_sample(trace_type,
2852 cpu->pstate.current_pstate,
2856 get_avg_frequency(cpu),
2857 fp_toint(cpu->iowait_boost * 100));
2860 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
2861 u32 desired, bool fast_switch)
2863 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
2865 value &= ~HWP_MIN_PERF(~0L);
2866 value |= HWP_MIN_PERF(min);
2868 value &= ~HWP_MAX_PERF(~0L);
2869 value |= HWP_MAX_PERF(max);
2871 value &= ~HWP_DESIRED_PERF(~0L);
2872 value |= HWP_DESIRED_PERF(desired);
2877 WRITE_ONCE(cpu->hwp_req_cached, value);
2879 wrmsrl(MSR_HWP_REQUEST, value);
2881 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
2884 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
2885 u32 target_pstate, bool fast_switch)
2888 wrmsrl(MSR_IA32_PERF_CTL,
2889 pstate_funcs.get_val(cpu, target_pstate));
2891 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2892 pstate_funcs.get_val(cpu, target_pstate));
2895 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
2896 int target_pstate, bool fast_switch)
2898 struct cpudata *cpu = all_cpu_data[policy->cpu];
2899 int old_pstate = cpu->pstate.current_pstate;
2901 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2903 int max_pstate = policy->strict_target ?
2904 target_pstate : cpu->max_perf_ratio;
2906 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0,
2908 } else if (target_pstate != old_pstate) {
2909 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
2912 cpu->pstate.current_pstate = target_pstate;
2914 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
2915 INTEL_PSTATE_TRACE_TARGET, old_pstate);
2917 return target_pstate;
2920 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2921 unsigned int target_freq,
2922 unsigned int relation)
2924 struct cpudata *cpu = all_cpu_data[policy->cpu];
2925 struct cpufreq_freqs freqs;
2928 update_turbo_state();
2930 freqs.old = policy->cur;
2931 freqs.new = target_freq;
2933 cpufreq_freq_transition_begin(policy, &freqs);
2935 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation);
2936 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
2938 freqs.new = target_pstate * cpu->pstate.scaling;
2940 cpufreq_freq_transition_end(policy, &freqs, false);
2945 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2946 unsigned int target_freq)
2948 struct cpudata *cpu = all_cpu_data[policy->cpu];
2951 update_turbo_state();
2953 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq);
2955 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
2957 return target_pstate * cpu->pstate.scaling;
2960 static void intel_cpufreq_adjust_perf(unsigned int cpunum,
2961 unsigned long min_perf,
2962 unsigned long target_perf,
2963 unsigned long capacity)
2965 struct cpudata *cpu = all_cpu_data[cpunum];
2966 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2967 int old_pstate = cpu->pstate.current_pstate;
2968 int cap_pstate, min_pstate, max_pstate, target_pstate;
2970 update_turbo_state();
2971 cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) :
2972 HWP_HIGHEST_PERF(hwp_cap);
2974 /* Optimization: Avoid unnecessary divisions. */
2976 target_pstate = cap_pstate;
2977 if (target_perf < capacity)
2978 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
2980 min_pstate = cap_pstate;
2981 if (min_perf < capacity)
2982 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
2984 if (min_pstate < cpu->pstate.min_pstate)
2985 min_pstate = cpu->pstate.min_pstate;
2987 if (min_pstate < cpu->min_perf_ratio)
2988 min_pstate = cpu->min_perf_ratio;
2990 if (min_pstate > cpu->max_perf_ratio)
2991 min_pstate = cpu->max_perf_ratio;
2993 max_pstate = min(cap_pstate, cpu->max_perf_ratio);
2994 if (max_pstate < min_pstate)
2995 max_pstate = min_pstate;
2997 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
2999 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true);
3001 cpu->pstate.current_pstate = target_pstate;
3002 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
3005 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
3007 struct freq_qos_request *req;
3008 struct cpudata *cpu;
3012 dev = get_cpu_device(policy->cpu);
3016 ret = __intel_pstate_cpu_init(policy);
3020 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
3021 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
3022 policy->cur = policy->cpuinfo.min_freq;
3024 req = kcalloc(2, sizeof(*req), GFP_KERNEL);
3030 cpu = all_cpu_data[policy->cpu];
3035 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
3037 intel_pstate_get_hwp_cap(cpu);
3039 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
3040 WRITE_ONCE(cpu->hwp_req_cached, value);
3042 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
3044 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
3047 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
3049 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
3052 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
3056 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
3058 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
3061 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3062 goto remove_min_req;
3065 policy->driver_data = req;
3070 freq_qos_remove_request(req);
3074 intel_pstate_exit_perf_limits(policy);
3079 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3081 struct freq_qos_request *req;
3083 req = policy->driver_data;
3085 freq_qos_remove_request(req + 1);
3086 freq_qos_remove_request(req);
3089 return intel_pstate_cpu_exit(policy);
3092 static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3094 intel_pstate_suspend(policy);
3097 struct cpudata *cpu = all_cpu_data[policy->cpu];
3098 u64 value = READ_ONCE(cpu->hwp_req_cached);
3101 * Clear the desired perf field in MSR_HWP_REQUEST in case
3102 * intel_cpufreq_adjust_perf() is in use and the last value
3103 * written by it may not be suitable.
3105 value &= ~HWP_DESIRED_PERF(~0L);
3106 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3107 WRITE_ONCE(cpu->hwp_req_cached, value);
3113 static struct cpufreq_driver intel_cpufreq = {
3114 .flags = CPUFREQ_CONST_LOOPS,
3115 .verify = intel_cpufreq_verify_policy,
3116 .target = intel_cpufreq_target,
3117 .fast_switch = intel_cpufreq_fast_switch,
3118 .init = intel_cpufreq_cpu_init,
3119 .exit = intel_cpufreq_cpu_exit,
3120 .offline = intel_cpufreq_cpu_offline,
3121 .online = intel_pstate_cpu_online,
3122 .suspend = intel_cpufreq_suspend,
3123 .resume = intel_pstate_resume,
3124 .update_limits = intel_pstate_update_limits,
3125 .name = "intel_cpufreq",
3128 static struct cpufreq_driver *default_driver;
3130 static void intel_pstate_driver_cleanup(void)
3135 for_each_online_cpu(cpu) {
3136 if (all_cpu_data[cpu]) {
3137 if (intel_pstate_driver == &intel_pstate)
3138 intel_pstate_clear_update_util_hook(cpu);
3140 spin_lock(&hwp_notify_lock);
3141 kfree(all_cpu_data[cpu]);
3142 WRITE_ONCE(all_cpu_data[cpu], NULL);
3143 spin_unlock(&hwp_notify_lock);
3148 intel_pstate_driver = NULL;
3151 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
3155 if (driver == &intel_pstate)
3156 intel_pstate_sysfs_expose_hwp_dynamic_boost();
3158 memset(&global, 0, sizeof(global));
3159 global.max_perf_pct = 100;
3161 intel_pstate_driver = driver;
3162 ret = cpufreq_register_driver(intel_pstate_driver);
3164 intel_pstate_driver_cleanup();
3168 global.min_perf_pct = min_perf_pct_min();
3173 static ssize_t intel_pstate_show_status(char *buf)
3175 if (!intel_pstate_driver)
3176 return sprintf(buf, "off\n");
3178 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
3179 "active" : "passive");
3182 static int intel_pstate_update_status(const char *buf, size_t size)
3184 if (size == 3 && !strncmp(buf, "off", size)) {
3185 if (!intel_pstate_driver)
3191 cpufreq_unregister_driver(intel_pstate_driver);
3192 intel_pstate_driver_cleanup();
3196 if (size == 6 && !strncmp(buf, "active", size)) {
3197 if (intel_pstate_driver) {
3198 if (intel_pstate_driver == &intel_pstate)
3201 cpufreq_unregister_driver(intel_pstate_driver);
3204 return intel_pstate_register_driver(&intel_pstate);
3207 if (size == 7 && !strncmp(buf, "passive", size)) {
3208 if (intel_pstate_driver) {
3209 if (intel_pstate_driver == &intel_cpufreq)
3212 cpufreq_unregister_driver(intel_pstate_driver);
3213 intel_pstate_sysfs_hide_hwp_dynamic_boost();
3216 return intel_pstate_register_driver(&intel_cpufreq);
3222 static int no_load __initdata;
3223 static int no_hwp __initdata;
3224 static int hwp_only __initdata;
3225 static unsigned int force_load __initdata;
3227 static int __init intel_pstate_msrs_not_valid(void)
3229 if (!pstate_funcs.get_max(0) ||
3230 !pstate_funcs.get_min(0) ||
3231 !pstate_funcs.get_turbo(0))
3237 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
3239 pstate_funcs.get_max = funcs->get_max;
3240 pstate_funcs.get_max_physical = funcs->get_max_physical;
3241 pstate_funcs.get_min = funcs->get_min;
3242 pstate_funcs.get_turbo = funcs->get_turbo;
3243 pstate_funcs.get_scaling = funcs->get_scaling;
3244 pstate_funcs.get_val = funcs->get_val;
3245 pstate_funcs.get_vid = funcs->get_vid;
3246 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
3251 static bool __init intel_pstate_no_acpi_pss(void)
3255 for_each_possible_cpu(i) {
3257 union acpi_object *pss;
3258 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3259 struct acpi_processor *pr = per_cpu(processors, i);
3264 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
3265 if (ACPI_FAILURE(status))
3268 pss = buffer.pointer;
3269 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3277 pr_debug("ACPI _PSS not found\n");
3281 static bool __init intel_pstate_no_acpi_pcch(void)
3286 status = acpi_get_handle(NULL, "\\_SB", &handle);
3287 if (ACPI_FAILURE(status))
3290 if (acpi_has_method(handle, "PCCH"))
3294 pr_debug("ACPI PCCH not found\n");
3298 static bool __init intel_pstate_has_acpi_ppc(void)
3302 for_each_possible_cpu(i) {
3303 struct acpi_processor *pr = per_cpu(processors, i);
3307 if (acpi_has_method(pr->handle, "_PPC"))
3310 pr_debug("ACPI _PPC not found\n");
3319 /* Hardware vendor-specific info that has its own power management modes */
3320 static struct acpi_platform_list plat_info[] __initdata = {
3321 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3322 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3323 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3324 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3325 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3326 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3327 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3328 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3329 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3330 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3331 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3332 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3333 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3334 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3335 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3339 #define BITMASK_OOB (BIT(8) | BIT(18))
3341 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
3343 const struct x86_cpu_id *id;
3347 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3349 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
3350 if (misc_pwr & BITMASK_OOB) {
3351 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3352 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3357 idx = acpi_match_platform_list(plat_info);
3361 switch (plat_info[idx].data) {
3363 if (!intel_pstate_no_acpi_pss())
3366 return intel_pstate_no_acpi_pcch();
3368 return intel_pstate_has_acpi_ppc() && !force_load;
3374 static void intel_pstate_request_control_from_smm(void)
3377 * It may be unsafe to request P-states control from SMM if _PPC support
3378 * has not been enabled.
3381 acpi_processor_pstate_control();
3383 #else /* CONFIG_ACPI not enabled */
3384 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
3385 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
3386 static inline void intel_pstate_request_control_from_smm(void) {}
3387 #endif /* CONFIG_ACPI */
3389 #define INTEL_PSTATE_HWP_BROADWELL 0x01
3391 #define X86_MATCH_HWP(model, hwp_mode) \
3392 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
3393 X86_FEATURE_HWP, hwp_mode)
3395 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3396 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
3397 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL),
3398 X86_MATCH_HWP(ANY, 0),
3402 static bool intel_pstate_hwp_is_enabled(void)
3406 rdmsrl(MSR_PM_ENABLE, value);
3407 return !!(value & 0x1);
3410 static const struct x86_cpu_id intel_epp_balance_perf[] = {
3412 * Set EPP value as 102, this is the max suggested EPP
3413 * which can result in one core turbo frequency for
3414 * AlderLake Mobile CPUs.
3416 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 102),
3417 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, 32),
3421 static const struct x86_cpu_id intel_hybrid_scaling_factor[] = {
3422 X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL),
3426 static int __init intel_pstate_init(void)
3428 static struct cpudata **_all_cpu_data;
3429 const struct x86_cpu_id *id;
3432 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3435 id = x86_match_cpu(hwp_support_ids);
3437 hwp_forced = intel_pstate_hwp_is_enabled();
3440 pr_info("HWP enabled by BIOS\n");
3444 copy_cpu_funcs(&core_funcs);
3446 * Avoid enabling HWP for processors without EPP support,
3447 * because that means incomplete HWP implementation which is a
3448 * corner case and supporting it is generally problematic.
3450 * If HWP is enabled already, though, there is no choice but to
3453 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
3454 WRITE_ONCE(hwp_active, 1);
3455 hwp_mode_bdw = id->driver_data;
3456 intel_pstate.attr = hwp_cpufreq_attrs;
3457 intel_cpufreq.attr = hwp_cpufreq_attrs;
3458 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3459 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3460 if (!default_driver)
3461 default_driver = &intel_pstate;
3463 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling;
3465 goto hwp_cpu_matched;
3467 pr_info("HWP not enabled\n");
3472 id = x86_match_cpu(intel_pstate_cpu_ids);
3474 pr_info("CPU model not supported\n");
3478 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3481 if (intel_pstate_msrs_not_valid()) {
3482 pr_info("Invalid MSRs\n");
3485 /* Without HWP start in the passive mode. */
3486 if (!default_driver)
3487 default_driver = &intel_cpufreq;
3491 * The Intel pstate driver will be ignored if the platform
3492 * firmware has its own power management modes.
3494 if (intel_pstate_platform_pwr_mgmt_exists()) {
3495 pr_info("P-states controlled by the platform\n");
3499 if (!hwp_active && hwp_only)
3502 pr_info("Intel P-state driver initializing\n");
3504 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3508 WRITE_ONCE(all_cpu_data, _all_cpu_data);
3510 intel_pstate_request_control_from_smm();
3512 intel_pstate_sysfs_expose_params();
3515 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_balance_perf);
3516 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor);
3519 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = id->driver_data;
3522 hybrid_scaling_factor = hybrid_id->driver_data;
3523 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor);
3528 mutex_lock(&intel_pstate_driver_lock);
3529 rc = intel_pstate_register_driver(default_driver);
3530 mutex_unlock(&intel_pstate_driver_lock);
3532 intel_pstate_sysfs_remove();
3537 const struct x86_cpu_id *id;
3539 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3541 set_power_ctl_ee_state(false);
3542 pr_info("Disabling energy efficiency optimization\n");
3545 pr_info("HWP enabled\n");
3546 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3547 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
3552 device_initcall(intel_pstate_init);
3554 static int __init intel_pstate_setup(char *str)
3559 if (!strcmp(str, "disable"))
3561 else if (!strcmp(str, "active"))
3562 default_driver = &intel_pstate;
3563 else if (!strcmp(str, "passive"))
3564 default_driver = &intel_cpufreq;
3566 if (!strcmp(str, "no_hwp"))
3569 if (!strcmp(str, "force"))
3571 if (!strcmp(str, "hwp_only"))
3573 if (!strcmp(str, "per_cpu_perf_limits"))
3574 per_cpu_limits = true;
3577 if (!strcmp(str, "support_acpi_ppc"))
3583 early_param("intel_pstate", intel_pstate_setup);
3585 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3586 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");