1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel_pstate.c: Native P state management for Intel processors
5 * (C) Copyright 2012 Intel Corporation
6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/kernel.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/module.h>
14 #include <linux/ktime.h>
15 #include <linux/hrtimer.h>
16 #include <linux/tick.h>
17 #include <linux/slab.h>
18 #include <linux/sched/cpufreq.h>
19 #include <linux/list.h>
20 #include <linux/cpu.h>
21 #include <linux/cpufreq.h>
22 #include <linux/sysfs.h>
23 #include <linux/types.h>
25 #include <linux/acpi.h>
26 #include <linux/vmalloc.h>
27 #include <linux/pm_qos.h>
28 #include <linux/bitfield.h>
29 #include <trace/events/power.h>
32 #include <asm/div64.h>
34 #include <asm/cpu_device_id.h>
35 #include <asm/cpufeature.h>
36 #include <asm/intel-family.h>
37 #include "../drivers/thermal/intel/thermal_interrupt.h"
39 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
41 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
42 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000
43 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
46 #include <acpi/processor.h>
47 #include <acpi/cppc_acpi.h>
51 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
52 #define fp_toint(X) ((X) >> FRAC_BITS)
54 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
57 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
58 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
59 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
61 static inline int32_t mul_fp(int32_t x, int32_t y)
63 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
66 static inline int32_t div_fp(s64 x, s64 y)
68 return div64_s64((int64_t)x << FRAC_BITS, y);
71 static inline int ceiling_fp(int32_t x)
76 mask = (1 << FRAC_BITS) - 1;
82 static inline u64 mul_ext_fp(u64 x, u64 y)
84 return (x * y) >> EXT_FRAC_BITS;
87 static inline u64 div_ext_fp(u64 x, u64 y)
89 return div64_u64(x << EXT_FRAC_BITS, y);
93 * struct sample - Store performance sample
94 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
95 * performance during last sample period
96 * @busy_scaled: Scaled busy value which is used to calculate next
97 * P state. This can be different than core_avg_perf
98 * to account for cpu idle period
99 * @aperf: Difference of actual performance frequency clock count
100 * read from APERF MSR between last and current sample
101 * @mperf: Difference of maximum performance frequency clock count
102 * read from MPERF MSR between last and current sample
103 * @tsc: Difference of time stamp counter between last and
105 * @time: Current time from scheduler
107 * This structure is used in the cpudata structure to store performance sample
108 * data for choosing next P State.
111 int32_t core_avg_perf;
120 * struct pstate_data - Store P state data
121 * @current_pstate: Current requested P state
122 * @min_pstate: Min P state possible for this platform
123 * @max_pstate: Max P state possible for this platform
124 * @max_pstate_physical:This is physical Max P state for a processor
125 * This can be higher than the max_pstate which can
126 * be limited by platform thermal design power limits
127 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor
128 * @scaling: Scaling factor between performance and frequency
129 * @turbo_pstate: Max Turbo P state possible for this platform
130 * @min_freq: @min_pstate frequency in cpufreq units
131 * @max_freq: @max_pstate frequency in cpufreq units
132 * @turbo_freq: @turbo_pstate frequency in cpufreq units
134 * Stores the per cpu model P state limits and current P state.
140 int max_pstate_physical;
141 int perf_ctl_scaling;
144 unsigned int min_freq;
145 unsigned int max_freq;
146 unsigned int turbo_freq;
150 * struct vid_data - Stores voltage information data
151 * @min: VID data for this platform corresponding to
153 * @max: VID data corresponding to the highest P State.
154 * @turbo: VID data for turbo P state
155 * @ratio: Ratio of (vid max - vid min) /
156 * (max P state - Min P State)
158 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
159 * This data is used in Atom platforms, where in addition to target P state,
160 * the voltage data needs to be specified to select next P State.
170 * struct global_params - Global parameters, mostly tunable via sysfs.
171 * @no_turbo: Whether or not to use turbo P-states.
172 * @turbo_disabled: Whether or not turbo P-states are available at all,
173 * based on the MSR_IA32_MISC_ENABLE value and whether or
174 * not the maximum reported turbo P-state is different from
175 * the maximum reported non-turbo one.
176 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq.
177 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
179 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
182 struct global_params {
185 bool turbo_disabled_mf;
191 * struct cpudata - Per CPU instance data storage
192 * @cpu: CPU number for this instance data
193 * @policy: CPUFreq policy value
194 * @update_util: CPUFreq utility callback information
195 * @update_util_set: CPUFreq utility callback is set
196 * @iowait_boost: iowait-related boost fraction
197 * @last_update: Time of the last update.
198 * @pstate: Stores P state limits for this CPU
199 * @vid: Stores VID limits for this CPU
200 * @last_sample_time: Last Sample time
201 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference
202 * @prev_aperf: Last APERF value read from APERF MSR
203 * @prev_mperf: Last MPERF value read from MPERF MSR
204 * @prev_tsc: Last timestamp counter (TSC) value
205 * @sample: Storage for storing last Sample data
206 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
207 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
208 * @acpi_perf_data: Stores ACPI perf information read from _PSS
209 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
210 * @epp_powersave: Last saved HWP energy performance preference
211 * (EPP) or energy performance bias (EPB),
212 * when policy switched to performance
213 * @epp_policy: Last saved policy used to set EPP/EPB
214 * @epp_default: Power on default HWP energy performance
216 * @epp_cached Cached HWP energy-performance preference value
217 * @hwp_req_cached: Cached value of the last HWP Request MSR
218 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
219 * @last_io_update: Last time when IO wake flag was set
220 * @sched_flags: Store scheduler flags for possible cross CPU update
221 * @hwp_boost_min: Last HWP boosted min performance
222 * @suspended: Whether or not the driver has been suspended.
223 * @hwp_notify_work: workqueue for HWP notifications.
225 * This structure stores per CPU instance data for all CPUs.
231 struct update_util_data update_util;
232 bool update_util_set;
234 struct pstate_data pstate;
238 u64 last_sample_time;
239 u64 aperf_mperf_shift;
243 struct sample sample;
244 int32_t min_perf_ratio;
245 int32_t max_perf_ratio;
247 struct acpi_processor_performance acpi_perf_data;
248 bool valid_pss_table;
250 unsigned int iowait_boost;
258 unsigned int sched_flags;
261 struct delayed_work hwp_notify_work;
264 static struct cpudata **all_cpu_data;
267 * struct pstate_funcs - Per CPU model specific callbacks
268 * @get_max: Callback to get maximum non turbo effective P state
269 * @get_max_physical: Callback to get maximum non turbo physical P state
270 * @get_min: Callback to get minimum P state
271 * @get_turbo: Callback to get turbo P state
272 * @get_scaling: Callback to get frequency scaling factor
273 * @get_cpu_scaling: Get frequency scaling factor for a given cpu
274 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
275 * @get_val: Callback to convert P state to actual MSR write value
276 * @get_vid: Callback to get VID data for Atom platforms
278 * Core and Atom CPU models have different way to get P State limits. This
279 * structure is used to store those callbacks.
281 struct pstate_funcs {
282 int (*get_max)(int cpu);
283 int (*get_max_physical)(int cpu);
284 int (*get_min)(int cpu);
285 int (*get_turbo)(int cpu);
286 int (*get_scaling)(void);
287 int (*get_cpu_scaling)(int cpu);
288 int (*get_aperf_mperf_shift)(void);
289 u64 (*get_val)(struct cpudata*, int pstate);
290 void (*get_vid)(struct cpudata *);
293 static struct pstate_funcs pstate_funcs __read_mostly;
295 static int hwp_active __read_mostly;
296 static int hwp_mode_bdw __read_mostly;
297 static bool per_cpu_limits __read_mostly;
298 static bool hwp_boost __read_mostly;
299 static bool hwp_forced __read_mostly;
301 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
303 #define HYBRID_SCALING_FACTOR 78741
304 #define HYBRID_SCALING_FACTOR_MTL 80000
306 static int hybrid_scaling_factor = HYBRID_SCALING_FACTOR;
308 static inline int core_get_scaling(void)
314 static bool acpi_ppc;
317 static struct global_params global;
319 static DEFINE_MUTEX(intel_pstate_driver_lock);
320 static DEFINE_MUTEX(intel_pstate_limits_lock);
324 static bool intel_pstate_acpi_pm_profile_server(void)
326 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
327 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
333 static bool intel_pstate_get_ppc_enable_status(void)
335 if (intel_pstate_acpi_pm_profile_server())
341 #ifdef CONFIG_ACPI_CPPC_LIB
343 /* The work item is needed to avoid CPU hotplug locking issues */
344 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
346 sched_set_itmt_support();
349 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
351 #define CPPC_MAX_PERF U8_MAX
353 static void intel_pstate_set_itmt_prio(int cpu)
355 struct cppc_perf_caps cppc_perf;
356 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
359 ret = cppc_get_perf_caps(cpu, &cppc_perf);
364 * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff.
365 * In this case we can't use CPPC.highest_perf to enable ITMT.
366 * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide.
368 if (cppc_perf.highest_perf == CPPC_MAX_PERF)
369 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
372 * The priorities can be set regardless of whether or not
373 * sched_set_itmt_support(true) has been called and it is valid to
374 * update them at any time after it has been called.
376 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
378 if (max_highest_perf <= min_highest_perf) {
379 if (cppc_perf.highest_perf > max_highest_perf)
380 max_highest_perf = cppc_perf.highest_perf;
382 if (cppc_perf.highest_perf < min_highest_perf)
383 min_highest_perf = cppc_perf.highest_perf;
385 if (max_highest_perf > min_highest_perf) {
387 * This code can be run during CPU online under the
388 * CPU hotplug locks, so sched_set_itmt_support()
389 * cannot be called from here. Queue up a work item
392 schedule_work(&sched_itmt_work);
397 static int intel_pstate_get_cppc_guaranteed(int cpu)
399 struct cppc_perf_caps cppc_perf;
402 ret = cppc_get_perf_caps(cpu, &cppc_perf);
406 if (cppc_perf.guaranteed_perf)
407 return cppc_perf.guaranteed_perf;
409 return cppc_perf.nominal_perf;
412 static int intel_pstate_cppc_get_scaling(int cpu)
414 struct cppc_perf_caps cppc_perf;
417 ret = cppc_get_perf_caps(cpu, &cppc_perf);
420 * If the nominal frequency and the nominal performance are not
421 * zero and the ratio between them is not 100, return the hybrid
424 if (!ret && cppc_perf.nominal_perf && cppc_perf.nominal_freq &&
425 cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq)
426 return hybrid_scaling_factor;
428 return core_get_scaling();
431 #else /* CONFIG_ACPI_CPPC_LIB */
432 static inline void intel_pstate_set_itmt_prio(int cpu)
435 #endif /* CONFIG_ACPI_CPPC_LIB */
437 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
444 intel_pstate_set_itmt_prio(policy->cpu);
448 if (!intel_pstate_get_ppc_enable_status())
451 cpu = all_cpu_data[policy->cpu];
453 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
459 * Check if the control value in _PSS is for PERF_CTL MSR, which should
460 * guarantee that the states returned by it map to the states in our
463 if (cpu->acpi_perf_data.control_register.space_id !=
464 ACPI_ADR_SPACE_FIXED_HARDWARE)
468 * If there is only one entry _PSS, simply ignore _PSS and continue as
469 * usual without taking _PSS into account
471 if (cpu->acpi_perf_data.state_count < 2)
474 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
475 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
476 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
477 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
478 (u32) cpu->acpi_perf_data.states[i].core_frequency,
479 (u32) cpu->acpi_perf_data.states[i].power,
480 (u32) cpu->acpi_perf_data.states[i].control);
483 cpu->valid_pss_table = true;
484 pr_debug("_PPC limits will be enforced\n");
489 cpu->valid_pss_table = false;
490 acpi_processor_unregister_performance(policy->cpu);
493 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
497 cpu = all_cpu_data[policy->cpu];
498 if (!cpu->valid_pss_table)
501 acpi_processor_unregister_performance(policy->cpu);
503 #else /* CONFIG_ACPI */
504 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
508 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
512 static inline bool intel_pstate_acpi_pm_profile_server(void)
516 #endif /* CONFIG_ACPI */
518 #ifndef CONFIG_ACPI_CPPC_LIB
519 static inline int intel_pstate_get_cppc_guaranteed(int cpu)
524 static int intel_pstate_cppc_get_scaling(int cpu)
526 return core_get_scaling();
528 #endif /* CONFIG_ACPI_CPPC_LIB */
530 static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq,
531 unsigned int relation)
533 if (freq == cpu->pstate.turbo_freq)
534 return cpu->pstate.turbo_pstate;
536 if (freq == cpu->pstate.max_freq)
537 return cpu->pstate.max_pstate;
540 case CPUFREQ_RELATION_H:
541 return freq / cpu->pstate.scaling;
542 case CPUFREQ_RELATION_C:
543 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling);
546 return DIV_ROUND_UP(freq, cpu->pstate.scaling);
549 static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq)
551 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L);
555 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
558 * On hybrid processors, HWP may expose more performance levels than there are
559 * P-states accessible through the PERF_CTL interface. If that happens, the
560 * scaling factor between HWP performance levels and CPU frequency will be less
561 * than the scaling factor between P-state values and CPU frequency.
563 * In that case, adjust the CPU parameters used in computations accordingly.
565 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
567 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
568 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
569 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu);
570 int scaling = cpu->pstate.scaling;
573 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
574 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo);
575 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling);
576 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
577 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
578 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
580 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
582 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
585 freq = perf_ctl_max_phys * perf_ctl_scaling;
586 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq);
588 freq = cpu->pstate.min_pstate * perf_ctl_scaling;
589 cpu->pstate.min_freq = freq;
591 * Cast the min P-state value retrieved via pstate_funcs.get_min() to
592 * the effective range of HWP performance levels.
594 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq);
597 static inline void update_turbo_state(void)
601 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
602 global.turbo_disabled = misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE;
605 static int min_perf_pct_min(void)
607 struct cpudata *cpu = all_cpu_data[0];
608 int turbo_pstate = cpu->pstate.turbo_pstate;
610 return turbo_pstate ?
611 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
614 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
619 if (!boot_cpu_has(X86_FEATURE_EPB))
622 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
626 return (s16)(epb & 0x0f);
629 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
633 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
635 * When hwp_req_data is 0, means that caller didn't read
636 * MSR_HWP_REQUEST, so need to read and get EPP.
639 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
644 epp = (hwp_req_data >> 24) & 0xff;
646 /* When there is no EPP present, HWP uses EPB settings */
647 epp = intel_pstate_get_epb(cpu_data);
653 static int intel_pstate_set_epb(int cpu, s16 pref)
658 if (!boot_cpu_has(X86_FEATURE_EPB))
661 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
665 epb = (epb & ~0x0f) | pref;
666 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
672 * EPP/EPB display strings corresponding to EPP index in the
673 * energy_perf_strings[]
675 *-------------------------------------
678 * 2 balance_performance
683 enum energy_perf_value_index {
684 EPP_INDEX_DEFAULT = 0,
685 EPP_INDEX_PERFORMANCE,
686 EPP_INDEX_BALANCE_PERFORMANCE,
687 EPP_INDEX_BALANCE_POWERSAVE,
691 static const char * const energy_perf_strings[] = {
692 [EPP_INDEX_DEFAULT] = "default",
693 [EPP_INDEX_PERFORMANCE] = "performance",
694 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
695 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
696 [EPP_INDEX_POWERSAVE] = "power",
699 static unsigned int epp_values[] = {
700 [EPP_INDEX_DEFAULT] = 0, /* Unused index */
701 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
702 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
703 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
704 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
707 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
713 epp = intel_pstate_get_epp(cpu_data, 0);
717 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
718 if (epp == epp_values[EPP_INDEX_PERFORMANCE])
719 return EPP_INDEX_PERFORMANCE;
720 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
721 return EPP_INDEX_BALANCE_PERFORMANCE;
722 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
723 return EPP_INDEX_BALANCE_POWERSAVE;
724 if (epp == epp_values[EPP_INDEX_POWERSAVE])
725 return EPP_INDEX_POWERSAVE;
728 } else if (boot_cpu_has(X86_FEATURE_EPB)) {
731 * 0x00-0x03 : Performance
732 * 0x04-0x07 : Balance performance
733 * 0x08-0x0B : Balance power
735 * The EPB is a 4 bit value, but our ranges restrict the
736 * value which can be set. Here only using top two bits
739 index = (epp >> 2) + 1;
745 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
750 * Use the cached HWP Request MSR value, because in the active mode the
751 * register itself may be updated by intel_pstate_hwp_boost_up() or
752 * intel_pstate_hwp_boost_down() at any time.
754 u64 value = READ_ONCE(cpu->hwp_req_cached);
756 value &= ~GENMASK_ULL(31, 24);
757 value |= (u64)epp << 24;
759 * The only other updater of hwp_req_cached in the active mode,
760 * intel_pstate_hwp_set(), is called under the same lock as this
761 * function, so it cannot run in parallel with the update below.
763 WRITE_ONCE(cpu->hwp_req_cached, value);
764 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
766 cpu->epp_cached = epp;
771 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
772 int pref_index, bool use_raw,
779 epp = cpu_data->epp_default;
781 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
784 else if (epp == -EINVAL)
785 epp = epp_values[pref_index];
788 * To avoid confusion, refuse to set EPP to any values different
789 * from 0 (performance) if the current policy is "performance",
790 * because those values would be overridden.
792 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
795 ret = intel_pstate_set_epp(cpu_data, epp);
798 epp = (pref_index - 1) << 2;
799 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
805 static ssize_t show_energy_performance_available_preferences(
806 struct cpufreq_policy *policy, char *buf)
811 while (energy_perf_strings[i] != NULL)
812 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
814 ret += sprintf(&buf[ret], "\n");
819 cpufreq_freq_attr_ro(energy_performance_available_preferences);
821 static struct cpufreq_driver intel_pstate;
823 static ssize_t store_energy_performance_preference(
824 struct cpufreq_policy *policy, const char *buf, size_t count)
826 struct cpudata *cpu = all_cpu_data[policy->cpu];
827 char str_preference[21];
832 ret = sscanf(buf, "%20s", str_preference);
836 ret = match_string(energy_perf_strings, -1, str_preference);
838 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
841 ret = kstrtouint(buf, 10, &epp);
852 * This function runs with the policy R/W semaphore held, which
853 * guarantees that the driver pointer will not change while it is
856 if (!intel_pstate_driver)
859 mutex_lock(&intel_pstate_limits_lock);
861 if (intel_pstate_driver == &intel_pstate) {
862 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
865 * In the passive mode the governor needs to be stopped on the
866 * target CPU before the EPP update and restarted after it,
867 * which is super-heavy-weight, so make sure it is worth doing
871 epp = ret ? epp_values[ret] : cpu->epp_default;
873 if (cpu->epp_cached != epp) {
876 cpufreq_stop_governor(policy);
877 ret = intel_pstate_set_epp(cpu, epp);
878 err = cpufreq_start_governor(policy);
886 mutex_unlock(&intel_pstate_limits_lock);
891 static ssize_t show_energy_performance_preference(
892 struct cpufreq_policy *policy, char *buf)
894 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
895 int preference, raw_epp;
897 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
902 return sprintf(buf, "%d\n", raw_epp);
904 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
907 cpufreq_freq_attr_rw(energy_performance_preference);
909 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
911 struct cpudata *cpu = all_cpu_data[policy->cpu];
914 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu);
918 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
919 ratio = HWP_GUARANTEED_PERF(cap);
922 freq = ratio * cpu->pstate.scaling;
923 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
924 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
926 return sprintf(buf, "%d\n", freq);
929 cpufreq_freq_attr_ro(base_frequency);
931 static struct freq_attr *hwp_cpufreq_attrs[] = {
932 &energy_performance_preference,
933 &energy_performance_available_preferences,
938 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
942 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
943 WRITE_ONCE(cpu->hwp_cap_cached, cap);
944 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
945 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
948 static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
950 int scaling = cpu->pstate.scaling;
952 __intel_pstate_get_hwp_cap(cpu);
954 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
955 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
956 if (scaling != cpu->pstate.perf_ctl_scaling) {
957 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
959 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
961 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
966 static void intel_pstate_hwp_set(unsigned int cpu)
968 struct cpudata *cpu_data = all_cpu_data[cpu];
973 max = cpu_data->max_perf_ratio;
974 min = cpu_data->min_perf_ratio;
976 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
979 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
981 value &= ~HWP_MIN_PERF(~0L);
982 value |= HWP_MIN_PERF(min);
984 value &= ~HWP_MAX_PERF(~0L);
985 value |= HWP_MAX_PERF(max);
987 if (cpu_data->epp_policy == cpu_data->policy)
990 cpu_data->epp_policy = cpu_data->policy;
992 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
993 epp = intel_pstate_get_epp(cpu_data, value);
994 cpu_data->epp_powersave = epp;
995 /* If EPP read was failed, then don't try to write */
1001 /* skip setting EPP, when saved value is invalid */
1002 if (cpu_data->epp_powersave < 0)
1006 * No need to restore EPP when it is not zero. This
1008 * - Policy is not changed
1009 * - user has manually changed
1010 * - Error reading EPB
1012 epp = intel_pstate_get_epp(cpu_data, value);
1016 epp = cpu_data->epp_powersave;
1018 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1019 value &= ~GENMASK_ULL(31, 24);
1020 value |= (u64)epp << 24;
1022 intel_pstate_set_epb(cpu, epp);
1025 WRITE_ONCE(cpu_data->hwp_req_cached, value);
1026 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
1029 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
1031 static void intel_pstate_hwp_offline(struct cpudata *cpu)
1033 u64 value = READ_ONCE(cpu->hwp_req_cached);
1036 intel_pstate_disable_hwp_interrupt(cpu);
1038 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1040 * In case the EPP has been set to "performance" by the
1041 * active mode "performance" scaling algorithm, replace that
1042 * temporary value with the cached EPP one.
1044 value &= ~GENMASK_ULL(31, 24);
1045 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
1047 * However, make sure that EPP will be set to "performance" when
1048 * the CPU is brought back online again and the "performance"
1049 * scaling algorithm is still in effect.
1051 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
1055 * Clear the desired perf field in the cached HWP request value to
1056 * prevent nonzero desired values from being leaked into the active
1059 value &= ~HWP_DESIRED_PERF(~0L);
1060 WRITE_ONCE(cpu->hwp_req_cached, value);
1062 value &= ~GENMASK_ULL(31, 0);
1063 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1065 /* Set hwp_max = hwp_min */
1066 value |= HWP_MAX_PERF(min_perf);
1067 value |= HWP_MIN_PERF(min_perf);
1069 /* Set EPP to min */
1070 if (boot_cpu_has(X86_FEATURE_HWP_EPP))
1071 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1073 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
1076 #define POWER_CTL_EE_ENABLE 1
1077 #define POWER_CTL_EE_DISABLE 2
1079 static int power_ctl_ee_state;
1081 static void set_power_ctl_ee_state(bool input)
1085 mutex_lock(&intel_pstate_driver_lock);
1086 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1088 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1089 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1091 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1092 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1094 wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
1095 mutex_unlock(&intel_pstate_driver_lock);
1098 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1100 static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1102 intel_pstate_hwp_enable(cpu);
1103 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1106 static int intel_pstate_suspend(struct cpufreq_policy *policy)
1108 struct cpudata *cpu = all_cpu_data[policy->cpu];
1110 pr_debug("CPU %d suspending\n", cpu->cpu);
1112 cpu->suspended = true;
1114 /* disable HWP interrupt and cancel any pending work */
1115 intel_pstate_disable_hwp_interrupt(cpu);
1120 static int intel_pstate_resume(struct cpufreq_policy *policy)
1122 struct cpudata *cpu = all_cpu_data[policy->cpu];
1124 pr_debug("CPU %d resuming\n", cpu->cpu);
1126 /* Only restore if the system default is changed */
1127 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1128 set_power_ctl_ee_state(true);
1129 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1130 set_power_ctl_ee_state(false);
1132 if (cpu->suspended && hwp_active) {
1133 mutex_lock(&intel_pstate_limits_lock);
1135 /* Re-enable HWP, because "online" has not done that. */
1136 intel_pstate_hwp_reenable(cpu);
1138 mutex_unlock(&intel_pstate_limits_lock);
1141 cpu->suspended = false;
1146 static void intel_pstate_update_policies(void)
1150 for_each_possible_cpu(cpu)
1151 cpufreq_update_policy(cpu);
1154 static void __intel_pstate_update_max_freq(struct cpudata *cpudata,
1155 struct cpufreq_policy *policy)
1157 policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
1158 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1159 refresh_frequency_limits(policy);
1162 static void intel_pstate_update_max_freq(unsigned int cpu)
1164 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1169 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy);
1171 cpufreq_cpu_release(policy);
1174 static void intel_pstate_update_limits(unsigned int cpu)
1176 mutex_lock(&intel_pstate_driver_lock);
1178 update_turbo_state();
1180 * If turbo has been turned on or off globally, policy limits for
1181 * all CPUs need to be updated to reflect that.
1183 if (global.turbo_disabled_mf != global.turbo_disabled) {
1184 global.turbo_disabled_mf = global.turbo_disabled;
1185 arch_set_max_freq_ratio(global.turbo_disabled);
1186 for_each_possible_cpu(cpu)
1187 intel_pstate_update_max_freq(cpu);
1189 cpufreq_update_policy(cpu);
1192 mutex_unlock(&intel_pstate_driver_lock);
1195 /************************** sysfs begin ************************/
1196 #define show_one(file_name, object) \
1197 static ssize_t show_##file_name \
1198 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \
1200 return sprintf(buf, "%u\n", global.object); \
1203 static ssize_t intel_pstate_show_status(char *buf);
1204 static int intel_pstate_update_status(const char *buf, size_t size);
1206 static ssize_t show_status(struct kobject *kobj,
1207 struct kobj_attribute *attr, char *buf)
1211 mutex_lock(&intel_pstate_driver_lock);
1212 ret = intel_pstate_show_status(buf);
1213 mutex_unlock(&intel_pstate_driver_lock);
1218 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1219 const char *buf, size_t count)
1221 char *p = memchr(buf, '\n', count);
1224 mutex_lock(&intel_pstate_driver_lock);
1225 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1226 mutex_unlock(&intel_pstate_driver_lock);
1228 return ret < 0 ? ret : count;
1231 static ssize_t show_turbo_pct(struct kobject *kobj,
1232 struct kobj_attribute *attr, char *buf)
1234 struct cpudata *cpu;
1235 int total, no_turbo, turbo_pct;
1238 mutex_lock(&intel_pstate_driver_lock);
1240 if (!intel_pstate_driver) {
1241 mutex_unlock(&intel_pstate_driver_lock);
1245 cpu = all_cpu_data[0];
1247 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1248 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1249 turbo_fp = div_fp(no_turbo, total);
1250 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1252 mutex_unlock(&intel_pstate_driver_lock);
1254 return sprintf(buf, "%u\n", turbo_pct);
1257 static ssize_t show_num_pstates(struct kobject *kobj,
1258 struct kobj_attribute *attr, char *buf)
1260 struct cpudata *cpu;
1263 mutex_lock(&intel_pstate_driver_lock);
1265 if (!intel_pstate_driver) {
1266 mutex_unlock(&intel_pstate_driver_lock);
1270 cpu = all_cpu_data[0];
1271 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1273 mutex_unlock(&intel_pstate_driver_lock);
1275 return sprintf(buf, "%u\n", total);
1278 static ssize_t show_no_turbo(struct kobject *kobj,
1279 struct kobj_attribute *attr, char *buf)
1283 mutex_lock(&intel_pstate_driver_lock);
1285 if (!intel_pstate_driver) {
1286 mutex_unlock(&intel_pstate_driver_lock);
1290 update_turbo_state();
1291 if (global.turbo_disabled)
1292 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1294 ret = sprintf(buf, "%u\n", global.no_turbo);
1296 mutex_unlock(&intel_pstate_driver_lock);
1301 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1302 const char *buf, size_t count)
1307 ret = sscanf(buf, "%u", &input);
1311 mutex_lock(&intel_pstate_driver_lock);
1313 if (!intel_pstate_driver) {
1314 mutex_unlock(&intel_pstate_driver_lock);
1318 mutex_lock(&intel_pstate_limits_lock);
1320 update_turbo_state();
1321 if (global.turbo_disabled) {
1322 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
1323 mutex_unlock(&intel_pstate_limits_lock);
1324 mutex_unlock(&intel_pstate_driver_lock);
1328 global.no_turbo = clamp_t(int, input, 0, 1);
1330 if (global.no_turbo) {
1331 struct cpudata *cpu = all_cpu_data[0];
1332 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1334 /* Squash the global minimum into the permitted range. */
1335 if (global.min_perf_pct > pct)
1336 global.min_perf_pct = pct;
1339 mutex_unlock(&intel_pstate_limits_lock);
1341 intel_pstate_update_policies();
1342 arch_set_max_freq_ratio(global.no_turbo);
1344 mutex_unlock(&intel_pstate_driver_lock);
1349 static void update_qos_request(enum freq_qos_req_type type)
1351 struct freq_qos_request *req;
1352 struct cpufreq_policy *policy;
1355 for_each_possible_cpu(i) {
1356 struct cpudata *cpu = all_cpu_data[i];
1357 unsigned int freq, perf_pct;
1359 policy = cpufreq_cpu_get(i);
1363 req = policy->driver_data;
1364 cpufreq_cpu_put(policy);
1370 intel_pstate_get_hwp_cap(cpu);
1372 if (type == FREQ_QOS_MIN) {
1373 perf_pct = global.min_perf_pct;
1376 perf_pct = global.max_perf_pct;
1379 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100);
1381 if (freq_qos_update_request(req, freq) < 0)
1382 pr_warn("Failed to update freq constraint: CPU%d\n", i);
1386 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1387 const char *buf, size_t count)
1392 ret = sscanf(buf, "%u", &input);
1396 mutex_lock(&intel_pstate_driver_lock);
1398 if (!intel_pstate_driver) {
1399 mutex_unlock(&intel_pstate_driver_lock);
1403 mutex_lock(&intel_pstate_limits_lock);
1405 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1407 mutex_unlock(&intel_pstate_limits_lock);
1409 if (intel_pstate_driver == &intel_pstate)
1410 intel_pstate_update_policies();
1412 update_qos_request(FREQ_QOS_MAX);
1414 mutex_unlock(&intel_pstate_driver_lock);
1419 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1420 const char *buf, size_t count)
1425 ret = sscanf(buf, "%u", &input);
1429 mutex_lock(&intel_pstate_driver_lock);
1431 if (!intel_pstate_driver) {
1432 mutex_unlock(&intel_pstate_driver_lock);
1436 mutex_lock(&intel_pstate_limits_lock);
1438 global.min_perf_pct = clamp_t(int, input,
1439 min_perf_pct_min(), global.max_perf_pct);
1441 mutex_unlock(&intel_pstate_limits_lock);
1443 if (intel_pstate_driver == &intel_pstate)
1444 intel_pstate_update_policies();
1446 update_qos_request(FREQ_QOS_MIN);
1448 mutex_unlock(&intel_pstate_driver_lock);
1453 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1454 struct kobj_attribute *attr, char *buf)
1456 return sprintf(buf, "%u\n", hwp_boost);
1459 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1460 struct kobj_attribute *b,
1461 const char *buf, size_t count)
1466 ret = kstrtouint(buf, 10, &input);
1470 mutex_lock(&intel_pstate_driver_lock);
1471 hwp_boost = !!input;
1472 intel_pstate_update_policies();
1473 mutex_unlock(&intel_pstate_driver_lock);
1478 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1484 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1485 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1486 return sprintf(buf, "%d\n", !enable);
1489 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1490 const char *buf, size_t count)
1495 ret = kstrtobool(buf, &input);
1499 set_power_ctl_ee_state(input);
1504 show_one(max_perf_pct, max_perf_pct);
1505 show_one(min_perf_pct, min_perf_pct);
1507 define_one_global_rw(status);
1508 define_one_global_rw(no_turbo);
1509 define_one_global_rw(max_perf_pct);
1510 define_one_global_rw(min_perf_pct);
1511 define_one_global_ro(turbo_pct);
1512 define_one_global_ro(num_pstates);
1513 define_one_global_rw(hwp_dynamic_boost);
1514 define_one_global_rw(energy_efficiency);
1516 static struct attribute *intel_pstate_attributes[] = {
1522 static const struct attribute_group intel_pstate_attr_group = {
1523 .attrs = intel_pstate_attributes,
1526 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1528 static struct kobject *intel_pstate_kobject;
1530 static void __init intel_pstate_sysfs_expose_params(void)
1532 struct device *dev_root = bus_get_dev_root(&cpu_subsys);
1536 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj);
1537 put_device(dev_root);
1539 if (WARN_ON(!intel_pstate_kobject))
1542 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1546 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1547 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr);
1550 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr);
1555 * If per cpu limits are enforced there are no global limits, so
1556 * return without creating max/min_perf_pct attributes
1561 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1564 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1567 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1568 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1573 static void __init intel_pstate_sysfs_remove(void)
1575 if (!intel_pstate_kobject)
1578 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1580 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1581 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr);
1582 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr);
1585 if (!per_cpu_limits) {
1586 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1587 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1589 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1590 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1593 kobject_put(intel_pstate_kobject);
1596 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1603 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1607 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1612 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1615 /************************** sysfs end ************************/
1617 static void intel_pstate_notify_work(struct work_struct *work)
1619 struct cpudata *cpudata =
1620 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
1621 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu);
1624 intel_pstate_get_hwp_cap(cpudata);
1625 __intel_pstate_update_max_freq(cpudata, policy);
1627 cpufreq_cpu_release(policy);
1630 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1633 static DEFINE_SPINLOCK(hwp_notify_lock);
1634 static cpumask_t hwp_intr_enable_mask;
1636 void notify_hwp_interrupt(void)
1638 unsigned int this_cpu = smp_processor_id();
1639 struct cpudata *cpudata;
1640 unsigned long flags;
1643 if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1646 rdmsrl_safe(MSR_HWP_STATUS, &value);
1647 if (!(value & 0x01))
1650 spin_lock_irqsave(&hwp_notify_lock, flags);
1652 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
1656 * Currently we never free all_cpu_data. And we can't reach here
1657 * without this allocated. But for safety for future changes, added
1660 if (unlikely(!READ_ONCE(all_cpu_data)))
1664 * The free is done during cleanup, when cpufreq registry is failed.
1665 * We wouldn't be here if it fails on init or switch status. But for
1666 * future changes, added check.
1668 cpudata = READ_ONCE(all_cpu_data[this_cpu]);
1669 if (unlikely(!cpudata))
1672 schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10));
1674 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1679 wrmsrl_safe(MSR_HWP_STATUS, 0);
1680 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1683 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1685 unsigned long flags;
1687 if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1690 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1691 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1693 spin_lock_irqsave(&hwp_notify_lock, flags);
1694 if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask))
1695 cancel_delayed_work(&cpudata->hwp_notify_work);
1696 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1699 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1701 /* Enable HWP notification interrupt for guaranteed performance change */
1702 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1703 unsigned long flags;
1705 spin_lock_irqsave(&hwp_notify_lock, flags);
1706 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1707 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1708 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1710 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1711 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
1712 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1716 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
1718 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1721 * If the EPP is set by firmware, which means that firmware enabled HWP
1722 * - Is equal or less than 0x80 (default balance_perf EPP)
1723 * - But less performance oriented than performance EPP
1724 * then use this as new balance_perf EPP.
1726 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE &&
1727 cpudata->epp_default > HWP_EPP_PERFORMANCE) {
1728 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
1733 * If this CPU gen doesn't call for change in balance_perf
1736 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
1740 * Use hard coded value per gen to update the balance_perf
1743 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
1744 intel_pstate_set_epp(cpudata, cpudata->epp_default);
1747 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1749 /* First disable HWP notification interrupt till we activate again */
1750 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1751 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1753 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1755 intel_pstate_enable_hwp_interrupt(cpudata);
1757 if (cpudata->epp_default >= 0)
1760 intel_pstate_update_epp_defaults(cpudata);
1763 static int atom_get_min_pstate(int not_used)
1767 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1768 return (value >> 8) & 0x7F;
1771 static int atom_get_max_pstate(int not_used)
1775 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1776 return (value >> 16) & 0x7F;
1779 static int atom_get_turbo_pstate(int not_used)
1783 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1784 return value & 0x7F;
1787 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1793 val = (u64)pstate << 8;
1794 if (global.no_turbo && !global.turbo_disabled)
1795 val |= (u64)1 << 32;
1797 vid_fp = cpudata->vid.min + mul_fp(
1798 int_tofp(pstate - cpudata->pstate.min_pstate),
1799 cpudata->vid.ratio);
1801 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1802 vid = ceiling_fp(vid_fp);
1804 if (pstate > cpudata->pstate.max_pstate)
1805 vid = cpudata->vid.turbo;
1810 static int silvermont_get_scaling(void)
1814 /* Defined in Table 35-6 from SDM (Sept 2015) */
1815 static int silvermont_freq_table[] = {
1816 83300, 100000, 133300, 116700, 80000};
1818 rdmsrl(MSR_FSB_FREQ, value);
1822 return silvermont_freq_table[i];
1825 static int airmont_get_scaling(void)
1829 /* Defined in Table 35-10 from SDM (Sept 2015) */
1830 static int airmont_freq_table[] = {
1831 83300, 100000, 133300, 116700, 80000,
1832 93300, 90000, 88900, 87500};
1834 rdmsrl(MSR_FSB_FREQ, value);
1838 return airmont_freq_table[i];
1841 static void atom_get_vid(struct cpudata *cpudata)
1845 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1846 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1847 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1848 cpudata->vid.ratio = div_fp(
1849 cpudata->vid.max - cpudata->vid.min,
1850 int_tofp(cpudata->pstate.max_pstate -
1851 cpudata->pstate.min_pstate));
1853 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1854 cpudata->vid.turbo = value & 0x7f;
1857 static int core_get_min_pstate(int cpu)
1861 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1862 return (value >> 40) & 0xFF;
1865 static int core_get_max_pstate_physical(int cpu)
1869 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1870 return (value >> 8) & 0xFF;
1873 static int core_get_tdp_ratio(int cpu, u64 plat_info)
1875 /* Check how many TDP levels present */
1876 if (plat_info & 0x600000000) {
1882 /* Get the TDP level (0, 1, 2) to get ratios */
1883 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1887 /* TDP MSR are continuous starting at 0x648 */
1888 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1889 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio);
1893 /* For level 1 and 2, bits[23:16] contain the ratio */
1894 if (tdp_ctrl & 0x03)
1897 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1898 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1900 return (int)tdp_ratio;
1906 static int core_get_max_pstate(int cpu)
1914 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
1915 max_pstate = (plat_info >> 8) & 0xFF;
1917 tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
1922 /* Turbo activation ratio is not used on HWP platforms */
1926 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar);
1930 /* Do some sanity checking for safety */
1931 tar_levels = tar & 0xff;
1932 if (tdp_ratio - 1 == tar_levels) {
1933 max_pstate = tar_levels;
1934 pr_debug("max_pstate=TAC %x\n", max_pstate);
1941 static int core_get_turbo_pstate(int cpu)
1946 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1947 nont = core_get_max_pstate(cpu);
1948 ret = (value) & 255;
1954 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1958 val = (u64)pstate << 8;
1959 if (global.no_turbo && !global.turbo_disabled)
1960 val |= (u64)1 << 32;
1965 static int knl_get_aperf_mperf_shift(void)
1970 static int knl_get_turbo_pstate(int cpu)
1975 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1976 nont = core_get_max_pstate(cpu);
1977 ret = (((value) >> 8) & 0xFF);
1983 static void hybrid_get_type(void *data)
1985 u8 *cpu_type = data;
1987 *cpu_type = get_this_hybrid_cpu_type();
1990 static int hwp_get_cpu_scaling(int cpu)
1994 smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1);
1995 /* P-cores have a smaller perf level-to-freqency scaling factor. */
1996 if (cpu_type == 0x40)
1997 return hybrid_scaling_factor;
1999 /* Use default core scaling for E-cores */
2000 if (cpu_type == 0x20)
2001 return core_get_scaling();
2004 * If reached here, this system is either non-hybrid (like Tiger
2005 * Lake) or hybrid-capable (like Alder Lake or Raptor Lake) with
2006 * no E cores (in which case CPUID for hybrid support is 0).
2008 * The CPPC nominal_frequency field is 0 for non-hybrid systems,
2009 * so the default core scaling will be used for them.
2011 return intel_pstate_cppc_get_scaling(cpu);
2014 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
2016 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
2017 cpu->pstate.current_pstate = pstate;
2019 * Generally, there is no guarantee that this code will always run on
2020 * the CPU being updated, so force the register update to run on the
2023 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2024 pstate_funcs.get_val(cpu, pstate));
2027 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
2029 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
2032 static void intel_pstate_max_within_limits(struct cpudata *cpu)
2034 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
2036 update_turbo_state();
2037 intel_pstate_set_pstate(cpu, pstate);
2040 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
2042 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu);
2043 int perf_ctl_scaling = pstate_funcs.get_scaling();
2045 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu);
2046 cpu->pstate.max_pstate_physical = perf_ctl_max_phys;
2047 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
2049 if (hwp_active && !hwp_mode_bdw) {
2050 __intel_pstate_get_hwp_cap(cpu);
2052 if (pstate_funcs.get_cpu_scaling) {
2053 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
2054 if (cpu->pstate.scaling != perf_ctl_scaling)
2055 intel_pstate_hybrid_hwp_adjust(cpu);
2057 cpu->pstate.scaling = perf_ctl_scaling;
2060 cpu->pstate.scaling = perf_ctl_scaling;
2061 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu);
2062 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu);
2065 if (cpu->pstate.scaling == perf_ctl_scaling) {
2066 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2067 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2068 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2071 if (pstate_funcs.get_aperf_mperf_shift)
2072 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2074 if (pstate_funcs.get_vid)
2075 pstate_funcs.get_vid(cpu);
2077 intel_pstate_set_min_pstate(cpu);
2081 * Long hold time will keep high perf limits for long time,
2082 * which negatively impacts perf/watt for some workloads,
2083 * like specpower. 3ms is based on experiements on some
2086 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2088 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2090 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
2091 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2092 u32 max_limit = (hwp_req & 0xff00) >> 8;
2093 u32 min_limit = (hwp_req & 0xff);
2097 * Cases to consider (User changes via sysfs or boot time):
2098 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2100 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2101 * Should result in one level boost only for P0.
2102 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2103 * Should result in two level boost:
2104 * (min + p1)/2 and P1.
2105 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2106 * Should result in three level boost:
2107 * (min + p1)/2, P1 and P0.
2110 /* If max and min are equal or already at max, nothing to boost */
2111 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2114 if (!cpu->hwp_boost_min)
2115 cpu->hwp_boost_min = min_limit;
2117 /* level at half way mark between min and guranteed */
2118 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
2120 if (cpu->hwp_boost_min < boost_level1)
2121 cpu->hwp_boost_min = boost_level1;
2122 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2123 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2124 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2125 max_limit != HWP_GUARANTEED_PERF(hwp_cap))
2126 cpu->hwp_boost_min = max_limit;
2130 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2131 wrmsrl(MSR_HWP_REQUEST, hwp_req);
2132 cpu->last_update = cpu->sample.time;
2135 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2137 if (cpu->hwp_boost_min) {
2140 /* Check if we are idle for hold time to boost down */
2141 expired = time_after64(cpu->sample.time, cpu->last_update +
2142 hwp_boost_hold_time_ns);
2144 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
2145 cpu->hwp_boost_min = 0;
2148 cpu->last_update = cpu->sample.time;
2151 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2154 cpu->sample.time = time;
2156 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2159 cpu->sched_flags = 0;
2161 * Set iowait_boost flag and update time. Since IO WAIT flag
2162 * is set all the time, we can't just conclude that there is
2163 * some IO bound activity is scheduled on this CPU with just
2164 * one occurrence. If we receive at least two in two
2165 * consecutive ticks, then we treat as boost candidate.
2167 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2170 cpu->last_io_update = time;
2173 intel_pstate_hwp_boost_up(cpu);
2176 intel_pstate_hwp_boost_down(cpu);
2180 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2181 u64 time, unsigned int flags)
2183 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2185 cpu->sched_flags |= flags;
2187 if (smp_processor_id() == cpu->cpu)
2188 intel_pstate_update_util_hwp_local(cpu, time);
2191 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
2193 struct sample *sample = &cpu->sample;
2195 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
2198 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
2201 unsigned long flags;
2204 local_irq_save(flags);
2205 rdmsrl(MSR_IA32_APERF, aperf);
2206 rdmsrl(MSR_IA32_MPERF, mperf);
2208 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
2209 local_irq_restore(flags);
2212 local_irq_restore(flags);
2214 cpu->last_sample_time = cpu->sample.time;
2215 cpu->sample.time = time;
2216 cpu->sample.aperf = aperf;
2217 cpu->sample.mperf = mperf;
2218 cpu->sample.tsc = tsc;
2219 cpu->sample.aperf -= cpu->prev_aperf;
2220 cpu->sample.mperf -= cpu->prev_mperf;
2221 cpu->sample.tsc -= cpu->prev_tsc;
2223 cpu->prev_aperf = aperf;
2224 cpu->prev_mperf = mperf;
2225 cpu->prev_tsc = tsc;
2227 * First time this function is invoked in a given cycle, all of the
2228 * previous sample data fields are equal to zero or stale and they must
2229 * be populated with meaningful numbers for things to work, so assume
2230 * that sample.time will always be reset before setting the utilization
2231 * update hook and make the caller skip the sample then.
2233 if (cpu->last_sample_time) {
2234 intel_pstate_calc_avg_perf(cpu);
2240 static inline int32_t get_avg_frequency(struct cpudata *cpu)
2242 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
2245 static inline int32_t get_avg_pstate(struct cpudata *cpu)
2247 return mul_ext_fp(cpu->pstate.max_pstate_physical,
2248 cpu->sample.core_avg_perf);
2251 static inline int32_t get_target_pstate(struct cpudata *cpu)
2253 struct sample *sample = &cpu->sample;
2255 int target, avg_pstate;
2257 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
2260 if (busy_frac < cpu->iowait_boost)
2261 busy_frac = cpu->iowait_boost;
2263 sample->busy_scaled = busy_frac * 100;
2265 target = global.no_turbo || global.turbo_disabled ?
2266 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2267 target += target >> 2;
2268 target = mul_fp(target, busy_frac);
2269 if (target < cpu->pstate.min_pstate)
2270 target = cpu->pstate.min_pstate;
2273 * If the average P-state during the previous cycle was higher than the
2274 * current target, add 50% of the difference to the target to reduce
2275 * possible performance oscillations and offset possible performance
2276 * loss related to moving the workload from one CPU to another within
2279 avg_pstate = get_avg_pstate(cpu);
2280 if (avg_pstate > target)
2281 target += (avg_pstate - target) >> 1;
2286 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
2288 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2289 int max_pstate = max(min_pstate, cpu->max_perf_ratio);
2291 return clamp_t(int, pstate, min_pstate, max_pstate);
2294 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2296 if (pstate == cpu->pstate.current_pstate)
2299 cpu->pstate.current_pstate = pstate;
2300 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
2303 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
2305 int from = cpu->pstate.current_pstate;
2306 struct sample *sample;
2309 update_turbo_state();
2311 target_pstate = get_target_pstate(cpu);
2312 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2313 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
2314 intel_pstate_update_pstate(cpu, target_pstate);
2316 sample = &cpu->sample;
2317 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
2318 fp_toint(sample->busy_scaled),
2320 cpu->pstate.current_pstate,
2324 get_avg_frequency(cpu),
2325 fp_toint(cpu->iowait_boost * 100));
2328 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
2331 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2334 /* Don't allow remote callbacks */
2335 if (smp_processor_id() != cpu->cpu)
2338 delta_ns = time - cpu->last_update;
2339 if (flags & SCHED_CPUFREQ_IOWAIT) {
2340 /* Start over if the CPU may have been idle. */
2341 if (delta_ns > TICK_NSEC) {
2342 cpu->iowait_boost = ONE_EIGHTH_FP;
2343 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2344 cpu->iowait_boost <<= 1;
2345 if (cpu->iowait_boost > int_tofp(1))
2346 cpu->iowait_boost = int_tofp(1);
2348 cpu->iowait_boost = ONE_EIGHTH_FP;
2350 } else if (cpu->iowait_boost) {
2351 /* Clear iowait_boost if the CPU may have been idle. */
2352 if (delta_ns > TICK_NSEC)
2353 cpu->iowait_boost = 0;
2355 cpu->iowait_boost >>= 1;
2357 cpu->last_update = time;
2358 delta_ns = time - cpu->sample.time;
2359 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2362 if (intel_pstate_sample(cpu, time))
2363 intel_pstate_adjust_pstate(cpu);
2366 static struct pstate_funcs core_funcs = {
2367 .get_max = core_get_max_pstate,
2368 .get_max_physical = core_get_max_pstate_physical,
2369 .get_min = core_get_min_pstate,
2370 .get_turbo = core_get_turbo_pstate,
2371 .get_scaling = core_get_scaling,
2372 .get_val = core_get_val,
2375 static const struct pstate_funcs silvermont_funcs = {
2376 .get_max = atom_get_max_pstate,
2377 .get_max_physical = atom_get_max_pstate,
2378 .get_min = atom_get_min_pstate,
2379 .get_turbo = atom_get_turbo_pstate,
2380 .get_val = atom_get_val,
2381 .get_scaling = silvermont_get_scaling,
2382 .get_vid = atom_get_vid,
2385 static const struct pstate_funcs airmont_funcs = {
2386 .get_max = atom_get_max_pstate,
2387 .get_max_physical = atom_get_max_pstate,
2388 .get_min = atom_get_min_pstate,
2389 .get_turbo = atom_get_turbo_pstate,
2390 .get_val = atom_get_val,
2391 .get_scaling = airmont_get_scaling,
2392 .get_vid = atom_get_vid,
2395 static const struct pstate_funcs knl_funcs = {
2396 .get_max = core_get_max_pstate,
2397 .get_max_physical = core_get_max_pstate_physical,
2398 .get_min = core_get_min_pstate,
2399 .get_turbo = knl_get_turbo_pstate,
2400 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2401 .get_scaling = core_get_scaling,
2402 .get_val = core_get_val,
2405 #define X86_MATCH(model, policy) \
2406 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
2407 X86_FEATURE_APERFMPERF, &policy)
2409 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2410 X86_MATCH(SANDYBRIDGE, core_funcs),
2411 X86_MATCH(SANDYBRIDGE_X, core_funcs),
2412 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs),
2413 X86_MATCH(IVYBRIDGE, core_funcs),
2414 X86_MATCH(HASWELL, core_funcs),
2415 X86_MATCH(BROADWELL, core_funcs),
2416 X86_MATCH(IVYBRIDGE_X, core_funcs),
2417 X86_MATCH(HASWELL_X, core_funcs),
2418 X86_MATCH(HASWELL_L, core_funcs),
2419 X86_MATCH(HASWELL_G, core_funcs),
2420 X86_MATCH(BROADWELL_G, core_funcs),
2421 X86_MATCH(ATOM_AIRMONT, airmont_funcs),
2422 X86_MATCH(SKYLAKE_L, core_funcs),
2423 X86_MATCH(BROADWELL_X, core_funcs),
2424 X86_MATCH(SKYLAKE, core_funcs),
2425 X86_MATCH(BROADWELL_D, core_funcs),
2426 X86_MATCH(XEON_PHI_KNL, knl_funcs),
2427 X86_MATCH(XEON_PHI_KNM, knl_funcs),
2428 X86_MATCH(ATOM_GOLDMONT, core_funcs),
2429 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs),
2430 X86_MATCH(SKYLAKE_X, core_funcs),
2431 X86_MATCH(COMETLAKE, core_funcs),
2432 X86_MATCH(ICELAKE_X, core_funcs),
2433 X86_MATCH(TIGERLAKE, core_funcs),
2434 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs),
2435 X86_MATCH(EMERALDRAPIDS_X, core_funcs),
2438 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2440 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2441 X86_MATCH(BROADWELL_D, core_funcs),
2442 X86_MATCH(BROADWELL_X, core_funcs),
2443 X86_MATCH(SKYLAKE_X, core_funcs),
2444 X86_MATCH(ICELAKE_X, core_funcs),
2445 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs),
2449 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2450 X86_MATCH(KABYLAKE, core_funcs),
2454 static int intel_pstate_init_cpu(unsigned int cpunum)
2456 struct cpudata *cpu;
2458 cpu = all_cpu_data[cpunum];
2461 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2465 WRITE_ONCE(all_cpu_data[cpunum], cpu);
2469 cpu->epp_default = -EINVAL;
2472 intel_pstate_hwp_enable(cpu);
2474 if (intel_pstate_acpi_pm_profile_server())
2477 } else if (hwp_active) {
2479 * Re-enable HWP in case this happens after a resume from ACPI
2480 * S3 if the CPU was offline during the whole system/resume
2483 intel_pstate_hwp_reenable(cpu);
2486 cpu->epp_powersave = -EINVAL;
2487 cpu->epp_policy = 0;
2489 intel_pstate_get_cpu_pstates(cpu);
2491 pr_debug("controlling: cpu %d\n", cpunum);
2496 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2498 struct cpudata *cpu = all_cpu_data[cpu_num];
2500 if (hwp_active && !hwp_boost)
2503 if (cpu->update_util_set)
2506 /* Prevent intel_pstate_update_util() from using stale data. */
2507 cpu->sample.time = 0;
2508 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2510 intel_pstate_update_util_hwp :
2511 intel_pstate_update_util));
2512 cpu->update_util_set = true;
2515 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2517 struct cpudata *cpu_data = all_cpu_data[cpu];
2519 if (!cpu_data->update_util_set)
2522 cpufreq_remove_update_util_hook(cpu);
2523 cpu_data->update_util_set = false;
2527 static int intel_pstate_get_max_freq(struct cpudata *cpu)
2529 return global.turbo_disabled || global.no_turbo ?
2530 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2533 static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2534 unsigned int policy_min,
2535 unsigned int policy_max)
2537 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
2538 int32_t max_policy_perf, min_policy_perf;
2540 max_policy_perf = policy_max / perf_ctl_scaling;
2541 if (policy_max == policy_min) {
2542 min_policy_perf = max_policy_perf;
2544 min_policy_perf = policy_min / perf_ctl_scaling;
2545 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2546 0, max_policy_perf);
2550 * HWP needs some special consideration, because HWP_REQUEST uses
2551 * abstract values to represent performance rather than pure ratios.
2553 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
2556 freq = max_policy_perf * perf_ctl_scaling;
2557 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2558 freq = min_policy_perf * perf_ctl_scaling;
2559 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2562 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2563 cpu->cpu, min_policy_perf, max_policy_perf);
2565 /* Normalize user input to [min_perf, max_perf] */
2566 if (per_cpu_limits) {
2567 cpu->min_perf_ratio = min_policy_perf;
2568 cpu->max_perf_ratio = max_policy_perf;
2570 int turbo_max = cpu->pstate.turbo_pstate;
2571 int32_t global_min, global_max;
2573 /* Global limits are in percent of the maximum turbo P-state. */
2574 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2575 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2576 global_min = clamp_t(int32_t, global_min, 0, global_max);
2578 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2579 global_min, global_max);
2581 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2582 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2583 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2584 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2586 /* Make sure min_perf <= max_perf */
2587 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2588 cpu->max_perf_ratio);
2591 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2592 cpu->max_perf_ratio,
2593 cpu->min_perf_ratio);
2596 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2598 struct cpudata *cpu;
2600 if (!policy->cpuinfo.max_freq)
2603 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2604 policy->cpuinfo.max_freq, policy->max);
2606 cpu = all_cpu_data[policy->cpu];
2607 cpu->policy = policy->policy;
2609 mutex_lock(&intel_pstate_limits_lock);
2611 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2613 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2615 * NOHZ_FULL CPUs need this as the governor callback may not
2616 * be invoked on them.
2618 intel_pstate_clear_update_util_hook(policy->cpu);
2619 intel_pstate_max_within_limits(cpu);
2621 intel_pstate_set_update_util_hook(policy->cpu);
2626 * When hwp_boost was active before and dynamically it
2627 * was turned off, in that case we need to clear the
2631 intel_pstate_clear_update_util_hook(policy->cpu);
2632 intel_pstate_hwp_set(policy->cpu);
2635 * policy->cur is never updated with the intel_pstate driver, but it
2636 * is used as a stale frequency value. So, keep it within limits.
2638 policy->cur = policy->min;
2640 mutex_unlock(&intel_pstate_limits_lock);
2645 static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2646 struct cpufreq_policy_data *policy)
2649 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2650 policy->max < policy->cpuinfo.max_freq &&
2651 policy->max > cpu->pstate.max_freq) {
2652 pr_debug("policy->max > max non turbo frequency\n");
2653 policy->max = policy->cpuinfo.max_freq;
2657 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2658 struct cpufreq_policy_data *policy)
2662 update_turbo_state();
2664 intel_pstate_get_hwp_cap(cpu);
2665 max_freq = global.no_turbo || global.turbo_disabled ?
2666 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2668 max_freq = intel_pstate_get_max_freq(cpu);
2670 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2672 intel_pstate_adjust_policy_max(cpu, policy);
2675 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2677 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2682 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
2684 struct cpudata *cpu = all_cpu_data[policy->cpu];
2686 pr_debug("CPU %d going offline\n", cpu->cpu);
2692 * If the CPU is an SMT thread and it goes offline with the performance
2693 * settings different from the minimum, it will prevent its sibling
2694 * from getting to lower performance levels, so force the minimum
2695 * performance on CPU offline to prevent that from happening.
2698 intel_pstate_hwp_offline(cpu);
2700 intel_pstate_set_min_pstate(cpu);
2702 intel_pstate_exit_perf_limits(policy);
2707 static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2709 struct cpudata *cpu = all_cpu_data[policy->cpu];
2711 pr_debug("CPU %d going online\n", cpu->cpu);
2713 intel_pstate_init_acpi_perf_limits(policy);
2717 * Re-enable HWP and clear the "suspended" flag to let "resume"
2718 * know that it need not do that.
2720 intel_pstate_hwp_reenable(cpu);
2721 cpu->suspended = false;
2727 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2729 intel_pstate_clear_update_util_hook(policy->cpu);
2731 return intel_cpufreq_cpu_offline(policy);
2734 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2736 pr_debug("CPU %d exiting\n", policy->cpu);
2738 policy->fast_switch_possible = false;
2743 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2745 struct cpudata *cpu;
2748 rc = intel_pstate_init_cpu(policy->cpu);
2752 cpu = all_cpu_data[policy->cpu];
2754 cpu->max_perf_ratio = 0xFF;
2755 cpu->min_perf_ratio = 0;
2757 /* cpuinfo and default policy values */
2758 policy->cpuinfo.min_freq = cpu->pstate.min_freq;
2759 update_turbo_state();
2760 global.turbo_disabled_mf = global.turbo_disabled;
2761 policy->cpuinfo.max_freq = global.turbo_disabled ?
2762 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2764 policy->min = policy->cpuinfo.min_freq;
2765 policy->max = policy->cpuinfo.max_freq;
2767 intel_pstate_init_acpi_perf_limits(policy);
2769 policy->fast_switch_possible = true;
2774 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2776 int ret = __intel_pstate_cpu_init(policy);
2782 * Set the policy to powersave to provide a valid fallback value in case
2783 * the default cpufreq governor is neither powersave nor performance.
2785 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2788 struct cpudata *cpu = all_cpu_data[policy->cpu];
2790 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
2796 static struct cpufreq_driver intel_pstate = {
2797 .flags = CPUFREQ_CONST_LOOPS,
2798 .verify = intel_pstate_verify_policy,
2799 .setpolicy = intel_pstate_set_policy,
2800 .suspend = intel_pstate_suspend,
2801 .resume = intel_pstate_resume,
2802 .init = intel_pstate_cpu_init,
2803 .exit = intel_pstate_cpu_exit,
2804 .offline = intel_pstate_cpu_offline,
2805 .online = intel_pstate_cpu_online,
2806 .update_limits = intel_pstate_update_limits,
2807 .name = "intel_pstate",
2810 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
2812 struct cpudata *cpu = all_cpu_data[policy->cpu];
2814 intel_pstate_verify_cpu_policy(cpu, policy);
2815 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2820 /* Use of trace in passive mode:
2822 * In passive mode the trace core_busy field (also known as the
2823 * performance field, and lablelled as such on the graphs; also known as
2824 * core_avg_perf) is not needed and so is re-assigned to indicate if the
2825 * driver call was via the normal or fast switch path. Various graphs
2826 * output from the intel_pstate_tracer.py utility that include core_busy
2827 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2828 * so we use 10 to indicate the normal path through the driver, and
2829 * 90 to indicate the fast switch path through the driver.
2830 * The scaled_busy field is not used, and is set to 0.
2833 #define INTEL_PSTATE_TRACE_TARGET 10
2834 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2836 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2838 struct sample *sample;
2840 if (!trace_pstate_sample_enabled())
2843 if (!intel_pstate_sample(cpu, ktime_get()))
2846 sample = &cpu->sample;
2847 trace_pstate_sample(trace_type,
2850 cpu->pstate.current_pstate,
2854 get_avg_frequency(cpu),
2855 fp_toint(cpu->iowait_boost * 100));
2858 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
2859 u32 desired, bool fast_switch)
2861 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
2863 value &= ~HWP_MIN_PERF(~0L);
2864 value |= HWP_MIN_PERF(min);
2866 value &= ~HWP_MAX_PERF(~0L);
2867 value |= HWP_MAX_PERF(max);
2869 value &= ~HWP_DESIRED_PERF(~0L);
2870 value |= HWP_DESIRED_PERF(desired);
2875 WRITE_ONCE(cpu->hwp_req_cached, value);
2877 wrmsrl(MSR_HWP_REQUEST, value);
2879 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
2882 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
2883 u32 target_pstate, bool fast_switch)
2886 wrmsrl(MSR_IA32_PERF_CTL,
2887 pstate_funcs.get_val(cpu, target_pstate));
2889 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2890 pstate_funcs.get_val(cpu, target_pstate));
2893 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
2894 int target_pstate, bool fast_switch)
2896 struct cpudata *cpu = all_cpu_data[policy->cpu];
2897 int old_pstate = cpu->pstate.current_pstate;
2899 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2901 int max_pstate = policy->strict_target ?
2902 target_pstate : cpu->max_perf_ratio;
2904 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0,
2906 } else if (target_pstate != old_pstate) {
2907 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
2910 cpu->pstate.current_pstate = target_pstate;
2912 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
2913 INTEL_PSTATE_TRACE_TARGET, old_pstate);
2915 return target_pstate;
2918 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2919 unsigned int target_freq,
2920 unsigned int relation)
2922 struct cpudata *cpu = all_cpu_data[policy->cpu];
2923 struct cpufreq_freqs freqs;
2926 update_turbo_state();
2928 freqs.old = policy->cur;
2929 freqs.new = target_freq;
2931 cpufreq_freq_transition_begin(policy, &freqs);
2933 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation);
2934 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
2936 freqs.new = target_pstate * cpu->pstate.scaling;
2938 cpufreq_freq_transition_end(policy, &freqs, false);
2943 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2944 unsigned int target_freq)
2946 struct cpudata *cpu = all_cpu_data[policy->cpu];
2949 update_turbo_state();
2951 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq);
2953 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
2955 return target_pstate * cpu->pstate.scaling;
2958 static void intel_cpufreq_adjust_perf(unsigned int cpunum,
2959 unsigned long min_perf,
2960 unsigned long target_perf,
2961 unsigned long capacity)
2963 struct cpudata *cpu = all_cpu_data[cpunum];
2964 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2965 int old_pstate = cpu->pstate.current_pstate;
2966 int cap_pstate, min_pstate, max_pstate, target_pstate;
2968 update_turbo_state();
2969 cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) :
2970 HWP_HIGHEST_PERF(hwp_cap);
2972 /* Optimization: Avoid unnecessary divisions. */
2974 target_pstate = cap_pstate;
2975 if (target_perf < capacity)
2976 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
2978 min_pstate = cap_pstate;
2979 if (min_perf < capacity)
2980 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
2982 if (min_pstate < cpu->pstate.min_pstate)
2983 min_pstate = cpu->pstate.min_pstate;
2985 if (min_pstate < cpu->min_perf_ratio)
2986 min_pstate = cpu->min_perf_ratio;
2988 if (min_pstate > cpu->max_perf_ratio)
2989 min_pstate = cpu->max_perf_ratio;
2991 max_pstate = min(cap_pstate, cpu->max_perf_ratio);
2992 if (max_pstate < min_pstate)
2993 max_pstate = min_pstate;
2995 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
2997 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true);
2999 cpu->pstate.current_pstate = target_pstate;
3000 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
3003 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
3005 struct freq_qos_request *req;
3006 struct cpudata *cpu;
3010 dev = get_cpu_device(policy->cpu);
3014 ret = __intel_pstate_cpu_init(policy);
3018 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
3019 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
3020 policy->cur = policy->cpuinfo.min_freq;
3022 req = kcalloc(2, sizeof(*req), GFP_KERNEL);
3028 cpu = all_cpu_data[policy->cpu];
3033 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
3035 intel_pstate_get_hwp_cap(cpu);
3037 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
3038 WRITE_ONCE(cpu->hwp_req_cached, value);
3040 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
3042 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
3045 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
3047 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
3050 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
3054 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
3056 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
3059 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3060 goto remove_min_req;
3063 policy->driver_data = req;
3068 freq_qos_remove_request(req);
3072 intel_pstate_exit_perf_limits(policy);
3077 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3079 struct freq_qos_request *req;
3081 req = policy->driver_data;
3083 freq_qos_remove_request(req + 1);
3084 freq_qos_remove_request(req);
3087 return intel_pstate_cpu_exit(policy);
3090 static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3092 intel_pstate_suspend(policy);
3095 struct cpudata *cpu = all_cpu_data[policy->cpu];
3096 u64 value = READ_ONCE(cpu->hwp_req_cached);
3099 * Clear the desired perf field in MSR_HWP_REQUEST in case
3100 * intel_cpufreq_adjust_perf() is in use and the last value
3101 * written by it may not be suitable.
3103 value &= ~HWP_DESIRED_PERF(~0L);
3104 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3105 WRITE_ONCE(cpu->hwp_req_cached, value);
3111 static struct cpufreq_driver intel_cpufreq = {
3112 .flags = CPUFREQ_CONST_LOOPS,
3113 .verify = intel_cpufreq_verify_policy,
3114 .target = intel_cpufreq_target,
3115 .fast_switch = intel_cpufreq_fast_switch,
3116 .init = intel_cpufreq_cpu_init,
3117 .exit = intel_cpufreq_cpu_exit,
3118 .offline = intel_cpufreq_cpu_offline,
3119 .online = intel_pstate_cpu_online,
3120 .suspend = intel_cpufreq_suspend,
3121 .resume = intel_pstate_resume,
3122 .update_limits = intel_pstate_update_limits,
3123 .name = "intel_cpufreq",
3126 static struct cpufreq_driver *default_driver;
3128 static void intel_pstate_driver_cleanup(void)
3133 for_each_online_cpu(cpu) {
3134 if (all_cpu_data[cpu]) {
3135 if (intel_pstate_driver == &intel_pstate)
3136 intel_pstate_clear_update_util_hook(cpu);
3138 spin_lock(&hwp_notify_lock);
3139 kfree(all_cpu_data[cpu]);
3140 WRITE_ONCE(all_cpu_data[cpu], NULL);
3141 spin_unlock(&hwp_notify_lock);
3146 intel_pstate_driver = NULL;
3149 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
3153 if (driver == &intel_pstate)
3154 intel_pstate_sysfs_expose_hwp_dynamic_boost();
3156 memset(&global, 0, sizeof(global));
3157 global.max_perf_pct = 100;
3159 intel_pstate_driver = driver;
3160 ret = cpufreq_register_driver(intel_pstate_driver);
3162 intel_pstate_driver_cleanup();
3166 global.min_perf_pct = min_perf_pct_min();
3171 static ssize_t intel_pstate_show_status(char *buf)
3173 if (!intel_pstate_driver)
3174 return sprintf(buf, "off\n");
3176 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
3177 "active" : "passive");
3180 static int intel_pstate_update_status(const char *buf, size_t size)
3182 if (size == 3 && !strncmp(buf, "off", size)) {
3183 if (!intel_pstate_driver)
3189 cpufreq_unregister_driver(intel_pstate_driver);
3190 intel_pstate_driver_cleanup();
3194 if (size == 6 && !strncmp(buf, "active", size)) {
3195 if (intel_pstate_driver) {
3196 if (intel_pstate_driver == &intel_pstate)
3199 cpufreq_unregister_driver(intel_pstate_driver);
3202 return intel_pstate_register_driver(&intel_pstate);
3205 if (size == 7 && !strncmp(buf, "passive", size)) {
3206 if (intel_pstate_driver) {
3207 if (intel_pstate_driver == &intel_cpufreq)
3210 cpufreq_unregister_driver(intel_pstate_driver);
3211 intel_pstate_sysfs_hide_hwp_dynamic_boost();
3214 return intel_pstate_register_driver(&intel_cpufreq);
3220 static int no_load __initdata;
3221 static int no_hwp __initdata;
3222 static int hwp_only __initdata;
3223 static unsigned int force_load __initdata;
3225 static int __init intel_pstate_msrs_not_valid(void)
3227 if (!pstate_funcs.get_max(0) ||
3228 !pstate_funcs.get_min(0) ||
3229 !pstate_funcs.get_turbo(0))
3235 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
3237 pstate_funcs.get_max = funcs->get_max;
3238 pstate_funcs.get_max_physical = funcs->get_max_physical;
3239 pstate_funcs.get_min = funcs->get_min;
3240 pstate_funcs.get_turbo = funcs->get_turbo;
3241 pstate_funcs.get_scaling = funcs->get_scaling;
3242 pstate_funcs.get_val = funcs->get_val;
3243 pstate_funcs.get_vid = funcs->get_vid;
3244 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
3249 static bool __init intel_pstate_no_acpi_pss(void)
3253 for_each_possible_cpu(i) {
3255 union acpi_object *pss;
3256 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3257 struct acpi_processor *pr = per_cpu(processors, i);
3262 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
3263 if (ACPI_FAILURE(status))
3266 pss = buffer.pointer;
3267 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3275 pr_debug("ACPI _PSS not found\n");
3279 static bool __init intel_pstate_no_acpi_pcch(void)
3284 status = acpi_get_handle(NULL, "\\_SB", &handle);
3285 if (ACPI_FAILURE(status))
3288 if (acpi_has_method(handle, "PCCH"))
3292 pr_debug("ACPI PCCH not found\n");
3296 static bool __init intel_pstate_has_acpi_ppc(void)
3300 for_each_possible_cpu(i) {
3301 struct acpi_processor *pr = per_cpu(processors, i);
3305 if (acpi_has_method(pr->handle, "_PPC"))
3308 pr_debug("ACPI _PPC not found\n");
3317 /* Hardware vendor-specific info that has its own power management modes */
3318 static struct acpi_platform_list plat_info[] __initdata = {
3319 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3320 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3321 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3322 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3323 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3324 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3325 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3326 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3327 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3328 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3329 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3330 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3331 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3332 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3333 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3337 #define BITMASK_OOB (BIT(8) | BIT(18))
3339 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
3341 const struct x86_cpu_id *id;
3345 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3347 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
3348 if (misc_pwr & BITMASK_OOB) {
3349 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3350 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3355 idx = acpi_match_platform_list(plat_info);
3359 switch (plat_info[idx].data) {
3361 if (!intel_pstate_no_acpi_pss())
3364 return intel_pstate_no_acpi_pcch();
3366 return intel_pstate_has_acpi_ppc() && !force_load;
3372 static void intel_pstate_request_control_from_smm(void)
3375 * It may be unsafe to request P-states control from SMM if _PPC support
3376 * has not been enabled.
3379 acpi_processor_pstate_control();
3381 #else /* CONFIG_ACPI not enabled */
3382 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
3383 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
3384 static inline void intel_pstate_request_control_from_smm(void) {}
3385 #endif /* CONFIG_ACPI */
3387 #define INTEL_PSTATE_HWP_BROADWELL 0x01
3389 #define X86_MATCH_HWP(model, hwp_mode) \
3390 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
3391 X86_FEATURE_HWP, hwp_mode)
3393 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3394 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
3395 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL),
3396 X86_MATCH_HWP(ANY, 0),
3400 static bool intel_pstate_hwp_is_enabled(void)
3404 rdmsrl(MSR_PM_ENABLE, value);
3405 return !!(value & 0x1);
3408 #define POWERSAVE_MASK GENMASK(7, 0)
3409 #define BALANCE_POWER_MASK GENMASK(15, 8)
3410 #define BALANCE_PERFORMANCE_MASK GENMASK(23, 16)
3411 #define PERFORMANCE_MASK GENMASK(31, 24)
3413 #define HWP_SET_EPP_VALUES(powersave, balance_power, balance_perf, performance) \
3414 (FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\
3415 FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\
3416 FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\
3417 FIELD_PREP_CONST(PERFORMANCE_MASK, performance))
3419 #define HWP_SET_DEF_BALANCE_PERF_EPP(balance_perf) \
3420 (HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, HWP_EPP_BALANCE_POWERSAVE,\
3421 balance_perf, HWP_EPP_PERFORMANCE))
3423 static const struct x86_cpu_id intel_epp_default[] = {
3425 * Set EPP value as 102, this is the max suggested EPP
3426 * which can result in one core turbo frequency for
3427 * AlderLake Mobile CPUs.
3429 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, HWP_SET_DEF_BALANCE_PERF_EPP(102)),
3430 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3431 X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE,
3432 HWP_EPP_BALANCE_POWERSAVE, 115, 16)),
3436 static const struct x86_cpu_id intel_hybrid_scaling_factor[] = {
3437 X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL),
3441 static int __init intel_pstate_init(void)
3443 static struct cpudata **_all_cpu_data;
3444 const struct x86_cpu_id *id;
3447 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3450 id = x86_match_cpu(hwp_support_ids);
3452 hwp_forced = intel_pstate_hwp_is_enabled();
3455 pr_info("HWP enabled by BIOS\n");
3459 copy_cpu_funcs(&core_funcs);
3461 * Avoid enabling HWP for processors without EPP support,
3462 * because that means incomplete HWP implementation which is a
3463 * corner case and supporting it is generally problematic.
3465 * If HWP is enabled already, though, there is no choice but to
3468 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
3469 WRITE_ONCE(hwp_active, 1);
3470 hwp_mode_bdw = id->driver_data;
3471 intel_pstate.attr = hwp_cpufreq_attrs;
3472 intel_cpufreq.attr = hwp_cpufreq_attrs;
3473 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3474 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3475 if (!default_driver)
3476 default_driver = &intel_pstate;
3478 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling;
3480 goto hwp_cpu_matched;
3482 pr_info("HWP not enabled\n");
3487 id = x86_match_cpu(intel_pstate_cpu_ids);
3489 pr_info("CPU model not supported\n");
3493 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3496 if (intel_pstate_msrs_not_valid()) {
3497 pr_info("Invalid MSRs\n");
3500 /* Without HWP start in the passive mode. */
3501 if (!default_driver)
3502 default_driver = &intel_cpufreq;
3506 * The Intel pstate driver will be ignored if the platform
3507 * firmware has its own power management modes.
3509 if (intel_pstate_platform_pwr_mgmt_exists()) {
3510 pr_info("P-states controlled by the platform\n");
3514 if (!hwp_active && hwp_only)
3517 pr_info("Intel P-state driver initializing\n");
3519 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3523 WRITE_ONCE(all_cpu_data, _all_cpu_data);
3525 intel_pstate_request_control_from_smm();
3527 intel_pstate_sysfs_expose_params();
3530 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_default);
3531 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor);
3534 epp_values[EPP_INDEX_POWERSAVE] =
3535 FIELD_GET(POWERSAVE_MASK, id->driver_data);
3536 epp_values[EPP_INDEX_BALANCE_POWERSAVE] =
3537 FIELD_GET(BALANCE_POWER_MASK, id->driver_data);
3538 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] =
3539 FIELD_GET(BALANCE_PERFORMANCE_MASK, id->driver_data);
3540 epp_values[EPP_INDEX_PERFORMANCE] =
3541 FIELD_GET(PERFORMANCE_MASK, id->driver_data);
3542 pr_debug("Updated EPPs powersave:%x balanced power:%x balanced perf:%x performance:%x\n",
3543 epp_values[EPP_INDEX_POWERSAVE],
3544 epp_values[EPP_INDEX_BALANCE_POWERSAVE],
3545 epp_values[EPP_INDEX_BALANCE_PERFORMANCE],
3546 epp_values[EPP_INDEX_PERFORMANCE]);
3550 hybrid_scaling_factor = hybrid_id->driver_data;
3551 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor);
3556 mutex_lock(&intel_pstate_driver_lock);
3557 rc = intel_pstate_register_driver(default_driver);
3558 mutex_unlock(&intel_pstate_driver_lock);
3560 intel_pstate_sysfs_remove();
3565 const struct x86_cpu_id *id;
3567 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3569 set_power_ctl_ee_state(false);
3570 pr_info("Disabling energy efficiency optimization\n");
3573 pr_info("HWP enabled\n");
3574 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3575 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
3580 device_initcall(intel_pstate_init);
3582 static int __init intel_pstate_setup(char *str)
3587 if (!strcmp(str, "disable"))
3589 else if (!strcmp(str, "active"))
3590 default_driver = &intel_pstate;
3591 else if (!strcmp(str, "passive"))
3592 default_driver = &intel_cpufreq;
3594 if (!strcmp(str, "no_hwp"))
3597 if (!strcmp(str, "force"))
3599 if (!strcmp(str, "hwp_only"))
3601 if (!strcmp(str, "per_cpu_perf_limits"))
3602 per_cpu_limits = true;
3605 if (!strcmp(str, "support_acpi_ppc"))
3611 early_param("intel_pstate", intel_pstate_setup);
3613 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3614 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");