drivers/cpufreq/intel_pstate.c

   1 /*
   2  * intel_pstate.c: Native P state management for Intel processors
   3  *
   4  * (C) Copyright 2012 Intel Corporation
   5  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; version 2
  10  * of the License.
  11  */
  12
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/kernel_stat.h>
  17 #include <linux/module.h>
  18 #include <linux/ktime.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/tick.h>
  21 #include <linux/slab.h>
  22 #include <linux/sched.h>
  23 #include <linux/list.h>
  24 #include <linux/cpu.h>
  25 #include <linux/cpufreq.h>
  26 #include <linux/sysfs.h>
  27 #include <linux/types.h>
  28 #include <linux/fs.h>
  29 #include <linux/debugfs.h>
  30 #include <linux/acpi.h>
  31 #include <linux/vmalloc.h>
  32 #include <trace/events/power.h>
  33
  34 #include <asm/div64.h>
  35 #include <asm/msr.h>
  36 #include <asm/cpu_device_id.h>
  37 #include <asm/cpufeature.h>
  38 #include <asm/intel-family.h>
  39
  40 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
  41
  42 #define ATOM_RATIOS             0x66a
  43 #define ATOM_VIDS               0x66b
  44 #define ATOM_TURBO_RATIOS       0x66c
  45 #define ATOM_TURBO_VIDS         0x66d
  46
  47 #ifdef CONFIG_ACPI
  48 #include <acpi/processor.h>
  49 #endif
  50
  51 #define FRAC_BITS 8
  52 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  53 #define fp_toint(X) ((X) >> FRAC_BITS)
  54
  55 #define EXT_BITS 6
  56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
  57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
  58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
  59
  60 static inline int32_t mul_fp(int32_t x, int32_t y)
  61 {
  62         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  63 }
  64
  65 static inline int32_t div_fp(s64 x, s64 y)
  66 {
  67         return div64_s64((int64_t)x << FRAC_BITS, y);
  68 }
  69
  70 static inline int ceiling_fp(int32_t x)
  71 {
  72         int mask, ret;
  73
  74         ret = fp_toint(x);
  75         mask = (1 << FRAC_BITS) - 1;
  76         if (x & mask)
  77                 ret += 1;
  78         return ret;
  79 }
  80
  81 static inline u64 mul_ext_fp(u64 x, u64 y)
  82 {
  83         return (x * y) >> EXT_FRAC_BITS;
  84 }
  85
  86 static inline u64 div_ext_fp(u64 x, u64 y)
  87 {
  88         return div64_u64(x << EXT_FRAC_BITS, y);
  89 }
  90
  91 /**
  92  * struct sample -      Store performance sample
  93  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
  94  *                      performance during last sample period
  95  * @busy_scaled:        Scaled busy value which is used to calculate next
  96  *                      P state. This can be different than core_avg_perf
  97  *                      to account for cpu idle period
  98  * @aperf:              Difference of actual performance frequency clock count
  99  *                      read from APERF MSR between last and current sample
 100  * @mperf:              Difference of maximum performance frequency clock count
 101  *                      read from MPERF MSR between last and current sample
 102  * @tsc:                Difference of time stamp counter between last and
 103  *                      current sample
 104  * @time:               Current time from scheduler
 105  *
 106  * This structure is used in the cpudata structure to store performance sample
 107  * data for choosing next P State.
 108  */
 109 struct sample {
 110         int32_t core_avg_perf;
 111         int32_t busy_scaled;
 112         u64 aperf;
 113         u64 mperf;
 114         u64 tsc;
 115         u64 time;
 116 };
 117
 118 /**
 119  * struct pstate_data - Store P state data
 120  * @current_pstate:     Current requested P state
 121  * @min_pstate:         Min P state possible for this platform
 122  * @max_pstate:         Max P state possible for this platform
 123  * @max_pstate_physical:This is physical Max P state for a processor
 124  *                      This can be higher than the max_pstate which can
 125  *                      be limited by platform thermal design power limits
 126  * @scaling:            Scaling factor to  convert frequency to cpufreq
 127  *                      frequency units
 128  * @turbo_pstate:       Max Turbo P state possible for this platform
 129  * @max_freq:           @max_pstate frequency in cpufreq units
 130  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
 131  *
 132  * Stores the per cpu model P state limits and current P state.
 133  */
 134 struct pstate_data {
 135         int     current_pstate;
 136         int     min_pstate;
 137         int     max_pstate;
 138         int     max_pstate_physical;
 139         int     scaling;
 140         int     turbo_pstate;
 141         unsigned int max_freq;
 142         unsigned int turbo_freq;
 143 };
 144
 145 /**
 146  * struct vid_data -    Stores voltage information data
 147  * @min:                VID data for this platform corresponding to
 148  *                      the lowest P state
 149  * @max:                VID data corresponding to the highest P State.
 150  * @turbo:              VID data for turbo P state
 151  * @ratio:              Ratio of (vid max - vid min) /
 152  *                      (max P state - Min P State)
 153  *
 154  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 155  * This data is used in Atom platforms, where in addition to target P state,
 156  * the voltage data needs to be specified to select next P State.
 157  */
 158 struct vid_data {
 159         int min;
 160         int max;
 161         int turbo;
 162         int32_t ratio;
 163 };
 164
 165 /**
 166  * struct _pid -        Stores PID data
 167  * @setpoint:           Target set point for busyness or performance
 168  * @integral:           Storage for accumulated error values
 169  * @p_gain:             PID proportional gain
 170  * @i_gain:             PID integral gain
 171  * @d_gain:             PID derivative gain
 172  * @deadband:           PID deadband
 173  * @last_err:           Last error storage for integral part of PID calculation
 174  *
 175  * Stores PID coefficients and last error for PID controller.
 176  */
 177 struct _pid {
 178         int setpoint;
 179         int32_t integral;
 180         int32_t p_gain;
 181         int32_t i_gain;
 182         int32_t d_gain;
 183         int deadband;
 184         int32_t last_err;
 185 };
 186
 187 /**
 188  * struct perf_limits - Store user and policy limits
 189  * @no_turbo:           User requested turbo state from intel_pstate sysfs
 190  * @turbo_disabled:     Platform turbo status either from msr
 191  *                      MSR_IA32_MISC_ENABLE or when maximum available pstate
 192  *                      matches the maximum turbo pstate
 193  * @max_perf_pct:       Effective maximum performance limit in percentage, this
 194  *                      is minimum of either limits enforced by cpufreq policy
 195  *                      or limits from user set limits via intel_pstate sysfs
 196  * @min_perf_pct:       Effective minimum performance limit in percentage, this
 197  *                      is maximum of either limits enforced by cpufreq policy
 198  *                      or limits from user set limits via intel_pstate sysfs
 199  * @max_perf:           This is a scaled value between 0 to 255 for max_perf_pct
 200  *                      This value is used to limit max pstate
 201  * @min_perf:           This is a scaled value between 0 to 255 for min_perf_pct
 202  *                      This value is used to limit min pstate
 203  * @max_policy_pct:     The maximum performance in percentage enforced by
 204  *                      cpufreq setpolicy interface
 205  * @max_sysfs_pct:      The maximum performance in percentage enforced by
 206  *                      intel pstate sysfs interface, unused when per cpu
 207  *                      controls are enforced
 208  * @min_policy_pct:     The minimum performance in percentage enforced by
 209  *                      cpufreq setpolicy interface
 210  * @min_sysfs_pct:      The minimum performance in percentage enforced by
 211  *                      intel pstate sysfs interface, unused when per cpu
 212  *                      controls are enforced
 213  *
 214  * Storage for user and policy defined limits.
 215  */
 216 struct perf_limits {
 217         int no_turbo;
 218         int turbo_disabled;
 219         int max_perf_pct;
 220         int min_perf_pct;
 221         int32_t max_perf;
 222         int32_t min_perf;
 223         int max_policy_pct;
 224         int max_sysfs_pct;
 225         int min_policy_pct;
 226         int min_sysfs_pct;
 227 };
 228
 229 /**
 230  * struct cpudata -     Per CPU instance data storage
 231  * @cpu:                CPU number for this instance data
 232  * @policy:             CPUFreq policy value
 233  * @update_util:        CPUFreq utility callback information
 234  * @update_util_set:    CPUFreq utility callback is set
 235  * @iowait_boost:       iowait-related boost fraction
 236  * @last_update:        Time of the last update.
 237  * @pstate:             Stores P state limits for this CPU
 238  * @vid:                Stores VID limits for this CPU
 239  * @pid:                Stores PID parameters for this CPU
 240  * @last_sample_time:   Last Sample time
 241  * @prev_aperf:         Last APERF value read from APERF MSR
 242  * @prev_mperf:         Last MPERF value read from MPERF MSR
 243  * @prev_tsc:           Last timestamp counter (TSC) value
 244  * @prev_cummulative_iowait: IO Wait time difference from last and
 245  *                      current sample
 246  * @sample:             Storage for storing last Sample data
 247  * @perf_limits:        Pointer to perf_limit unique to this CPU
 248  *                      Not all field in the structure are applicable
 249  *                      when per cpu controls are enforced
 250  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
 251  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
 252  * @epp_powersave:      Last saved HWP energy performance preference
 253  *                      (EPP) or energy performance bias (EPB),
 254  *                      when policy switched to performance
 255  * @epp_policy:         Last saved policy used to set EPP/EPB
 256  * @epp_default:        Power on default HWP energy performance
 257  *                      preference/bias
 258  * @epp_saved:          Saved EPP/EPB during system suspend or CPU offline
 259  *                      operation
 260  *
 261  * This structure stores per CPU instance data for all CPUs.
 262  */
 263 struct cpudata {
 264         int cpu;
 265
 266         unsigned int policy;
 267         struct update_util_data update_util;
 268         bool   update_util_set;
 269
 270         struct pstate_data pstate;
 271         struct vid_data vid;
 272         struct _pid pid;
 273
 274         u64     last_update;
 275         u64     last_sample_time;
 276         u64     prev_aperf;
 277         u64     prev_mperf;
 278         u64     prev_tsc;
 279         u64     prev_cummulative_iowait;
 280         struct sample sample;
 281         struct perf_limits *perf_limits;
 282 #ifdef CONFIG_ACPI
 283         struct acpi_processor_performance acpi_perf_data;
 284         bool valid_pss_table;
 285 #endif
 286         unsigned int iowait_boost;
 287         s16 epp_powersave;
 288         s16 epp_policy;
 289         s16 epp_default;
 290         s16 epp_saved;
 291 };
 292
 293 static struct cpudata **all_cpu_data;
 294
 295 /**
 296  * struct pstate_adjust_policy - Stores static PID configuration data
 297  * @sample_rate_ms:     PID calculation sample rate in ms
 298  * @sample_rate_ns:     Sample rate calculation in ns
 299  * @deadband:           PID deadband
 300  * @setpoint:           PID Setpoint
 301  * @p_gain_pct:         PID proportional gain
 302  * @i_gain_pct:         PID integral gain
 303  * @d_gain_pct:         PID derivative gain
 304  *
 305  * Stores per CPU model static PID configuration data.
 306  */
 307 struct pstate_adjust_policy {
 308         int sample_rate_ms;
 309         s64 sample_rate_ns;
 310         int deadband;
 311         int setpoint;
 312         int p_gain_pct;
 313         int d_gain_pct;
 314         int i_gain_pct;
 315 };
 316
 317 /**
 318  * struct pstate_funcs - Per CPU model specific callbacks
 319  * @get_max:            Callback to get maximum non turbo effective P state
 320  * @get_max_physical:   Callback to get maximum non turbo physical P state
 321  * @get_min:            Callback to get minimum P state
 322  * @get_turbo:          Callback to get turbo P state
 323  * @get_scaling:        Callback to get frequency scaling factor
 324  * @get_val:            Callback to convert P state to actual MSR write value
 325  * @get_vid:            Callback to get VID data for Atom platforms
 326  * @get_target_pstate:  Callback to a function to calculate next P state to use
 327  *
 328  * Core and Atom CPU models have different way to get P State limits. This
 329  * structure is used to store those callbacks.
 330  */
 331 struct pstate_funcs {
 332         int (*get_max)(void);
 333         int (*get_max_physical)(void);
 334         int (*get_min)(void);
 335         int (*get_turbo)(void);
 336         int (*get_scaling)(void);
 337         u64 (*get_val)(struct cpudata*, int pstate);
 338         void (*get_vid)(struct cpudata *);
 339         int32_t (*get_target_pstate)(struct cpudata *);
 340 };
 341
 342 /**
 343  * struct cpu_defaults- Per CPU model default config data
 344  * @pid_policy: PID config data
 345  * @funcs:              Callback function data
 346  */
 347 struct cpu_defaults {
 348         struct pstate_adjust_policy pid_policy;
 349         struct pstate_funcs funcs;
 350 };
 351
 352 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
 353 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
 354
 355 static struct pstate_adjust_policy pid_params __read_mostly;
 356 static struct pstate_funcs pstate_funcs __read_mostly;
 357 static int hwp_active __read_mostly;
 358 static bool per_cpu_limits __read_mostly;
 359
 360 #ifdef CONFIG_ACPI
 361 static bool acpi_ppc;
 362 #endif
 363
 364 static struct perf_limits performance_limits = {
 365         .no_turbo = 0,
 366         .turbo_disabled = 0,
 367         .max_perf_pct = 100,
 368         .max_perf = int_ext_tofp(1),
 369         .min_perf_pct = 100,
 370         .min_perf = int_ext_tofp(1),
 371         .max_policy_pct = 100,
 372         .max_sysfs_pct = 100,
 373         .min_policy_pct = 0,
 374         .min_sysfs_pct = 0,
 375 };
 376
 377 static struct perf_limits powersave_limits = {
 378         .no_turbo = 0,
 379         .turbo_disabled = 0,
 380         .max_perf_pct = 100,
 381         .max_perf = int_ext_tofp(1),
 382         .min_perf_pct = 0,
 383         .min_perf = 0,
 384         .max_policy_pct = 100,
 385         .max_sysfs_pct = 100,
 386         .min_policy_pct = 0,
 387         .min_sysfs_pct = 0,
 388 };
 389
 390 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
 391 static struct perf_limits *limits = &performance_limits;
 392 #else
 393 static struct perf_limits *limits = &powersave_limits;
 394 #endif
 395
 396 static DEFINE_MUTEX(intel_pstate_limits_lock);
 397
 398 #ifdef CONFIG_ACPI
 399
 400 static bool intel_pstate_get_ppc_enable_status(void)
 401 {
 402         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
 403             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
 404                 return true;
 405
 406         return acpi_ppc;
 407 }
 408
 409 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 410 {
 411         struct cpudata *cpu;
 412         int ret;
 413         int i;
 414
 415         if (hwp_active)
 416                 return;
 417
 418         if (!intel_pstate_get_ppc_enable_status())
 419                 return;
 420
 421         cpu = all_cpu_data[policy->cpu];
 422
 423         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 424                                                   policy->cpu);
 425         if (ret)
 426                 return;
 427
 428         /*
 429          * Check if the control value in _PSS is for PERF_CTL MSR, which should
 430          * guarantee that the states returned by it map to the states in our
 431          * list directly.
 432          */
 433         if (cpu->acpi_perf_data.control_register.space_id !=
 434                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
 435                 goto err;
 436
 437         /*
 438          * If there is only one entry _PSS, simply ignore _PSS and continue as
 439          * usual without taking _PSS into account
 440          */
 441         if (cpu->acpi_perf_data.state_count < 2)
 442                 goto err;
 443
 444         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
 445         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
 446                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
 447                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
 448                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
 449                          (u32) cpu->acpi_perf_data.states[i].power,
 450                          (u32) cpu->acpi_perf_data.states[i].control);
 451         }
 452
 453         /*
 454          * The _PSS table doesn't contain whole turbo frequency range.
 455          * This just contains +1 MHZ above the max non turbo frequency,
 456          * with control value corresponding to max turbo ratio. But
 457          * when cpufreq set policy is called, it will call with this
 458          * max frequency, which will cause a reduced performance as
 459          * this driver uses real max turbo frequency as the max
 460          * frequency. So correct this frequency in _PSS table to
 461          * correct max turbo frequency based on the turbo state.
 462          * Also need to convert to MHz as _PSS freq is in MHz.
 463          */
 464         if (!limits->turbo_disabled)
 465                 cpu->acpi_perf_data.states[0].core_frequency =
 466                                         policy->cpuinfo.max_freq / 1000;
 467         cpu->valid_pss_table = true;
 468         pr_debug("_PPC limits will be enforced\n");
 469
 470         return;
 471
 472  err:
 473         cpu->valid_pss_table = false;
 474         acpi_processor_unregister_performance(policy->cpu);
 475 }
 476
 477 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 478 {
 479         struct cpudata *cpu;
 480
 481         cpu = all_cpu_data[policy->cpu];
 482         if (!cpu->valid_pss_table)
 483                 return;
 484
 485         acpi_processor_unregister_performance(policy->cpu);
 486 }
 487
 488 #else
 489 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 490 {
 491 }
 492
 493 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 494 {
 495 }
 496 #endif
 497
 498 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
 499                              int deadband, int integral) {
 500         pid->setpoint = int_tofp(setpoint);
 501         pid->deadband  = int_tofp(deadband);
 502         pid->integral  = int_tofp(integral);
 503         pid->last_err  = int_tofp(setpoint) - int_tofp(busy);
 504 }
 505
 506 static inline void pid_p_gain_set(struct _pid *pid, int percent)
 507 {
 508         pid->p_gain = div_fp(percent, 100);
 509 }
 510
 511 static inline void pid_i_gain_set(struct _pid *pid, int percent)
 512 {
 513         pid->i_gain = div_fp(percent, 100);
 514 }
 515
 516 static inline void pid_d_gain_set(struct _pid *pid, int percent)
 517 {
 518         pid->d_gain = div_fp(percent, 100);
 519 }
 520
 521 static signed int pid_calc(struct _pid *pid, int32_t busy)
 522 {
 523         signed int result;
 524         int32_t pterm, dterm, fp_error;
 525         int32_t integral_limit;
 526
 527         fp_error = pid->setpoint - busy;
 528
 529         if (abs(fp_error) <= pid->deadband)
 530                 return 0;
 531
 532         pterm = mul_fp(pid->p_gain, fp_error);
 533
 534         pid->integral += fp_error;
 535
 536         /*
 537          * We limit the integral here so that it will never
 538          * get higher than 30.  This prevents it from becoming
 539          * too large an input over long periods of time and allows
 540          * it to get factored out sooner.
 541          *
 542          * The value of 30 was chosen through experimentation.
 543          */
 544         integral_limit = int_tofp(30);
 545         if (pid->integral > integral_limit)
 546                 pid->integral = integral_limit;
 547         if (pid->integral < -integral_limit)
 548                 pid->integral = -integral_limit;
 549
 550         dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
 551         pid->last_err = fp_error;
 552
 553         result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
 554         result = result + (1 << (FRAC_BITS-1));
 555         return (signed int)fp_toint(result);
 556 }
 557
 558 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
 559 {
 560         pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
 561         pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
 562         pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
 563
 564         pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
 565 }
 566
 567 static inline void intel_pstate_reset_all_pid(void)
 568 {
 569         unsigned int cpu;
 570
 571         for_each_online_cpu(cpu) {
 572                 if (all_cpu_data[cpu])
 573                         intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
 574         }
 575 }
 576
 577 static inline void update_turbo_state(void)
 578 {
 579         u64 misc_en;
 580         struct cpudata *cpu;
 581
 582         cpu = all_cpu_data[0];
 583         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 584         limits->turbo_disabled =
 585                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 586                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 587 }
 588
 589 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
 590 {
 591         u64 epb;
 592         int ret;
 593
 594         if (!static_cpu_has(X86_FEATURE_EPB))
 595                 return -ENXIO;
 596
 597         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 598         if (ret)
 599                 return (s16)ret;
 600
 601         return (s16)(epb & 0x0f);
 602 }
 603
 604 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
 605 {
 606         s16 epp;
 607
 608         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 609                 /*
 610                  * When hwp_req_data is 0, means that caller didn't read
 611                  * MSR_HWP_REQUEST, so need to read and get EPP.
 612                  */
 613                 if (!hwp_req_data) {
 614                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
 615                                             &hwp_req_data);
 616                         if (epp)
 617                                 return epp;
 618                 }
 619                 epp = (hwp_req_data >> 24) & 0xff;
 620         } else {
 621                 /* When there is no EPP present, HWP uses EPB settings */
 622                 epp = intel_pstate_get_epb(cpu_data);
 623         }
 624
 625         return epp;
 626 }
 627
 628 static int intel_pstate_set_epb(int cpu, s16 pref)
 629 {
 630         u64 epb;
 631         int ret;
 632
 633         if (!static_cpu_has(X86_FEATURE_EPB))
 634                 return -ENXIO;
 635
 636         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 637         if (ret)
 638                 return ret;
 639
 640         epb = (epb & ~0x0f) | pref;
 641         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
 642
 643         return 0;
 644 }
 645
 646 /*
 647  * EPP/EPB display strings corresponding to EPP index in the
 648  * energy_perf_strings[]
 649  *      index           String
 650  *-------------------------------------
 651  *      0               default
 652  *      1               performance
 653  *      2               balance_performance
 654  *      3               balance_power
 655  *      4               power
 656  */
 657 static const char * const energy_perf_strings[] = {
 658         "default",
 659         "performance",
 660         "balance_performance",
 661         "balance_power",
 662         "power",
 663         NULL
 664 };
 665
 666 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
 667 {
 668         s16 epp;
 669         int index = -EINVAL;
 670
 671         epp = intel_pstate_get_epp(cpu_data, 0);
 672         if (epp < 0)
 673                 return epp;
 674
 675         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 676                 /*
 677                  * Range:
 678                  *      0x00-0x3F       :       Performance
 679                  *      0x40-0x7F       :       Balance performance
 680                  *      0x80-0xBF       :       Balance power
 681                  *      0xC0-0xFF       :       Power
 682                  * The EPP is a 8 bit value, but our ranges restrict the
 683                  * value which can be set. Here only using top two bits
 684                  * effectively.
 685                  */
 686                 index = (epp >> 6) + 1;
 687         } else if (static_cpu_has(X86_FEATURE_EPB)) {
 688                 /*
 689                  * Range:
 690                  *      0x00-0x03       :       Performance
 691                  *      0x04-0x07       :       Balance performance
 692                  *      0x08-0x0B       :       Balance power
 693                  *      0x0C-0x0F       :       Power
 694                  * The EPB is a 4 bit value, but our ranges restrict the
 695                  * value which can be set. Here only using top two bits
 696                  * effectively.
 697                  */
 698                 index = (epp >> 2) + 1;
 699         }
 700
 701         return index;
 702 }
 703
 704 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
 705                                               int pref_index)
 706 {
 707         int epp = -EINVAL;
 708         int ret;
 709
 710         if (!pref_index)
 711                 epp = cpu_data->epp_default;
 712
 713         mutex_lock(&intel_pstate_limits_lock);
 714
 715         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 716                 u64 value;
 717
 718                 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
 719                 if (ret)
 720                         goto return_pref;
 721
 722                 value &= ~GENMASK_ULL(31, 24);
 723
 724                 /*
 725                  * If epp is not default, convert from index into
 726                  * energy_perf_strings to epp value, by shifting 6
 727                  * bits left to use only top two bits in epp.
 728                  * The resultant epp need to shifted by 24 bits to
 729                  * epp position in MSR_HWP_REQUEST.
 730                  */
 731                 if (epp == -EINVAL)
 732                         epp = (pref_index - 1) << 6;
 733
 734                 value |= (u64)epp << 24;
 735                 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
 736         } else {
 737                 if (epp == -EINVAL)
 738                         epp = (pref_index - 1) << 2;
 739                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
 740         }
 741 return_pref:
 742         mutex_unlock(&intel_pstate_limits_lock);
 743
 744         return ret;
 745 }
 746
 747 static ssize_t show_energy_performance_available_preferences(
 748                                 struct cpufreq_policy *policy, char *buf)
 749 {
 750         int i = 0;
 751         int ret = 0;
 752
 753         while (energy_perf_strings[i] != NULL)
 754                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
 755
 756         ret += sprintf(&buf[ret], "\n");
 757
 758         return ret;
 759 }
 760
 761 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 762
 763 static ssize_t store_energy_performance_preference(
 764                 struct cpufreq_policy *policy, const char *buf, size_t count)
 765 {
 766         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 767         char str_preference[21];
 768         int ret, i = 0;
 769
 770         ret = sscanf(buf, "%20s", str_preference);
 771         if (ret != 1)
 772                 return -EINVAL;
 773
 774         while (energy_perf_strings[i] != NULL) {
 775                 if (!strcmp(str_preference, energy_perf_strings[i])) {
 776                         intel_pstate_set_energy_pref_index(cpu_data, i);
 777                         return count;
 778                 }
 779                 ++i;
 780         }
 781
 782         return -EINVAL;
 783 }
 784
 785 static ssize_t show_energy_performance_preference(
 786                                 struct cpufreq_policy *policy, char *buf)
 787 {
 788         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 789         int preference;
 790
 791         preference = intel_pstate_get_energy_pref_index(cpu_data);
 792         if (preference < 0)
 793                 return preference;
 794
 795         return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
 796 }
 797
 798 cpufreq_freq_attr_rw(energy_performance_preference);
 799
 800 static struct freq_attr *hwp_cpufreq_attrs[] = {
 801         &energy_performance_preference,
 802         &energy_performance_available_preferences,
 803         NULL,
 804 };
 805
 806 static void intel_pstate_hwp_set(const struct cpumask *cpumask)
 807 {
 808         int min, hw_min, max, hw_max, cpu, range, adj_range;
 809         struct perf_limits *perf_limits = limits;
 810         u64 value, cap;
 811
 812         for_each_cpu(cpu, cpumask) {
 813                 int max_perf_pct, min_perf_pct;
 814                 struct cpudata *cpu_data = all_cpu_data[cpu];
 815                 s16 epp;
 816
 817                 if (per_cpu_limits)
 818                         perf_limits = all_cpu_data[cpu]->perf_limits;
 819
 820                 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
 821                 hw_min = HWP_LOWEST_PERF(cap);
 822                 hw_max = HWP_HIGHEST_PERF(cap);
 823                 range = hw_max - hw_min;
 824
 825                 max_perf_pct = perf_limits->max_perf_pct;
 826                 min_perf_pct = perf_limits->min_perf_pct;
 827
 828                 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 829                 adj_range = min_perf_pct * range / 100;
 830                 min = hw_min + adj_range;
 831                 value &= ~HWP_MIN_PERF(~0L);
 832                 value |= HWP_MIN_PERF(min);
 833
 834                 adj_range = max_perf_pct * range / 100;
 835                 max = hw_min + adj_range;
 836                 if (limits->no_turbo) {
 837                         hw_max = HWP_GUARANTEED_PERF(cap);
 838                         if (hw_max < max)
 839                                 max = hw_max;
 840                 }
 841
 842                 value &= ~HWP_MAX_PERF(~0L);
 843                 value |= HWP_MAX_PERF(max);
 844
 845                 if (cpu_data->epp_policy == cpu_data->policy)
 846                         goto skip_epp;
 847
 848                 cpu_data->epp_policy = cpu_data->policy;
 849
 850                 if (cpu_data->epp_saved >= 0) {
 851                         epp = cpu_data->epp_saved;
 852                         cpu_data->epp_saved = -EINVAL;
 853                         goto update_epp;
 854                 }
 855
 856                 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
 857                         epp = intel_pstate_get_epp(cpu_data, value);
 858                         cpu_data->epp_powersave = epp;
 859                         /* If EPP read was failed, then don't try to write */
 860                         if (epp < 0)
 861                                 goto skip_epp;
 862
 863
 864                         epp = 0;
 865                 } else {
 866                         /* skip setting EPP, when saved value is invalid */
 867                         if (cpu_data->epp_powersave < 0)
 868                                 goto skip_epp;
 869
 870                         /*
 871                          * No need to restore EPP when it is not zero. This
 872                          * means:
 873                          *  - Policy is not changed
 874                          *  - user has manually changed
 875                          *  - Error reading EPB
 876                          */
 877                         epp = intel_pstate_get_epp(cpu_data, value);
 878                         if (epp)
 879                                 goto skip_epp;
 880
 881                         epp = cpu_data->epp_powersave;
 882                 }
 883 update_epp:
 884                 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 885                         value &= ~GENMASK_ULL(31, 24);
 886                         value |= (u64)epp << 24;
 887                 } else {
 888                         intel_pstate_set_epb(cpu, epp);
 889                 }
 890 skip_epp:
 891                 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 892         }
 893 }
 894
 895 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy)
 896 {
 897         if (hwp_active)
 898                 intel_pstate_hwp_set(policy->cpus);
 899
 900         return 0;
 901 }
 902
 903 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
 904 {
 905         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 906
 907         if (!hwp_active)
 908                 return 0;
 909
 910         cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
 911
 912         return 0;
 913 }
 914
 915 static int intel_pstate_resume(struct cpufreq_policy *policy)
 916 {
 917         if (!hwp_active)
 918                 return 0;
 919
 920         all_cpu_data[policy->cpu]->epp_policy = 0;
 921
 922         return intel_pstate_hwp_set_policy(policy);
 923 }
 924
 925 static void intel_pstate_hwp_set_online_cpus(void)
 926 {
 927         get_online_cpus();
 928         intel_pstate_hwp_set(cpu_online_mask);
 929         put_online_cpus();
 930 }
 931
 932 /************************** debugfs begin ************************/
 933 static int pid_param_set(void *data, u64 val)
 934 {
 935         *(u32 *)data = val;
 936         intel_pstate_reset_all_pid();
 937         return 0;
 938 }
 939
 940 static int pid_param_get(void *data, u64 *val)
 941 {
 942         *val = *(u32 *)data;
 943         return 0;
 944 }
 945 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
 946
 947 struct pid_param {
 948         char *name;
 949         void *value;
 950 };
 951
 952 static struct pid_param pid_files[] = {
 953         {"sample_rate_ms", &pid_params.sample_rate_ms},
 954         {"d_gain_pct", &pid_params.d_gain_pct},
 955         {"i_gain_pct", &pid_params.i_gain_pct},
 956         {"deadband", &pid_params.deadband},
 957         {"setpoint", &pid_params.setpoint},
 958         {"p_gain_pct", &pid_params.p_gain_pct},
 959         {NULL, NULL}
 960 };
 961
 962 static void __init intel_pstate_debug_expose_params(void)
 963 {
 964         struct dentry *debugfs_parent;
 965         int i = 0;
 966
 967         if (hwp_active ||
 968             pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load)
 969                 return;
 970
 971         debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
 972         if (IS_ERR_OR_NULL(debugfs_parent))
 973                 return;
 974         while (pid_files[i].name) {
 975                 debugfs_create_file(pid_files[i].name, 0660,
 976                                     debugfs_parent, pid_files[i].value,
 977                                     &fops_pid_param);
 978                 i++;
 979         }
 980 }
 981
 982 /************************** debugfs end ************************/
 983
 984 /************************** sysfs begin ************************/
 985 #define show_one(file_name, object)                                     \
 986         static ssize_t show_##file_name                                 \
 987         (struct kobject *kobj, struct attribute *attr, char *buf)       \
 988         {                                                               \
 989                 return sprintf(buf, "%u\n", limits->object);            \
 990         }
 991
 992 static ssize_t show_turbo_pct(struct kobject *kobj,
 993                                 struct attribute *attr, char *buf)
 994 {
 995         struct cpudata *cpu;
 996         int total, no_turbo, turbo_pct;
 997         uint32_t turbo_fp;
 998
 999         cpu = all_cpu_data[0];
1000
1001         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1002         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1003         turbo_fp = div_fp(no_turbo, total);
1004         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1005         return sprintf(buf, "%u\n", turbo_pct);
1006 }
1007
1008 static ssize_t show_num_pstates(struct kobject *kobj,
1009                                 struct attribute *attr, char *buf)
1010 {
1011         struct cpudata *cpu;
1012         int total;
1013
1014         cpu = all_cpu_data[0];
1015         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1016         return sprintf(buf, "%u\n", total);
1017 }
1018
1019 static ssize_t show_no_turbo(struct kobject *kobj,
1020                              struct attribute *attr, char *buf)
1021 {
1022         ssize_t ret;
1023
1024         update_turbo_state();
1025         if (limits->turbo_disabled)
1026                 ret = sprintf(buf, "%u\n", limits->turbo_disabled);
1027         else
1028                 ret = sprintf(buf, "%u\n", limits->no_turbo);
1029
1030         return ret;
1031 }
1032
1033 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1034                               const char *buf, size_t count)
1035 {
1036         unsigned int input;
1037         int ret;
1038
1039         ret = sscanf(buf, "%u", &input);
1040         if (ret != 1)
1041                 return -EINVAL;
1042
1043         mutex_lock(&intel_pstate_limits_lock);
1044
1045         update_turbo_state();
1046         if (limits->turbo_disabled) {
1047                 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1048                 mutex_unlock(&intel_pstate_limits_lock);
1049                 return -EPERM;
1050         }
1051
1052         limits->no_turbo = clamp_t(int, input, 0, 1);
1053
1054         if (hwp_active)
1055                 intel_pstate_hwp_set_online_cpus();
1056
1057         mutex_unlock(&intel_pstate_limits_lock);
1058
1059         return count;
1060 }
1061
1062 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1063                                   const char *buf, size_t count)
1064 {
1065         unsigned int input;
1066         int ret;
1067
1068         ret = sscanf(buf, "%u", &input);
1069         if (ret != 1)
1070                 return -EINVAL;
1071
1072         mutex_lock(&intel_pstate_limits_lock);
1073
1074         limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);
1075         limits->max_perf_pct = min(limits->max_policy_pct,
1076                                    limits->max_sysfs_pct);
1077         limits->max_perf_pct = max(limits->min_policy_pct,
1078                                    limits->max_perf_pct);
1079         limits->max_perf_pct = max(limits->min_perf_pct,
1080                                    limits->max_perf_pct);
1081         limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
1082
1083         if (hwp_active)
1084                 intel_pstate_hwp_set_online_cpus();
1085
1086         mutex_unlock(&intel_pstate_limits_lock);
1087
1088         return count;
1089 }
1090
1091 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1092                                   const char *buf, size_t count)
1093 {
1094         unsigned int input;
1095         int ret;
1096
1097         ret = sscanf(buf, "%u", &input);
1098         if (ret != 1)
1099                 return -EINVAL;
1100
1101         mutex_lock(&intel_pstate_limits_lock);
1102
1103         limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);
1104         limits->min_perf_pct = max(limits->min_policy_pct,
1105                                    limits->min_sysfs_pct);
1106         limits->min_perf_pct = min(limits->max_policy_pct,
1107                                    limits->min_perf_pct);
1108         limits->min_perf_pct = min(limits->max_perf_pct,
1109                                    limits->min_perf_pct);
1110         limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
1111
1112         if (hwp_active)
1113                 intel_pstate_hwp_set_online_cpus();
1114
1115         mutex_unlock(&intel_pstate_limits_lock);
1116
1117         return count;
1118 }
1119
1120 show_one(max_perf_pct, max_perf_pct);
1121 show_one(min_perf_pct, min_perf_pct);
1122
1123 define_one_global_rw(no_turbo);
1124 define_one_global_rw(max_perf_pct);
1125 define_one_global_rw(min_perf_pct);
1126 define_one_global_ro(turbo_pct);
1127 define_one_global_ro(num_pstates);
1128
1129 static struct attribute *intel_pstate_attributes[] = {
1130         &no_turbo.attr,
1131         &turbo_pct.attr,
1132         &num_pstates.attr,
1133         NULL
1134 };
1135
1136 static struct attribute_group intel_pstate_attr_group = {
1137         .attrs = intel_pstate_attributes,
1138 };
1139
1140 static void __init intel_pstate_sysfs_expose_params(void)
1141 {
1142         struct kobject *intel_pstate_kobject;
1143         int rc;
1144
1145         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1146                                                 &cpu_subsys.dev_root->kobj);
1147         if (WARN_ON(!intel_pstate_kobject))
1148                 return;
1149
1150         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1151         if (WARN_ON(rc))
1152                 return;
1153
1154         /*
1155          * If per cpu limits are enforced there are no global limits, so
1156          * return without creating max/min_perf_pct attributes
1157          */
1158         if (per_cpu_limits)
1159                 return;
1160
1161         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1162         WARN_ON(rc);
1163
1164         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1165         WARN_ON(rc);
1166
1167 }
1168 /************************** sysfs end ************************/
1169
1170 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1171 {
1172         /* First disable HWP notification interrupt as we don't process them */
1173         if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1174                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1175
1176         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1177         cpudata->epp_policy = 0;
1178         if (cpudata->epp_default == -EINVAL)
1179                 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1180 }
1181
1182 static int atom_get_min_pstate(void)
1183 {
1184         u64 value;
1185
1186         rdmsrl(ATOM_RATIOS, value);
1187         return (value >> 8) & 0x7F;
1188 }
1189
1190 static int atom_get_max_pstate(void)
1191 {
1192         u64 value;
1193
1194         rdmsrl(ATOM_RATIOS, value);
1195         return (value >> 16) & 0x7F;
1196 }
1197
1198 static int atom_get_turbo_pstate(void)
1199 {
1200         u64 value;
1201
1202         rdmsrl(ATOM_TURBO_RATIOS, value);
1203         return value & 0x7F;
1204 }
1205
1206 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1207 {
1208         u64 val;
1209         int32_t vid_fp;
1210         u32 vid;
1211
1212         val = (u64)pstate << 8;
1213         if (limits->no_turbo && !limits->turbo_disabled)
1214                 val |= (u64)1 << 32;
1215
1216         vid_fp = cpudata->vid.min + mul_fp(
1217                 int_tofp(pstate - cpudata->pstate.min_pstate),
1218                 cpudata->vid.ratio);
1219
1220         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1221         vid = ceiling_fp(vid_fp);
1222
1223         if (pstate > cpudata->pstate.max_pstate)
1224                 vid = cpudata->vid.turbo;
1225
1226         return val | vid;
1227 }
1228
1229 static int silvermont_get_scaling(void)
1230 {
1231         u64 value;
1232         int i;
1233         /* Defined in Table 35-6 from SDM (Sept 2015) */
1234         static int silvermont_freq_table[] = {
1235                 83300, 100000, 133300, 116700, 80000};
1236
1237         rdmsrl(MSR_FSB_FREQ, value);
1238         i = value & 0x7;
1239         WARN_ON(i > 4);
1240
1241         return silvermont_freq_table[i];
1242 }
1243
1244 static int airmont_get_scaling(void)
1245 {
1246         u64 value;
1247         int i;
1248         /* Defined in Table 35-10 from SDM (Sept 2015) */
1249         static int airmont_freq_table[] = {
1250                 83300, 100000, 133300, 116700, 80000,
1251                 93300, 90000, 88900, 87500};
1252
1253         rdmsrl(MSR_FSB_FREQ, value);
1254         i = value & 0xF;
1255         WARN_ON(i > 8);
1256
1257         return airmont_freq_table[i];
1258 }
1259
1260 static void atom_get_vid(struct cpudata *cpudata)
1261 {
1262         u64 value;
1263
1264         rdmsrl(ATOM_VIDS, value);
1265         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1266         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1267         cpudata->vid.ratio = div_fp(
1268                 cpudata->vid.max - cpudata->vid.min,
1269                 int_tofp(cpudata->pstate.max_pstate -
1270                         cpudata->pstate.min_pstate));
1271
1272         rdmsrl(ATOM_TURBO_VIDS, value);
1273         cpudata->vid.turbo = value & 0x7f;
1274 }
1275
1276 static int core_get_min_pstate(void)
1277 {
1278         u64 value;
1279
1280         rdmsrl(MSR_PLATFORM_INFO, value);
1281         return (value >> 40) & 0xFF;
1282 }
1283
1284 static int core_get_max_pstate_physical(void)
1285 {
1286         u64 value;
1287
1288         rdmsrl(MSR_PLATFORM_INFO, value);
1289         return (value >> 8) & 0xFF;
1290 }
1291
1292 static int core_get_max_pstate(void)
1293 {
1294         u64 tar;
1295         u64 plat_info;
1296         int max_pstate;
1297         int err;
1298
1299         rdmsrl(MSR_PLATFORM_INFO, plat_info);
1300         max_pstate = (plat_info >> 8) & 0xFF;
1301
1302         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1303         if (!err) {
1304                 /* Do some sanity checking for safety */
1305                 if (plat_info & 0x600000000) {
1306                         u64 tdp_ctrl;
1307                         u64 tdp_ratio;
1308                         int tdp_msr;
1309
1310                         err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1311                         if (err)
1312                                 goto skip_tar;
1313
1314                         tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x3);
1315                         err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1316                         if (err)
1317                                 goto skip_tar;
1318
1319                         /* For level 1 and 2, bits[23:16] contain the ratio */
1320                         if (tdp_ctrl)
1321                                 tdp_ratio >>= 16;
1322
1323                         tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1324                         if (tdp_ratio - 1 == tar) {
1325                                 max_pstate = tar;
1326                                 pr_debug("max_pstate=TAC %x\n", max_pstate);
1327                         } else {
1328                                 goto skip_tar;
1329                         }
1330                 }
1331         }
1332
1333 skip_tar:
1334         return max_pstate;
1335 }
1336
1337 static int core_get_turbo_pstate(void)
1338 {
1339         u64 value;
1340         int nont, ret;
1341
1342         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1343         nont = core_get_max_pstate();
1344         ret = (value) & 255;
1345         if (ret <= nont)
1346                 ret = nont;
1347         return ret;
1348 }
1349
1350 static inline int core_get_scaling(void)
1351 {
1352         return 100000;
1353 }
1354
1355 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1356 {
1357         u64 val;
1358
1359         val = (u64)pstate << 8;
1360         if (limits->no_turbo && !limits->turbo_disabled)
1361                 val |= (u64)1 << 32;
1362
1363         return val;
1364 }
1365
1366 static int knl_get_turbo_pstate(void)
1367 {
1368         u64 value;
1369         int nont, ret;
1370
1371         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1372         nont = core_get_max_pstate();
1373         ret = (((value) >> 8) & 0xFF);
1374         if (ret <= nont)
1375                 ret = nont;
1376         return ret;
1377 }
1378
1379 static struct cpu_defaults core_params = {
1380         .pid_policy = {
1381                 .sample_rate_ms = 10,
1382                 .deadband = 0,
1383                 .setpoint = 97,
1384                 .p_gain_pct = 20,
1385                 .d_gain_pct = 0,
1386                 .i_gain_pct = 0,
1387         },
1388         .funcs = {
1389                 .get_max = core_get_max_pstate,
1390                 .get_max_physical = core_get_max_pstate_physical,
1391                 .get_min = core_get_min_pstate,
1392                 .get_turbo = core_get_turbo_pstate,
1393                 .get_scaling = core_get_scaling,
1394                 .get_val = core_get_val,
1395                 .get_target_pstate = get_target_pstate_use_performance,
1396         },
1397 };
1398
1399 static const struct cpu_defaults silvermont_params = {
1400         .pid_policy = {
1401                 .sample_rate_ms = 10,
1402                 .deadband = 0,
1403                 .setpoint = 60,
1404                 .p_gain_pct = 14,
1405                 .d_gain_pct = 0,
1406                 .i_gain_pct = 4,
1407         },
1408         .funcs = {
1409                 .get_max = atom_get_max_pstate,
1410                 .get_max_physical = atom_get_max_pstate,
1411                 .get_min = atom_get_min_pstate,
1412                 .get_turbo = atom_get_turbo_pstate,
1413                 .get_val = atom_get_val,
1414                 .get_scaling = silvermont_get_scaling,
1415                 .get_vid = atom_get_vid,
1416                 .get_target_pstate = get_target_pstate_use_cpu_load,
1417         },
1418 };
1419
1420 static const struct cpu_defaults airmont_params = {
1421         .pid_policy = {
1422                 .sample_rate_ms = 10,
1423                 .deadband = 0,
1424                 .setpoint = 60,
1425                 .p_gain_pct = 14,
1426                 .d_gain_pct = 0,
1427                 .i_gain_pct = 4,
1428         },
1429         .funcs = {
1430                 .get_max = atom_get_max_pstate,
1431                 .get_max_physical = atom_get_max_pstate,
1432                 .get_min = atom_get_min_pstate,
1433                 .get_turbo = atom_get_turbo_pstate,
1434                 .get_val = atom_get_val,
1435                 .get_scaling = airmont_get_scaling,
1436                 .get_vid = atom_get_vid,
1437                 .get_target_pstate = get_target_pstate_use_cpu_load,
1438         },
1439 };
1440
1441 static const struct cpu_defaults knl_params = {
1442         .pid_policy = {
1443                 .sample_rate_ms = 10,
1444                 .deadband = 0,
1445                 .setpoint = 97,
1446                 .p_gain_pct = 20,
1447                 .d_gain_pct = 0,
1448                 .i_gain_pct = 0,
1449         },
1450         .funcs = {
1451                 .get_max = core_get_max_pstate,
1452                 .get_max_physical = core_get_max_pstate_physical,
1453                 .get_min = core_get_min_pstate,
1454                 .get_turbo = knl_get_turbo_pstate,
1455                 .get_scaling = core_get_scaling,
1456                 .get_val = core_get_val,
1457                 .get_target_pstate = get_target_pstate_use_performance,
1458         },
1459 };
1460
1461 static const struct cpu_defaults bxt_params = {
1462         .pid_policy = {
1463                 .sample_rate_ms = 10,
1464                 .deadband = 0,
1465                 .setpoint = 60,
1466                 .p_gain_pct = 14,
1467                 .d_gain_pct = 0,
1468                 .i_gain_pct = 4,
1469         },
1470         .funcs = {
1471                 .get_max = core_get_max_pstate,
1472                 .get_max_physical = core_get_max_pstate_physical,
1473                 .get_min = core_get_min_pstate,
1474                 .get_turbo = core_get_turbo_pstate,
1475                 .get_scaling = core_get_scaling,
1476                 .get_val = core_get_val,
1477                 .get_target_pstate = get_target_pstate_use_cpu_load,
1478         },
1479 };
1480
1481 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1482 {
1483         int max_perf = cpu->pstate.turbo_pstate;
1484         int max_perf_adj;
1485         int min_perf;
1486         struct perf_limits *perf_limits = limits;
1487
1488         if (limits->no_turbo || limits->turbo_disabled)
1489                 max_perf = cpu->pstate.max_pstate;
1490
1491         if (per_cpu_limits)
1492                 perf_limits = cpu->perf_limits;
1493
1494         /*
1495          * performance can be limited by user through sysfs, by cpufreq
1496          * policy, or by cpu specific default values determined through
1497          * experimentation.
1498          */
1499         max_perf_adj = fp_ext_toint(max_perf * perf_limits->max_perf);
1500         *max = clamp_t(int, max_perf_adj,
1501                         cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
1502
1503         min_perf = fp_ext_toint(max_perf * perf_limits->min_perf);
1504         *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
1505 }
1506
1507 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1508 {
1509         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1510         cpu->pstate.current_pstate = pstate;
1511         /*
1512          * Generally, there is no guarantee that this code will always run on
1513          * the CPU being updated, so force the register update to run on the
1514          * right CPU.
1515          */
1516         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1517                       pstate_funcs.get_val(cpu, pstate));
1518 }
1519
1520 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1521 {
1522         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1523 }
1524
1525 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1526 {
1527         int min_pstate, max_pstate;
1528
1529         update_turbo_state();
1530         intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate);
1531         intel_pstate_set_pstate(cpu, max_pstate);
1532 }
1533
1534 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1535 {
1536         cpu->pstate.min_pstate = pstate_funcs.get_min();
1537         cpu->pstate.max_pstate = pstate_funcs.get_max();
1538         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1539         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1540         cpu->pstate.scaling = pstate_funcs.get_scaling();
1541         cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1542         cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1543
1544         if (pstate_funcs.get_vid)
1545                 pstate_funcs.get_vid(cpu);
1546
1547         intel_pstate_set_min_pstate(cpu);
1548 }
1549
1550 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1551 {
1552         struct sample *sample = &cpu->sample;
1553
1554         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1555 }
1556
1557 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1558 {
1559         u64 aperf, mperf;
1560         unsigned long flags;
1561         u64 tsc;
1562
1563         local_irq_save(flags);
1564         rdmsrl(MSR_IA32_APERF, aperf);
1565         rdmsrl(MSR_IA32_MPERF, mperf);
1566         tsc = rdtsc();
1567         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1568                 local_irq_restore(flags);
1569                 return false;
1570         }
1571         local_irq_restore(flags);
1572
1573         cpu->last_sample_time = cpu->sample.time;
1574         cpu->sample.time = time;
1575         cpu->sample.aperf = aperf;
1576         cpu->sample.mperf = mperf;
1577         cpu->sample.tsc =  tsc;
1578         cpu->sample.aperf -= cpu->prev_aperf;
1579         cpu->sample.mperf -= cpu->prev_mperf;
1580         cpu->sample.tsc -= cpu->prev_tsc;
1581
1582         cpu->prev_aperf = aperf;
1583         cpu->prev_mperf = mperf;
1584         cpu->prev_tsc = tsc;
1585         /*
1586          * First time this function is invoked in a given cycle, all of the
1587          * previous sample data fields are equal to zero or stale and they must
1588          * be populated with meaningful numbers for things to work, so assume
1589          * that sample.time will always be reset before setting the utilization
1590          * update hook and make the caller skip the sample then.
1591          */
1592         return !!cpu->last_sample_time;
1593 }
1594
1595 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1596 {
1597         return mul_ext_fp(cpu->sample.core_avg_perf,
1598                           cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1599 }
1600
1601 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1602 {
1603         return mul_ext_fp(cpu->pstate.max_pstate_physical,
1604                           cpu->sample.core_avg_perf);
1605 }
1606
1607 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1608 {
1609         struct sample *sample = &cpu->sample;
1610         int32_t busy_frac, boost;
1611         int target, avg_pstate;
1612
1613         busy_frac = div_fp(sample->mperf, sample->tsc);
1614
1615         boost = cpu->iowait_boost;
1616         cpu->iowait_boost >>= 1;
1617
1618         if (busy_frac < boost)
1619                 busy_frac = boost;
1620
1621         sample->busy_scaled = busy_frac * 100;
1622
1623         target = limits->no_turbo || limits->turbo_disabled ?
1624                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1625         target += target >> 2;
1626         target = mul_fp(target, busy_frac);
1627         if (target < cpu->pstate.min_pstate)
1628                 target = cpu->pstate.min_pstate;
1629
1630         /*
1631          * If the average P-state during the previous cycle was higher than the
1632          * current target, add 50% of the difference to the target to reduce
1633          * possible performance oscillations and offset possible performance
1634          * loss related to moving the workload from one CPU to another within
1635          * a package/module.
1636          */
1637         avg_pstate = get_avg_pstate(cpu);
1638         if (avg_pstate > target)
1639                 target += (avg_pstate - target) >> 1;
1640
1641         return target;
1642 }
1643
1644 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1645 {
1646         int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1647         u64 duration_ns;
1648
1649         /*
1650          * perf_scaled is the ratio of the average P-state during the last
1651          * sampling period to the P-state requested last time (in percent).
1652          *
1653          * That measures the system's response to the previous P-state
1654          * selection.
1655          */
1656         max_pstate = cpu->pstate.max_pstate_physical;
1657         current_pstate = cpu->pstate.current_pstate;
1658         perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1659                                div_fp(100 * max_pstate, current_pstate));
1660
1661         /*
1662          * Since our utilization update callback will not run unless we are
1663          * in C0, check if the actual elapsed time is significantly greater (3x)
1664          * than our sample interval.  If it is, then we were idle for a long
1665          * enough period of time to adjust our performance metric.
1666          */
1667         duration_ns = cpu->sample.time - cpu->last_sample_time;
1668         if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1669                 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1670                 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1671         } else {
1672                 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1673                 if (sample_ratio < int_tofp(1))
1674                         perf_scaled = 0;
1675         }
1676
1677         cpu->sample.busy_scaled = perf_scaled;
1678         return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1679 }
1680
1681 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1682 {
1683         int max_perf, min_perf;
1684
1685         intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1686         pstate = clamp_t(int, pstate, min_perf, max_perf);
1687         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1688         return pstate;
1689 }
1690
1691 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1692 {
1693         pstate = intel_pstate_prepare_request(cpu, pstate);
1694         if (pstate == cpu->pstate.current_pstate)
1695                 return;
1696
1697         cpu->pstate.current_pstate = pstate;
1698         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1699 }
1700
1701 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1702 {
1703         int from, target_pstate;
1704         struct sample *sample;
1705
1706         from = cpu->pstate.current_pstate;
1707
1708         target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ?
1709                 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu);
1710
1711         update_turbo_state();
1712
1713         intel_pstate_update_pstate(cpu, target_pstate);
1714
1715         sample = &cpu->sample;
1716         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1717                 fp_toint(sample->busy_scaled),
1718                 from,
1719                 cpu->pstate.current_pstate,
1720                 sample->mperf,
1721                 sample->aperf,
1722                 sample->tsc,
1723                 get_avg_frequency(cpu),
1724                 fp_toint(cpu->iowait_boost * 100));
1725 }
1726
1727 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1728                                      unsigned int flags)
1729 {
1730         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1731         u64 delta_ns;
1732
1733         if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) {
1734                 if (flags & SCHED_CPUFREQ_IOWAIT) {
1735                         cpu->iowait_boost = int_tofp(1);
1736                 } else if (cpu->iowait_boost) {
1737                         /* Clear iowait_boost if the CPU may have been idle. */
1738                         delta_ns = time - cpu->last_update;
1739                         if (delta_ns > TICK_NSEC)
1740                                 cpu->iowait_boost = 0;
1741                 }
1742                 cpu->last_update = time;
1743         }
1744
1745         delta_ns = time - cpu->sample.time;
1746         if ((s64)delta_ns >= pid_params.sample_rate_ns) {
1747                 bool sample_taken = intel_pstate_sample(cpu, time);
1748
1749                 if (sample_taken) {
1750                         intel_pstate_calc_avg_perf(cpu);
1751                         if (!hwp_active)
1752                                 intel_pstate_adjust_busy_pstate(cpu);
1753                 }
1754         }
1755 }
1756
1757 #define ICPU(model, policy) \
1758         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1759                         (unsigned long)&policy }
1760
1761 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1762         ICPU(INTEL_FAM6_SANDYBRIDGE,            core_params),
1763         ICPU(INTEL_FAM6_SANDYBRIDGE_X,          core_params),
1764         ICPU(INTEL_FAM6_ATOM_SILVERMONT1,       silvermont_params),
1765         ICPU(INTEL_FAM6_IVYBRIDGE,              core_params),
1766         ICPU(INTEL_FAM6_HASWELL_CORE,           core_params),
1767         ICPU(INTEL_FAM6_BROADWELL_CORE,         core_params),
1768         ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_params),
1769         ICPU(INTEL_FAM6_HASWELL_X,              core_params),
1770         ICPU(INTEL_FAM6_HASWELL_ULT,            core_params),
1771         ICPU(INTEL_FAM6_HASWELL_GT3E,           core_params),
1772         ICPU(INTEL_FAM6_BROADWELL_GT3E,         core_params),
1773         ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_params),
1774         ICPU(INTEL_FAM6_SKYLAKE_MOBILE,         core_params),
1775         ICPU(INTEL_FAM6_BROADWELL_X,            core_params),
1776         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP,        core_params),
1777         ICPU(INTEL_FAM6_BROADWELL_XEON_D,       core_params),
1778         ICPU(INTEL_FAM6_XEON_PHI_KNL,           knl_params),
1779         ICPU(INTEL_FAM6_XEON_PHI_KNM,           knl_params),
1780         ICPU(INTEL_FAM6_ATOM_GOLDMONT,          bxt_params),
1781         {}
1782 };
1783 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1784
1785 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1786         ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1787         ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1788         ICPU(INTEL_FAM6_SKYLAKE_X, core_params),
1789         {}
1790 };
1791
1792 static int intel_pstate_init_cpu(unsigned int cpunum)
1793 {
1794         struct cpudata *cpu;
1795
1796         cpu = all_cpu_data[cpunum];
1797
1798         if (!cpu) {
1799                 unsigned int size = sizeof(struct cpudata);
1800
1801                 if (per_cpu_limits)
1802                         size += sizeof(struct perf_limits);
1803
1804                 cpu = kzalloc(size, GFP_KERNEL);
1805                 if (!cpu)
1806                         return -ENOMEM;
1807
1808                 all_cpu_data[cpunum] = cpu;
1809                 if (per_cpu_limits)
1810                         cpu->perf_limits = (struct perf_limits *)(cpu + 1);
1811
1812                 cpu->epp_default = -EINVAL;
1813                 cpu->epp_powersave = -EINVAL;
1814                 cpu->epp_saved = -EINVAL;
1815         }
1816
1817         cpu = all_cpu_data[cpunum];
1818
1819         cpu->cpu = cpunum;
1820
1821         if (hwp_active) {
1822                 intel_pstate_hwp_enable(cpu);
1823                 pid_params.sample_rate_ms = 50;
1824                 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
1825         }
1826
1827         intel_pstate_get_cpu_pstates(cpu);
1828
1829         intel_pstate_busy_pid_reset(cpu);
1830
1831         pr_debug("controlling: cpu %d\n", cpunum);
1832
1833         return 0;
1834 }
1835
1836 static unsigned int intel_pstate_get(unsigned int cpu_num)
1837 {
1838         struct cpudata *cpu = all_cpu_data[cpu_num];
1839
1840         return cpu ? get_avg_frequency(cpu) : 0;
1841 }
1842
1843 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1844 {
1845         struct cpudata *cpu = all_cpu_data[cpu_num];
1846
1847         if (cpu->update_util_set)
1848                 return;
1849
1850         /* Prevent intel_pstate_update_util() from using stale data. */
1851         cpu->sample.time = 0;
1852         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1853                                      intel_pstate_update_util);
1854         cpu->update_util_set = true;
1855 }
1856
1857 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1858 {
1859         struct cpudata *cpu_data = all_cpu_data[cpu];
1860
1861         if (!cpu_data->update_util_set)
1862                 return;
1863
1864         cpufreq_remove_update_util_hook(cpu);
1865         cpu_data->update_util_set = false;
1866         synchronize_sched();
1867 }
1868
1869 static void intel_pstate_set_performance_limits(struct perf_limits *limits)
1870 {
1871         limits->no_turbo = 0;
1872         limits->turbo_disabled = 0;
1873         limits->max_perf_pct = 100;
1874         limits->max_perf = int_ext_tofp(1);
1875         limits->min_perf_pct = 100;
1876         limits->min_perf = int_ext_tofp(1);
1877         limits->max_policy_pct = 100;
1878         limits->max_sysfs_pct = 100;
1879         limits->min_policy_pct = 0;
1880         limits->min_sysfs_pct = 0;
1881 }
1882
1883 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1884                                             struct perf_limits *limits)
1885 {
1886
1887         limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
1888                                               policy->cpuinfo.max_freq);
1889         limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0, 100);
1890         if (policy->max == policy->min) {
1891                 limits->min_policy_pct = limits->max_policy_pct;
1892         } else {
1893                 limits->min_policy_pct = DIV_ROUND_UP(policy->min * 100,
1894                                                       policy->cpuinfo.max_freq);
1895                 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct,
1896                                                  0, 100);
1897         }
1898
1899         /* Normalize user input to [min_policy_pct, max_policy_pct] */
1900         limits->min_perf_pct = max(limits->min_policy_pct,
1901                                    limits->min_sysfs_pct);
1902         limits->min_perf_pct = min(limits->max_policy_pct,
1903                                    limits->min_perf_pct);
1904         limits->max_perf_pct = min(limits->max_policy_pct,
1905                                    limits->max_sysfs_pct);
1906         limits->max_perf_pct = max(limits->min_policy_pct,
1907                                    limits->max_perf_pct);
1908
1909         /* Make sure min_perf_pct <= max_perf_pct */
1910         limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
1911
1912         limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
1913         limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
1914         limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS);
1915         limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS);
1916
1917         pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
1918                  limits->max_perf_pct, limits->min_perf_pct);
1919 }
1920
1921 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1922 {
1923         struct cpudata *cpu;
1924         struct perf_limits *perf_limits = NULL;
1925
1926         if (!policy->cpuinfo.max_freq)
1927                 return -ENODEV;
1928
1929         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1930                  policy->cpuinfo.max_freq, policy->max);
1931
1932         cpu = all_cpu_data[policy->cpu];
1933         cpu->policy = policy->policy;
1934
1935         if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
1936             policy->max < policy->cpuinfo.max_freq &&
1937             policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) {
1938                 pr_debug("policy->max > max non turbo frequency\n");
1939                 policy->max = policy->cpuinfo.max_freq;
1940         }
1941
1942         if (per_cpu_limits)
1943                 perf_limits = cpu->perf_limits;
1944
1945         mutex_lock(&intel_pstate_limits_lock);
1946
1947         if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
1948                 if (!perf_limits) {
1949                         limits = &performance_limits;
1950                         perf_limits = limits;
1951                 }
1952                 if (policy->max >= policy->cpuinfo.max_freq) {
1953                         pr_debug("set performance\n");
1954                         intel_pstate_set_performance_limits(perf_limits);
1955                         goto out;
1956                 }
1957         } else {
1958                 pr_debug("set powersave\n");
1959                 if (!perf_limits) {
1960                         limits = &powersave_limits;
1961                         perf_limits = limits;
1962                 }
1963
1964         }
1965
1966         intel_pstate_update_perf_limits(policy, perf_limits);
1967  out:
1968         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
1969                 /*
1970                  * NOHZ_FULL CPUs need this as the governor callback may not
1971                  * be invoked on them.
1972                  */
1973                 intel_pstate_clear_update_util_hook(policy->cpu);
1974                 intel_pstate_max_within_limits(cpu);
1975         }
1976
1977         intel_pstate_set_update_util_hook(policy->cpu);
1978
1979         intel_pstate_hwp_set_policy(policy);
1980
1981         mutex_unlock(&intel_pstate_limits_lock);
1982
1983         return 0;
1984 }
1985
1986 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
1987 {
1988         cpufreq_verify_within_cpu_limits(policy);
1989
1990         if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
1991             policy->policy != CPUFREQ_POLICY_PERFORMANCE)
1992                 return -EINVAL;
1993
1994         return 0;
1995 }
1996
1997 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
1998 {
1999         intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2000 }
2001
2002 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2003 {
2004         pr_debug("CPU %d exiting\n", policy->cpu);
2005
2006         intel_pstate_clear_update_util_hook(policy->cpu);
2007         if (hwp_active)
2008                 intel_pstate_hwp_save_state(policy);
2009         else
2010                 intel_cpufreq_stop_cpu(policy);
2011 }
2012
2013 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2014 {
2015         intel_pstate_exit_perf_limits(policy);
2016
2017         policy->fast_switch_possible = false;
2018
2019         return 0;
2020 }
2021
2022 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2023 {
2024         struct cpudata *cpu;
2025         int rc;
2026
2027         rc = intel_pstate_init_cpu(policy->cpu);
2028         if (rc)
2029                 return rc;
2030
2031         cpu = all_cpu_data[policy->cpu];
2032
2033         /*
2034          * We need sane value in the cpu->perf_limits, so inherit from global
2035          * perf_limits limits, which are seeded with values based on the
2036          * CONFIG_CPU_FREQ_DEFAULT_GOV_*, during boot up.
2037          */
2038         if (per_cpu_limits)
2039                 memcpy(cpu->perf_limits, limits, sizeof(struct perf_limits));
2040
2041         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2042         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2043
2044         /* cpuinfo and default policy values */
2045         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2046         update_turbo_state();
2047         policy->cpuinfo.max_freq = limits->turbo_disabled ?
2048                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2049         policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2050
2051         intel_pstate_init_acpi_perf_limits(policy);
2052         cpumask_set_cpu(policy->cpu, policy->cpus);
2053
2054         policy->fast_switch_possible = true;
2055
2056         return 0;
2057 }
2058
2059 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2060 {
2061         int ret = __intel_pstate_cpu_init(policy);
2062
2063         if (ret)
2064                 return ret;
2065
2066         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2067         if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)
2068                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2069         else
2070                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2071
2072         return 0;
2073 }
2074
2075 static struct cpufreq_driver intel_pstate = {
2076         .flags          = CPUFREQ_CONST_LOOPS,
2077         .verify         = intel_pstate_verify_policy,
2078         .setpolicy      = intel_pstate_set_policy,
2079         .suspend        = intel_pstate_hwp_save_state,
2080         .resume         = intel_pstate_resume,
2081         .get            = intel_pstate_get,
2082         .init           = intel_pstate_cpu_init,
2083         .exit           = intel_pstate_cpu_exit,
2084         .stop_cpu       = intel_pstate_stop_cpu,
2085         .name           = "intel_pstate",
2086 };
2087
2088 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2089 {
2090         struct cpudata *cpu = all_cpu_data[policy->cpu];
2091         struct perf_limits *perf_limits = limits;
2092
2093         update_turbo_state();
2094         policy->cpuinfo.max_freq = limits->turbo_disabled ?
2095                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2096
2097         cpufreq_verify_within_cpu_limits(policy);
2098
2099         if (per_cpu_limits)
2100                 perf_limits = cpu->perf_limits;
2101
2102         intel_pstate_update_perf_limits(policy, perf_limits);
2103
2104         return 0;
2105 }
2106
2107 static unsigned int intel_cpufreq_turbo_update(struct cpudata *cpu,
2108                                                struct cpufreq_policy *policy,
2109                                                unsigned int target_freq)
2110 {
2111         unsigned int max_freq;
2112
2113         update_turbo_state();
2114
2115         max_freq = limits->no_turbo || limits->turbo_disabled ?
2116                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2117         policy->cpuinfo.max_freq = max_freq;
2118         if (policy->max > max_freq)
2119                 policy->max = max_freq;
2120
2121         if (target_freq > max_freq)
2122                 target_freq = max_freq;
2123
2124         return target_freq;
2125 }
2126
2127 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2128                                 unsigned int target_freq,
2129                                 unsigned int relation)
2130 {
2131         struct cpudata *cpu = all_cpu_data[policy->cpu];
2132         struct cpufreq_freqs freqs;
2133         int target_pstate;
2134
2135         freqs.old = policy->cur;
2136         freqs.new = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2137
2138         cpufreq_freq_transition_begin(policy, &freqs);
2139         switch (relation) {
2140         case CPUFREQ_RELATION_L:
2141                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2142                 break;
2143         case CPUFREQ_RELATION_H:
2144                 target_pstate = freqs.new / cpu->pstate.scaling;
2145                 break;
2146         default:
2147                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2148                 break;
2149         }
2150         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2151         if (target_pstate != cpu->pstate.current_pstate) {
2152                 cpu->pstate.current_pstate = target_pstate;
2153                 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2154                               pstate_funcs.get_val(cpu, target_pstate));
2155         }
2156         cpufreq_freq_transition_end(policy, &freqs, false);
2157
2158         return 0;
2159 }
2160
2161 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2162                                               unsigned int target_freq)
2163 {
2164         struct cpudata *cpu = all_cpu_data[policy->cpu];
2165         int target_pstate;
2166
2167         target_freq = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2168         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2169         intel_pstate_update_pstate(cpu, target_pstate);
2170         return target_freq;
2171 }
2172
2173 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2174 {
2175         int ret = __intel_pstate_cpu_init(policy);
2176
2177         if (ret)
2178                 return ret;
2179
2180         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2181         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2182         policy->cur = policy->cpuinfo.min_freq;
2183
2184         return 0;
2185 }
2186
2187 static struct cpufreq_driver intel_cpufreq = {
2188         .flags          = CPUFREQ_CONST_LOOPS,
2189         .verify         = intel_cpufreq_verify_policy,
2190         .target         = intel_cpufreq_target,
2191         .fast_switch    = intel_cpufreq_fast_switch,
2192         .init           = intel_cpufreq_cpu_init,
2193         .exit           = intel_pstate_cpu_exit,
2194         .stop_cpu       = intel_cpufreq_stop_cpu,
2195         .name           = "intel_cpufreq",
2196 };
2197
2198 static struct cpufreq_driver *intel_pstate_driver = &intel_pstate;
2199
2200 static int no_load __initdata;
2201 static int no_hwp __initdata;
2202 static int hwp_only __initdata;
2203 static unsigned int force_load __initdata;
2204
2205 static int __init intel_pstate_msrs_not_valid(void)
2206 {
2207         if (!pstate_funcs.get_max() ||
2208             !pstate_funcs.get_min() ||
2209             !pstate_funcs.get_turbo())
2210                 return -ENODEV;
2211
2212         return 0;
2213 }
2214
2215 static void __init copy_pid_params(struct pstate_adjust_policy *policy)
2216 {
2217         pid_params.sample_rate_ms = policy->sample_rate_ms;
2218         pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
2219         pid_params.p_gain_pct = policy->p_gain_pct;
2220         pid_params.i_gain_pct = policy->i_gain_pct;
2221         pid_params.d_gain_pct = policy->d_gain_pct;
2222         pid_params.deadband = policy->deadband;
2223         pid_params.setpoint = policy->setpoint;
2224 }
2225
2226 #ifdef CONFIG_ACPI
2227 static void intel_pstate_use_acpi_profile(void)
2228 {
2229         if (acpi_gbl_FADT.preferred_profile == PM_MOBILE)
2230                 pstate_funcs.get_target_pstate =
2231                                 get_target_pstate_use_cpu_load;
2232 }
2233 #else
2234 static void intel_pstate_use_acpi_profile(void)
2235 {
2236 }
2237 #endif
2238
2239 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2240 {
2241         pstate_funcs.get_max   = funcs->get_max;
2242         pstate_funcs.get_max_physical = funcs->get_max_physical;
2243         pstate_funcs.get_min   = funcs->get_min;
2244         pstate_funcs.get_turbo = funcs->get_turbo;
2245         pstate_funcs.get_scaling = funcs->get_scaling;
2246         pstate_funcs.get_val   = funcs->get_val;
2247         pstate_funcs.get_vid   = funcs->get_vid;
2248         pstate_funcs.get_target_pstate = funcs->get_target_pstate;
2249
2250         intel_pstate_use_acpi_profile();
2251 }
2252
2253 #ifdef CONFIG_ACPI
2254
2255 static bool __init intel_pstate_no_acpi_pss(void)
2256 {
2257         int i;
2258
2259         for_each_possible_cpu(i) {
2260                 acpi_status status;
2261                 union acpi_object *pss;
2262                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2263                 struct acpi_processor *pr = per_cpu(processors, i);
2264
2265                 if (!pr)
2266                         continue;
2267
2268                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2269                 if (ACPI_FAILURE(status))
2270                         continue;
2271
2272                 pss = buffer.pointer;
2273                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2274                         kfree(pss);
2275                         return false;
2276                 }
2277
2278                 kfree(pss);
2279         }
2280
2281         return true;
2282 }
2283
2284 static bool __init intel_pstate_has_acpi_ppc(void)
2285 {
2286         int i;
2287
2288         for_each_possible_cpu(i) {
2289                 struct acpi_processor *pr = per_cpu(processors, i);
2290
2291                 if (!pr)
2292                         continue;
2293                 if (acpi_has_method(pr->handle, "_PPC"))
2294                         return true;
2295         }
2296         return false;
2297 }
2298
2299 enum {
2300         PSS,
2301         PPC,
2302 };
2303
2304 struct hw_vendor_info {
2305         u16  valid;
2306         char oem_id[ACPI_OEM_ID_SIZE];
2307         char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
2308         int  oem_pwr_table;
2309 };
2310
2311 /* Hardware vendor-specific info that has its own power management modes */
2312 static struct hw_vendor_info vendor_info[] __initdata = {
2313         {1, "HP    ", "ProLiant", PSS},
2314         {1, "ORACLE", "X4-2    ", PPC},
2315         {1, "ORACLE", "X4-2L   ", PPC},
2316         {1, "ORACLE", "X4-2B   ", PPC},
2317         {1, "ORACLE", "X3-2    ", PPC},
2318         {1, "ORACLE", "X3-2L   ", PPC},
2319         {1, "ORACLE", "X3-2B   ", PPC},
2320         {1, "ORACLE", "X4470M2 ", PPC},
2321         {1, "ORACLE", "X4270M3 ", PPC},
2322         {1, "ORACLE", "X4270M2 ", PPC},
2323         {1, "ORACLE", "X4170M2 ", PPC},
2324         {1, "ORACLE", "X4170 M3", PPC},
2325         {1, "ORACLE", "X4275 M3", PPC},
2326         {1, "ORACLE", "X6-2    ", PPC},
2327         {1, "ORACLE", "Sudbury ", PPC},
2328         {0, "", ""},
2329 };
2330
2331 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2332 {
2333         struct acpi_table_header hdr;
2334         struct hw_vendor_info *v_info;
2335         const struct x86_cpu_id *id;
2336         u64 misc_pwr;
2337
2338         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2339         if (id) {
2340                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2341                 if ( misc_pwr & (1 << 8))
2342                         return true;
2343         }
2344
2345         if (acpi_disabled ||
2346             ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
2347                 return false;
2348
2349         for (v_info = vendor_info; v_info->valid; v_info++) {
2350                 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
2351                         !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2352                                                 ACPI_OEM_TABLE_ID_SIZE))
2353                         switch (v_info->oem_pwr_table) {
2354                         case PSS:
2355                                 return intel_pstate_no_acpi_pss();
2356                         case PPC:
2357                                 return intel_pstate_has_acpi_ppc() &&
2358                                         (!force_load);
2359                         }
2360         }
2361
2362         return false;
2363 }
2364
2365 static void intel_pstate_request_control_from_smm(void)
2366 {
2367         /*
2368          * It may be unsafe to request P-states control from SMM if _PPC support
2369          * has not been enabled.
2370          */
2371         if (acpi_ppc)
2372                 acpi_processor_pstate_control();
2373 }
2374 #else /* CONFIG_ACPI not enabled */
2375 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2376 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2377 static inline void intel_pstate_request_control_from_smm(void) {}
2378 #endif /* CONFIG_ACPI */
2379
2380 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2381         { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2382         {}
2383 };
2384
2385 static int __init intel_pstate_init(void)
2386 {
2387         int cpu, rc = 0;
2388         const struct x86_cpu_id *id;
2389         struct cpu_defaults *cpu_def;
2390
2391         if (no_load)
2392                 return -ENODEV;
2393
2394         if (x86_match_cpu(hwp_support_ids) && !no_hwp) {
2395                 copy_cpu_funcs(&core_params.funcs);
2396                 hwp_active++;
2397                 intel_pstate.attr = hwp_cpufreq_attrs;
2398                 goto hwp_cpu_matched;
2399         }
2400
2401         id = x86_match_cpu(intel_pstate_cpu_ids);
2402         if (!id)
2403                 return -ENODEV;
2404
2405         cpu_def = (struct cpu_defaults *)id->driver_data;
2406
2407         copy_pid_params(&cpu_def->pid_policy);
2408         copy_cpu_funcs(&cpu_def->funcs);
2409
2410         if (intel_pstate_msrs_not_valid())
2411                 return -ENODEV;
2412
2413 hwp_cpu_matched:
2414         /*
2415          * The Intel pstate driver will be ignored if the platform
2416          * firmware has its own power management modes.
2417          */
2418         if (intel_pstate_platform_pwr_mgmt_exists())
2419                 return -ENODEV;
2420
2421         pr_info("Intel P-state driver initializing\n");
2422
2423         all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2424         if (!all_cpu_data)
2425                 return -ENOMEM;
2426
2427         if (!hwp_active && hwp_only)
2428                 goto out;
2429
2430         intel_pstate_request_control_from_smm();
2431
2432         rc = cpufreq_register_driver(intel_pstate_driver);
2433         if (rc)
2434                 goto out;
2435
2436         intel_pstate_debug_expose_params();
2437         intel_pstate_sysfs_expose_params();
2438
2439         if (hwp_active)
2440                 pr_info("HWP enabled\n");
2441
2442         return rc;
2443 out:
2444         get_online_cpus();
2445         for_each_online_cpu(cpu) {
2446                 if (all_cpu_data[cpu]) {
2447                         if (intel_pstate_driver == &intel_pstate)
2448                                 intel_pstate_clear_update_util_hook(cpu);
2449
2450                         kfree(all_cpu_data[cpu]);
2451                 }
2452         }
2453
2454         put_online_cpus();
2455         vfree(all_cpu_data);
2456         return -ENODEV;
2457 }
2458 device_initcall(intel_pstate_init);
2459
2460 static int __init intel_pstate_setup(char *str)
2461 {
2462         if (!str)
2463                 return -EINVAL;
2464
2465         if (!strcmp(str, "disable")) {
2466                 no_load = 1;
2467         } else if (!strcmp(str, "passive")) {
2468                 pr_info("Passive mode enabled\n");
2469                 intel_pstate_driver = &intel_cpufreq;
2470                 no_hwp = 1;
2471         }
2472         if (!strcmp(str, "no_hwp")) {
2473                 pr_info("HWP disabled\n");
2474                 no_hwp = 1;
2475         }
2476         if (!strcmp(str, "force"))
2477                 force_load = 1;
2478         if (!strcmp(str, "hwp_only"))
2479                 hwp_only = 1;
2480         if (!strcmp(str, "per_cpu_perf_limits"))
2481                 per_cpu_limits = true;
2482
2483 #ifdef CONFIG_ACPI
2484         if (!strcmp(str, "support_acpi_ppc"))
2485                 acpi_ppc = true;
2486 #endif
2487
2488         return 0;
2489 }
2490 early_param("intel_pstate", intel_pstate_setup);
2491
2492 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2493 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2494 MODULE_LICENSE("GPL");