2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
29 #include <linux/acpi.h>
30 #include <linux/vmalloc.h>
31 #include <trace/events/power.h>
33 #include <asm/div64.h>
35 #include <asm/cpu_device_id.h>
36 #include <asm/cpufeature.h>
37 #include <asm/intel-family.h>
39 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
41 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
42 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
45 #include <acpi/processor.h>
46 #include <acpi/cppc_acpi.h>
50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
51 #define fp_toint(X) ((X) >> FRAC_BITS)
54 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
55 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
56 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
58 static inline int32_t mul_fp(int32_t x, int32_t y)
60 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
63 static inline int32_t div_fp(s64 x, s64 y)
65 return div64_s64((int64_t)x << FRAC_BITS, y);
68 static inline int ceiling_fp(int32_t x)
73 mask = (1 << FRAC_BITS) - 1;
79 static inline int32_t percent_fp(int percent)
81 return div_fp(percent, 100);
84 static inline u64 mul_ext_fp(u64 x, u64 y)
86 return (x * y) >> EXT_FRAC_BITS;
89 static inline u64 div_ext_fp(u64 x, u64 y)
91 return div64_u64(x << EXT_FRAC_BITS, y);
94 static inline int32_t percent_ext_fp(int percent)
96 return div_ext_fp(percent, 100);
100 * struct sample - Store performance sample
101 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
102 * performance during last sample period
103 * @busy_scaled: Scaled busy value which is used to calculate next
104 * P state. This can be different than core_avg_perf
105 * to account for cpu idle period
106 * @aperf: Difference of actual performance frequency clock count
107 * read from APERF MSR between last and current sample
108 * @mperf: Difference of maximum performance frequency clock count
109 * read from MPERF MSR between last and current sample
110 * @tsc: Difference of time stamp counter between last and
112 * @time: Current time from scheduler
114 * This structure is used in the cpudata structure to store performance sample
115 * data for choosing next P State.
118 int32_t core_avg_perf;
127 * struct pstate_data - Store P state data
128 * @current_pstate: Current requested P state
129 * @min_pstate: Min P state possible for this platform
130 * @max_pstate: Max P state possible for this platform
131 * @max_pstate_physical:This is physical Max P state for a processor
132 * This can be higher than the max_pstate which can
133 * be limited by platform thermal design power limits
134 * @scaling: Scaling factor to convert frequency to cpufreq
136 * @turbo_pstate: Max Turbo P state possible for this platform
137 * @max_freq: @max_pstate frequency in cpufreq units
138 * @turbo_freq: @turbo_pstate frequency in cpufreq units
140 * Stores the per cpu model P state limits and current P state.
146 int max_pstate_physical;
149 unsigned int max_freq;
150 unsigned int turbo_freq;
154 * struct vid_data - Stores voltage information data
155 * @min: VID data for this platform corresponding to
157 * @max: VID data corresponding to the highest P State.
158 * @turbo: VID data for turbo P state
159 * @ratio: Ratio of (vid max - vid min) /
160 * (max P state - Min P State)
162 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
163 * This data is used in Atom platforms, where in addition to target P state,
164 * the voltage data needs to be specified to select next P State.
174 * struct global_params - Global parameters, mostly tunable via sysfs.
175 * @no_turbo: Whether or not to use turbo P-states.
176 * @turbo_disabled: Whethet or not turbo P-states are available at all,
177 * based on the MSR_IA32_MISC_ENABLE value and whether or
178 * not the maximum reported turbo P-state is different from
179 * the maximum reported non-turbo one.
180 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
182 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
185 struct global_params {
193 * struct cpudata - Per CPU instance data storage
194 * @cpu: CPU number for this instance data
195 * @policy: CPUFreq policy value
196 * @update_util: CPUFreq utility callback information
197 * @update_util_set: CPUFreq utility callback is set
198 * @iowait_boost: iowait-related boost fraction
199 * @last_update: Time of the last update.
200 * @pstate: Stores P state limits for this CPU
201 * @vid: Stores VID limits for this CPU
202 * @last_sample_time: Last Sample time
203 * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented
204 * This shift is a multiplier to mperf delta to
205 * calculate CPU busy.
206 * @prev_aperf: Last APERF value read from APERF MSR
207 * @prev_mperf: Last MPERF value read from MPERF MSR
208 * @prev_tsc: Last timestamp counter (TSC) value
209 * @prev_cummulative_iowait: IO Wait time difference from last and
211 * @sample: Storage for storing last Sample data
212 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
213 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
214 * @acpi_perf_data: Stores ACPI perf information read from _PSS
215 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
216 * @epp_powersave: Last saved HWP energy performance preference
217 * (EPP) or energy performance bias (EPB),
218 * when policy switched to performance
219 * @epp_policy: Last saved policy used to set EPP/EPB
220 * @epp_default: Power on default HWP energy performance
222 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
225 * This structure stores per CPU instance data for all CPUs.
231 struct update_util_data update_util;
232 bool update_util_set;
234 struct pstate_data pstate;
238 u64 last_sample_time;
239 u64 aperf_mperf_shift;
243 u64 prev_cummulative_iowait;
244 struct sample sample;
245 int32_t min_perf_ratio;
246 int32_t max_perf_ratio;
248 struct acpi_processor_performance acpi_perf_data;
249 bool valid_pss_table;
251 unsigned int iowait_boost;
258 static struct cpudata **all_cpu_data;
261 * struct pstate_funcs - Per CPU model specific callbacks
262 * @get_max: Callback to get maximum non turbo effective P state
263 * @get_max_physical: Callback to get maximum non turbo physical P state
264 * @get_min: Callback to get minimum P state
265 * @get_turbo: Callback to get turbo P state
266 * @get_scaling: Callback to get frequency scaling factor
267 * @get_val: Callback to convert P state to actual MSR write value
268 * @get_vid: Callback to get VID data for Atom platforms
270 * Core and Atom CPU models have different way to get P State limits. This
271 * structure is used to store those callbacks.
273 struct pstate_funcs {
274 int (*get_max)(void);
275 int (*get_max_physical)(void);
276 int (*get_min)(void);
277 int (*get_turbo)(void);
278 int (*get_scaling)(void);
279 int (*get_aperf_mperf_shift)(void);
280 u64 (*get_val)(struct cpudata*, int pstate);
281 void (*get_vid)(struct cpudata *);
284 static struct pstate_funcs pstate_funcs __read_mostly;
286 static int hwp_active __read_mostly;
287 static bool per_cpu_limits __read_mostly;
289 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
292 static bool acpi_ppc;
295 static struct global_params global;
297 static DEFINE_MUTEX(intel_pstate_driver_lock);
298 static DEFINE_MUTEX(intel_pstate_limits_lock);
302 static bool intel_pstate_get_ppc_enable_status(void)
304 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
305 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
311 #ifdef CONFIG_ACPI_CPPC_LIB
313 /* The work item is needed to avoid CPU hotplug locking issues */
314 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
316 sched_set_itmt_support();
319 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
321 static void intel_pstate_set_itmt_prio(int cpu)
323 struct cppc_perf_caps cppc_perf;
324 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
327 ret = cppc_get_perf_caps(cpu, &cppc_perf);
332 * The priorities can be set regardless of whether or not
333 * sched_set_itmt_support(true) has been called and it is valid to
334 * update them at any time after it has been called.
336 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
338 if (max_highest_perf <= min_highest_perf) {
339 if (cppc_perf.highest_perf > max_highest_perf)
340 max_highest_perf = cppc_perf.highest_perf;
342 if (cppc_perf.highest_perf < min_highest_perf)
343 min_highest_perf = cppc_perf.highest_perf;
345 if (max_highest_perf > min_highest_perf) {
347 * This code can be run during CPU online under the
348 * CPU hotplug locks, so sched_set_itmt_support()
349 * cannot be called from here. Queue up a work item
352 schedule_work(&sched_itmt_work);
357 static void intel_pstate_set_itmt_prio(int cpu)
362 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
369 intel_pstate_set_itmt_prio(policy->cpu);
373 if (!intel_pstate_get_ppc_enable_status())
376 cpu = all_cpu_data[policy->cpu];
378 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
384 * Check if the control value in _PSS is for PERF_CTL MSR, which should
385 * guarantee that the states returned by it map to the states in our
388 if (cpu->acpi_perf_data.control_register.space_id !=
389 ACPI_ADR_SPACE_FIXED_HARDWARE)
393 * If there is only one entry _PSS, simply ignore _PSS and continue as
394 * usual without taking _PSS into account
396 if (cpu->acpi_perf_data.state_count < 2)
399 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
400 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
401 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
402 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
403 (u32) cpu->acpi_perf_data.states[i].core_frequency,
404 (u32) cpu->acpi_perf_data.states[i].power,
405 (u32) cpu->acpi_perf_data.states[i].control);
409 * The _PSS table doesn't contain whole turbo frequency range.
410 * This just contains +1 MHZ above the max non turbo frequency,
411 * with control value corresponding to max turbo ratio. But
412 * when cpufreq set policy is called, it will call with this
413 * max frequency, which will cause a reduced performance as
414 * this driver uses real max turbo frequency as the max
415 * frequency. So correct this frequency in _PSS table to
416 * correct max turbo frequency based on the turbo state.
417 * Also need to convert to MHz as _PSS freq is in MHz.
419 if (!global.turbo_disabled)
420 cpu->acpi_perf_data.states[0].core_frequency =
421 policy->cpuinfo.max_freq / 1000;
422 cpu->valid_pss_table = true;
423 pr_debug("_PPC limits will be enforced\n");
428 cpu->valid_pss_table = false;
429 acpi_processor_unregister_performance(policy->cpu);
432 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
436 cpu = all_cpu_data[policy->cpu];
437 if (!cpu->valid_pss_table)
440 acpi_processor_unregister_performance(policy->cpu);
443 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
447 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
452 static inline void update_turbo_state(void)
457 cpu = all_cpu_data[0];
458 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
459 global.turbo_disabled =
460 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
461 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
464 static int min_perf_pct_min(void)
466 struct cpudata *cpu = all_cpu_data[0];
467 int turbo_pstate = cpu->pstate.turbo_pstate;
469 return turbo_pstate ?
470 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
473 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
478 if (!static_cpu_has(X86_FEATURE_EPB))
481 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
485 return (s16)(epb & 0x0f);
488 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
492 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
494 * When hwp_req_data is 0, means that caller didn't read
495 * MSR_HWP_REQUEST, so need to read and get EPP.
498 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
503 epp = (hwp_req_data >> 24) & 0xff;
505 /* When there is no EPP present, HWP uses EPB settings */
506 epp = intel_pstate_get_epb(cpu_data);
512 static int intel_pstate_set_epb(int cpu, s16 pref)
517 if (!static_cpu_has(X86_FEATURE_EPB))
520 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
524 epb = (epb & ~0x0f) | pref;
525 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
531 * EPP/EPB display strings corresponding to EPP index in the
532 * energy_perf_strings[]
534 *-------------------------------------
537 * 2 balance_performance
541 static const char * const energy_perf_strings[] = {
544 "balance_performance",
549 static const unsigned int epp_values[] = {
551 HWP_EPP_BALANCE_PERFORMANCE,
552 HWP_EPP_BALANCE_POWERSAVE,
556 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
561 epp = intel_pstate_get_epp(cpu_data, 0);
565 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
566 if (epp == HWP_EPP_PERFORMANCE)
568 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
570 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
574 } else if (static_cpu_has(X86_FEATURE_EPB)) {
577 * 0x00-0x03 : Performance
578 * 0x04-0x07 : Balance performance
579 * 0x08-0x0B : Balance power
581 * The EPB is a 4 bit value, but our ranges restrict the
582 * value which can be set. Here only using top two bits
585 index = (epp >> 2) + 1;
591 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
598 epp = cpu_data->epp_default;
600 mutex_lock(&intel_pstate_limits_lock);
602 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
605 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
609 value &= ~GENMASK_ULL(31, 24);
612 epp = epp_values[pref_index - 1];
614 value |= (u64)epp << 24;
615 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
618 epp = (pref_index - 1) << 2;
619 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
622 mutex_unlock(&intel_pstate_limits_lock);
627 static ssize_t show_energy_performance_available_preferences(
628 struct cpufreq_policy *policy, char *buf)
633 while (energy_perf_strings[i] != NULL)
634 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
636 ret += sprintf(&buf[ret], "\n");
641 cpufreq_freq_attr_ro(energy_performance_available_preferences);
643 static ssize_t store_energy_performance_preference(
644 struct cpufreq_policy *policy, const char *buf, size_t count)
646 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
647 char str_preference[21];
650 ret = sscanf(buf, "%20s", str_preference);
654 while (energy_perf_strings[i] != NULL) {
655 if (!strcmp(str_preference, energy_perf_strings[i])) {
656 intel_pstate_set_energy_pref_index(cpu_data, i);
665 static ssize_t show_energy_performance_preference(
666 struct cpufreq_policy *policy, char *buf)
668 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
671 preference = intel_pstate_get_energy_pref_index(cpu_data);
675 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
678 cpufreq_freq_attr_rw(energy_performance_preference);
680 static struct freq_attr *hwp_cpufreq_attrs[] = {
681 &energy_performance_preference,
682 &energy_performance_available_preferences,
686 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
691 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
693 *current_max = HWP_GUARANTEED_PERF(cap);
695 *current_max = HWP_HIGHEST_PERF(cap);
697 *phy_max = HWP_HIGHEST_PERF(cap);
700 static void intel_pstate_hwp_set(unsigned int cpu)
702 struct cpudata *cpu_data = all_cpu_data[cpu];
707 max = cpu_data->max_perf_ratio;
708 min = cpu_data->min_perf_ratio;
710 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
713 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
715 value &= ~HWP_MIN_PERF(~0L);
716 value |= HWP_MIN_PERF(min);
718 value &= ~HWP_MAX_PERF(~0L);
719 value |= HWP_MAX_PERF(max);
721 if (cpu_data->epp_policy == cpu_data->policy)
724 cpu_data->epp_policy = cpu_data->policy;
726 if (cpu_data->epp_saved >= 0) {
727 epp = cpu_data->epp_saved;
728 cpu_data->epp_saved = -EINVAL;
732 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
733 epp = intel_pstate_get_epp(cpu_data, value);
734 cpu_data->epp_powersave = epp;
735 /* If EPP read was failed, then don't try to write */
741 /* skip setting EPP, when saved value is invalid */
742 if (cpu_data->epp_powersave < 0)
746 * No need to restore EPP when it is not zero. This
748 * - Policy is not changed
749 * - user has manually changed
750 * - Error reading EPB
752 epp = intel_pstate_get_epp(cpu_data, value);
756 epp = cpu_data->epp_powersave;
759 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
760 value &= ~GENMASK_ULL(31, 24);
761 value |= (u64)epp << 24;
763 intel_pstate_set_epb(cpu, epp);
766 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
769 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
771 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
776 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
781 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
783 static int intel_pstate_resume(struct cpufreq_policy *policy)
788 mutex_lock(&intel_pstate_limits_lock);
790 if (policy->cpu == 0)
791 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);
793 all_cpu_data[policy->cpu]->epp_policy = 0;
794 intel_pstate_hwp_set(policy->cpu);
796 mutex_unlock(&intel_pstate_limits_lock);
801 static void intel_pstate_update_policies(void)
805 for_each_possible_cpu(cpu)
806 cpufreq_update_policy(cpu);
809 /************************** sysfs begin ************************/
810 #define show_one(file_name, object) \
811 static ssize_t show_##file_name \
812 (struct kobject *kobj, struct attribute *attr, char *buf) \
814 return sprintf(buf, "%u\n", global.object); \
817 static ssize_t intel_pstate_show_status(char *buf);
818 static int intel_pstate_update_status(const char *buf, size_t size);
820 static ssize_t show_status(struct kobject *kobj,
821 struct attribute *attr, char *buf)
825 mutex_lock(&intel_pstate_driver_lock);
826 ret = intel_pstate_show_status(buf);
827 mutex_unlock(&intel_pstate_driver_lock);
832 static ssize_t store_status(struct kobject *a, struct attribute *b,
833 const char *buf, size_t count)
835 char *p = memchr(buf, '\n', count);
838 mutex_lock(&intel_pstate_driver_lock);
839 ret = intel_pstate_update_status(buf, p ? p - buf : count);
840 mutex_unlock(&intel_pstate_driver_lock);
842 return ret < 0 ? ret : count;
845 static ssize_t show_turbo_pct(struct kobject *kobj,
846 struct attribute *attr, char *buf)
849 int total, no_turbo, turbo_pct;
852 mutex_lock(&intel_pstate_driver_lock);
854 if (!intel_pstate_driver) {
855 mutex_unlock(&intel_pstate_driver_lock);
859 cpu = all_cpu_data[0];
861 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
862 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
863 turbo_fp = div_fp(no_turbo, total);
864 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
866 mutex_unlock(&intel_pstate_driver_lock);
868 return sprintf(buf, "%u\n", turbo_pct);
871 static ssize_t show_num_pstates(struct kobject *kobj,
872 struct attribute *attr, char *buf)
877 mutex_lock(&intel_pstate_driver_lock);
879 if (!intel_pstate_driver) {
880 mutex_unlock(&intel_pstate_driver_lock);
884 cpu = all_cpu_data[0];
885 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
887 mutex_unlock(&intel_pstate_driver_lock);
889 return sprintf(buf, "%u\n", total);
892 static ssize_t show_no_turbo(struct kobject *kobj,
893 struct attribute *attr, char *buf)
897 mutex_lock(&intel_pstate_driver_lock);
899 if (!intel_pstate_driver) {
900 mutex_unlock(&intel_pstate_driver_lock);
904 update_turbo_state();
905 if (global.turbo_disabled)
906 ret = sprintf(buf, "%u\n", global.turbo_disabled);
908 ret = sprintf(buf, "%u\n", global.no_turbo);
910 mutex_unlock(&intel_pstate_driver_lock);
915 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
916 const char *buf, size_t count)
921 ret = sscanf(buf, "%u", &input);
925 mutex_lock(&intel_pstate_driver_lock);
927 if (!intel_pstate_driver) {
928 mutex_unlock(&intel_pstate_driver_lock);
932 mutex_lock(&intel_pstate_limits_lock);
934 update_turbo_state();
935 if (global.turbo_disabled) {
936 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
937 mutex_unlock(&intel_pstate_limits_lock);
938 mutex_unlock(&intel_pstate_driver_lock);
942 global.no_turbo = clamp_t(int, input, 0, 1);
944 if (global.no_turbo) {
945 struct cpudata *cpu = all_cpu_data[0];
946 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
948 /* Squash the global minimum into the permitted range. */
949 if (global.min_perf_pct > pct)
950 global.min_perf_pct = pct;
953 mutex_unlock(&intel_pstate_limits_lock);
955 intel_pstate_update_policies();
957 mutex_unlock(&intel_pstate_driver_lock);
962 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
963 const char *buf, size_t count)
968 ret = sscanf(buf, "%u", &input);
972 mutex_lock(&intel_pstate_driver_lock);
974 if (!intel_pstate_driver) {
975 mutex_unlock(&intel_pstate_driver_lock);
979 mutex_lock(&intel_pstate_limits_lock);
981 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
983 mutex_unlock(&intel_pstate_limits_lock);
985 intel_pstate_update_policies();
987 mutex_unlock(&intel_pstate_driver_lock);
992 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
993 const char *buf, size_t count)
998 ret = sscanf(buf, "%u", &input);
1002 mutex_lock(&intel_pstate_driver_lock);
1004 if (!intel_pstate_driver) {
1005 mutex_unlock(&intel_pstate_driver_lock);
1009 mutex_lock(&intel_pstate_limits_lock);
1011 global.min_perf_pct = clamp_t(int, input,
1012 min_perf_pct_min(), global.max_perf_pct);
1014 mutex_unlock(&intel_pstate_limits_lock);
1016 intel_pstate_update_policies();
1018 mutex_unlock(&intel_pstate_driver_lock);
1023 show_one(max_perf_pct, max_perf_pct);
1024 show_one(min_perf_pct, min_perf_pct);
1026 define_one_global_rw(status);
1027 define_one_global_rw(no_turbo);
1028 define_one_global_rw(max_perf_pct);
1029 define_one_global_rw(min_perf_pct);
1030 define_one_global_ro(turbo_pct);
1031 define_one_global_ro(num_pstates);
1033 static struct attribute *intel_pstate_attributes[] = {
1041 static const struct attribute_group intel_pstate_attr_group = {
1042 .attrs = intel_pstate_attributes,
1045 static void __init intel_pstate_sysfs_expose_params(void)
1047 struct kobject *intel_pstate_kobject;
1050 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1051 &cpu_subsys.dev_root->kobj);
1052 if (WARN_ON(!intel_pstate_kobject))
1055 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1060 * If per cpu limits are enforced there are no global limits, so
1061 * return without creating max/min_perf_pct attributes
1066 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1069 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1073 /************************** sysfs end ************************/
1075 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1077 /* First disable HWP notification interrupt as we don't process them */
1078 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1079 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1081 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1082 cpudata->epp_policy = 0;
1083 if (cpudata->epp_default == -EINVAL)
1084 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1087 #define MSR_IA32_POWER_CTL_BIT_EE 19
1089 /* Disable energy efficiency optimization */
1090 static void intel_pstate_disable_ee(int cpu)
1095 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1099 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1100 pr_info("Disabling energy efficiency optimization\n");
1101 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1102 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1106 static int atom_get_min_pstate(void)
1110 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1111 return (value >> 8) & 0x7F;
1114 static int atom_get_max_pstate(void)
1118 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1119 return (value >> 16) & 0x7F;
1122 static int atom_get_turbo_pstate(void)
1126 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1127 return value & 0x7F;
1130 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1136 val = (u64)pstate << 8;
1137 if (global.no_turbo && !global.turbo_disabled)
1138 val |= (u64)1 << 32;
1140 vid_fp = cpudata->vid.min + mul_fp(
1141 int_tofp(pstate - cpudata->pstate.min_pstate),
1142 cpudata->vid.ratio);
1144 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1145 vid = ceiling_fp(vid_fp);
1147 if (pstate > cpudata->pstate.max_pstate)
1148 vid = cpudata->vid.turbo;
1153 static int silvermont_get_scaling(void)
1157 /* Defined in Table 35-6 from SDM (Sept 2015) */
1158 static int silvermont_freq_table[] = {
1159 83300, 100000, 133300, 116700, 80000};
1161 rdmsrl(MSR_FSB_FREQ, value);
1165 return silvermont_freq_table[i];
1168 static int airmont_get_scaling(void)
1172 /* Defined in Table 35-10 from SDM (Sept 2015) */
1173 static int airmont_freq_table[] = {
1174 83300, 100000, 133300, 116700, 80000,
1175 93300, 90000, 88900, 87500};
1177 rdmsrl(MSR_FSB_FREQ, value);
1181 return airmont_freq_table[i];
1184 static void atom_get_vid(struct cpudata *cpudata)
1188 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1189 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1190 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1191 cpudata->vid.ratio = div_fp(
1192 cpudata->vid.max - cpudata->vid.min,
1193 int_tofp(cpudata->pstate.max_pstate -
1194 cpudata->pstate.min_pstate));
1196 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1197 cpudata->vid.turbo = value & 0x7f;
1200 static int core_get_min_pstate(void)
1204 rdmsrl(MSR_PLATFORM_INFO, value);
1205 return (value >> 40) & 0xFF;
1208 static int core_get_max_pstate_physical(void)
1212 rdmsrl(MSR_PLATFORM_INFO, value);
1213 return (value >> 8) & 0xFF;
1216 static int core_get_tdp_ratio(u64 plat_info)
1218 /* Check how many TDP levels present */
1219 if (plat_info & 0x600000000) {
1225 /* Get the TDP level (0, 1, 2) to get ratios */
1226 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1230 /* TDP MSR are continuous starting at 0x648 */
1231 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1232 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1236 /* For level 1 and 2, bits[23:16] contain the ratio */
1237 if (tdp_ctrl & 0x03)
1240 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1241 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1243 return (int)tdp_ratio;
1249 static int core_get_max_pstate(void)
1257 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1258 max_pstate = (plat_info >> 8) & 0xFF;
1260 tdp_ratio = core_get_tdp_ratio(plat_info);
1265 /* Turbo activation ratio is not used on HWP platforms */
1269 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1273 /* Do some sanity checking for safety */
1274 tar_levels = tar & 0xff;
1275 if (tdp_ratio - 1 == tar_levels) {
1276 max_pstate = tar_levels;
1277 pr_debug("max_pstate=TAC %x\n", max_pstate);
1284 static int core_get_turbo_pstate(void)
1289 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1290 nont = core_get_max_pstate();
1291 ret = (value) & 255;
1297 static inline int core_get_scaling(void)
1302 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1306 val = (u64)pstate << 8;
1307 if (global.no_turbo && !global.turbo_disabled)
1308 val |= (u64)1 << 32;
1313 static int knl_get_aperf_mperf_shift(void)
1318 static int knl_get_turbo_pstate(void)
1323 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1324 nont = core_get_max_pstate();
1325 ret = (((value) >> 8) & 0xFF);
1331 static int intel_pstate_get_base_pstate(struct cpudata *cpu)
1333 return global.no_turbo || global.turbo_disabled ?
1334 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1337 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1339 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1340 cpu->pstate.current_pstate = pstate;
1342 * Generally, there is no guarantee that this code will always run on
1343 * the CPU being updated, so force the register update to run on the
1346 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1347 pstate_funcs.get_val(cpu, pstate));
1350 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1352 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1355 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1359 update_turbo_state();
1360 pstate = intel_pstate_get_base_pstate(cpu);
1361 pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1362 intel_pstate_set_pstate(cpu, pstate);
1365 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1367 cpu->pstate.min_pstate = pstate_funcs.get_min();
1368 cpu->pstate.max_pstate = pstate_funcs.get_max();
1369 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1370 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1371 cpu->pstate.scaling = pstate_funcs.get_scaling();
1372 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1373 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1375 if (pstate_funcs.get_aperf_mperf_shift)
1376 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1378 if (pstate_funcs.get_vid)
1379 pstate_funcs.get_vid(cpu);
1381 intel_pstate_set_min_pstate(cpu);
1384 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1386 struct sample *sample = &cpu->sample;
1388 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1391 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1394 unsigned long flags;
1397 local_irq_save(flags);
1398 rdmsrl(MSR_IA32_APERF, aperf);
1399 rdmsrl(MSR_IA32_MPERF, mperf);
1401 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1402 local_irq_restore(flags);
1405 local_irq_restore(flags);
1407 cpu->last_sample_time = cpu->sample.time;
1408 cpu->sample.time = time;
1409 cpu->sample.aperf = aperf;
1410 cpu->sample.mperf = mperf;
1411 cpu->sample.tsc = tsc;
1412 cpu->sample.aperf -= cpu->prev_aperf;
1413 cpu->sample.mperf -= cpu->prev_mperf;
1414 cpu->sample.tsc -= cpu->prev_tsc;
1416 cpu->prev_aperf = aperf;
1417 cpu->prev_mperf = mperf;
1418 cpu->prev_tsc = tsc;
1420 * First time this function is invoked in a given cycle, all of the
1421 * previous sample data fields are equal to zero or stale and they must
1422 * be populated with meaningful numbers for things to work, so assume
1423 * that sample.time will always be reset before setting the utilization
1424 * update hook and make the caller skip the sample then.
1426 if (cpu->last_sample_time) {
1427 intel_pstate_calc_avg_perf(cpu);
1433 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1435 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
1438 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1440 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1441 cpu->sample.core_avg_perf);
1444 static inline int32_t get_target_pstate(struct cpudata *cpu)
1446 struct sample *sample = &cpu->sample;
1447 int32_t busy_frac, boost;
1448 int target, avg_pstate;
1450 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1453 boost = cpu->iowait_boost;
1454 cpu->iowait_boost >>= 1;
1456 if (busy_frac < boost)
1459 sample->busy_scaled = busy_frac * 100;
1461 target = global.no_turbo || global.turbo_disabled ?
1462 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1463 target += target >> 2;
1464 target = mul_fp(target, busy_frac);
1465 if (target < cpu->pstate.min_pstate)
1466 target = cpu->pstate.min_pstate;
1469 * If the average P-state during the previous cycle was higher than the
1470 * current target, add 50% of the difference to the target to reduce
1471 * possible performance oscillations and offset possible performance
1472 * loss related to moving the workload from one CPU to another within
1475 avg_pstate = get_avg_pstate(cpu);
1476 if (avg_pstate > target)
1477 target += (avg_pstate - target) >> 1;
1482 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1484 int max_pstate = intel_pstate_get_base_pstate(cpu);
1487 min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1488 max_pstate = max(min_pstate, cpu->max_perf_ratio);
1489 return clamp_t(int, pstate, min_pstate, max_pstate);
1492 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1494 if (pstate == cpu->pstate.current_pstate)
1497 cpu->pstate.current_pstate = pstate;
1498 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1501 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
1503 int from = cpu->pstate.current_pstate;
1504 struct sample *sample;
1507 update_turbo_state();
1509 target_pstate = get_target_pstate(cpu);
1510 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1511 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1512 intel_pstate_update_pstate(cpu, target_pstate);
1514 sample = &cpu->sample;
1515 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1516 fp_toint(sample->busy_scaled),
1518 cpu->pstate.current_pstate,
1522 get_avg_frequency(cpu),
1523 fp_toint(cpu->iowait_boost * 100));
1526 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1529 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1532 /* Don't allow remote callbacks */
1533 if (smp_processor_id() != cpu->cpu)
1536 if (flags & SCHED_CPUFREQ_IOWAIT) {
1537 cpu->iowait_boost = int_tofp(1);
1538 cpu->last_update = time;
1540 * The last time the busy was 100% so P-state was max anyway
1541 * so avoid overhead of computation.
1543 if (fp_toint(cpu->sample.busy_scaled) == 100)
1547 } else if (cpu->iowait_boost) {
1548 /* Clear iowait_boost if the CPU may have been idle. */
1549 delta_ns = time - cpu->last_update;
1550 if (delta_ns > TICK_NSEC)
1551 cpu->iowait_boost = 0;
1553 cpu->last_update = time;
1554 delta_ns = time - cpu->sample.time;
1555 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
1559 if (intel_pstate_sample(cpu, time))
1560 intel_pstate_adjust_pstate(cpu);
1563 static struct pstate_funcs core_funcs = {
1564 .get_max = core_get_max_pstate,
1565 .get_max_physical = core_get_max_pstate_physical,
1566 .get_min = core_get_min_pstate,
1567 .get_turbo = core_get_turbo_pstate,
1568 .get_scaling = core_get_scaling,
1569 .get_val = core_get_val,
1572 static const struct pstate_funcs silvermont_funcs = {
1573 .get_max = atom_get_max_pstate,
1574 .get_max_physical = atom_get_max_pstate,
1575 .get_min = atom_get_min_pstate,
1576 .get_turbo = atom_get_turbo_pstate,
1577 .get_val = atom_get_val,
1578 .get_scaling = silvermont_get_scaling,
1579 .get_vid = atom_get_vid,
1582 static const struct pstate_funcs airmont_funcs = {
1583 .get_max = atom_get_max_pstate,
1584 .get_max_physical = atom_get_max_pstate,
1585 .get_min = atom_get_min_pstate,
1586 .get_turbo = atom_get_turbo_pstate,
1587 .get_val = atom_get_val,
1588 .get_scaling = airmont_get_scaling,
1589 .get_vid = atom_get_vid,
1592 static const struct pstate_funcs knl_funcs = {
1593 .get_max = core_get_max_pstate,
1594 .get_max_physical = core_get_max_pstate_physical,
1595 .get_min = core_get_min_pstate,
1596 .get_turbo = knl_get_turbo_pstate,
1597 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
1598 .get_scaling = core_get_scaling,
1599 .get_val = core_get_val,
1602 #define ICPU(model, policy) \
1603 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1604 (unsigned long)&policy }
1606 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1607 ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs),
1608 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs),
1609 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_funcs),
1610 ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs),
1611 ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs),
1612 ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs),
1613 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs),
1614 ICPU(INTEL_FAM6_HASWELL_X, core_funcs),
1615 ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs),
1616 ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs),
1617 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs),
1618 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs),
1619 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs),
1620 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1621 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1622 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1623 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs),
1624 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs),
1625 ICPU(INTEL_FAM6_ATOM_GOLDMONT, core_funcs),
1626 ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE, core_funcs),
1627 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1630 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1632 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1633 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1634 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1635 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1639 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1640 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
1644 static int intel_pstate_init_cpu(unsigned int cpunum)
1646 struct cpudata *cpu;
1648 cpu = all_cpu_data[cpunum];
1651 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1655 all_cpu_data[cpunum] = cpu;
1657 cpu->epp_default = -EINVAL;
1658 cpu->epp_powersave = -EINVAL;
1659 cpu->epp_saved = -EINVAL;
1662 cpu = all_cpu_data[cpunum];
1667 const struct x86_cpu_id *id;
1669 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1671 intel_pstate_disable_ee(cpunum);
1673 intel_pstate_hwp_enable(cpu);
1676 intel_pstate_get_cpu_pstates(cpu);
1678 pr_debug("controlling: cpu %d\n", cpunum);
1683 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1685 struct cpudata *cpu = all_cpu_data[cpu_num];
1690 if (cpu->update_util_set)
1693 /* Prevent intel_pstate_update_util() from using stale data. */
1694 cpu->sample.time = 0;
1695 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1696 intel_pstate_update_util);
1697 cpu->update_util_set = true;
1700 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1702 struct cpudata *cpu_data = all_cpu_data[cpu];
1704 if (!cpu_data->update_util_set)
1707 cpufreq_remove_update_util_hook(cpu);
1708 cpu_data->update_util_set = false;
1709 synchronize_sched();
1712 static int intel_pstate_get_max_freq(struct cpudata *cpu)
1714 return global.turbo_disabled || global.no_turbo ?
1715 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1718 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1719 struct cpudata *cpu)
1721 int max_freq = intel_pstate_get_max_freq(cpu);
1722 int32_t max_policy_perf, min_policy_perf;
1723 int max_state, turbo_max;
1726 * HWP needs some special consideration, because on BDX the
1727 * HWP_REQUEST uses abstract value to represent performance
1728 * rather than pure ratios.
1731 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
1733 max_state = intel_pstate_get_base_pstate(cpu);
1734 turbo_max = cpu->pstate.turbo_pstate;
1737 max_policy_perf = max_state * policy->max / max_freq;
1738 if (policy->max == policy->min) {
1739 min_policy_perf = max_policy_perf;
1741 min_policy_perf = max_state * policy->min / max_freq;
1742 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1743 0, max_policy_perf);
1746 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
1747 policy->cpu, max_state,
1748 min_policy_perf, max_policy_perf);
1750 /* Normalize user input to [min_perf, max_perf] */
1751 if (per_cpu_limits) {
1752 cpu->min_perf_ratio = min_policy_perf;
1753 cpu->max_perf_ratio = max_policy_perf;
1755 int32_t global_min, global_max;
1757 /* Global limits are in percent of the maximum turbo P-state. */
1758 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
1759 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
1760 global_min = clamp_t(int32_t, global_min, 0, global_max);
1762 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
1763 global_min, global_max);
1765 cpu->min_perf_ratio = max(min_policy_perf, global_min);
1766 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
1767 cpu->max_perf_ratio = min(max_policy_perf, global_max);
1768 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
1770 /* Make sure min_perf <= max_perf */
1771 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
1772 cpu->max_perf_ratio);
1775 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
1776 cpu->max_perf_ratio,
1777 cpu->min_perf_ratio);
1780 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1782 struct cpudata *cpu;
1784 if (!policy->cpuinfo.max_freq)
1787 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1788 policy->cpuinfo.max_freq, policy->max);
1790 cpu = all_cpu_data[policy->cpu];
1791 cpu->policy = policy->policy;
1793 mutex_lock(&intel_pstate_limits_lock);
1795 intel_pstate_update_perf_limits(policy, cpu);
1797 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
1799 * NOHZ_FULL CPUs need this as the governor callback may not
1800 * be invoked on them.
1802 intel_pstate_clear_update_util_hook(policy->cpu);
1803 intel_pstate_max_within_limits(cpu);
1805 intel_pstate_set_update_util_hook(policy->cpu);
1809 intel_pstate_hwp_set(policy->cpu);
1811 mutex_unlock(&intel_pstate_limits_lock);
1816 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
1817 struct cpudata *cpu)
1819 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
1820 policy->max < policy->cpuinfo.max_freq &&
1821 policy->max > cpu->pstate.max_freq) {
1822 pr_debug("policy->max > max non turbo frequency\n");
1823 policy->max = policy->cpuinfo.max_freq;
1827 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
1829 struct cpudata *cpu = all_cpu_data[policy->cpu];
1831 update_turbo_state();
1832 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
1833 intel_pstate_get_max_freq(cpu));
1835 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
1836 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
1839 intel_pstate_adjust_policy_max(policy, cpu);
1844 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
1846 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
1849 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
1851 pr_debug("CPU %d exiting\n", policy->cpu);
1853 intel_pstate_clear_update_util_hook(policy->cpu);
1855 intel_pstate_hwp_save_state(policy);
1857 intel_cpufreq_stop_cpu(policy);
1860 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
1862 intel_pstate_exit_perf_limits(policy);
1864 policy->fast_switch_possible = false;
1869 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
1871 struct cpudata *cpu;
1874 rc = intel_pstate_init_cpu(policy->cpu);
1878 cpu = all_cpu_data[policy->cpu];
1880 cpu->max_perf_ratio = 0xFF;
1881 cpu->min_perf_ratio = 0;
1883 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
1884 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1886 /* cpuinfo and default policy values */
1887 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
1888 update_turbo_state();
1889 policy->cpuinfo.max_freq = global.turbo_disabled ?
1890 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1891 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
1893 intel_pstate_init_acpi_perf_limits(policy);
1895 policy->fast_switch_possible = true;
1900 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
1902 int ret = __intel_pstate_cpu_init(policy);
1907 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
1908 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
1910 policy->policy = CPUFREQ_POLICY_POWERSAVE;
1915 static struct cpufreq_driver intel_pstate = {
1916 .flags = CPUFREQ_CONST_LOOPS,
1917 .verify = intel_pstate_verify_policy,
1918 .setpolicy = intel_pstate_set_policy,
1919 .suspend = intel_pstate_hwp_save_state,
1920 .resume = intel_pstate_resume,
1921 .init = intel_pstate_cpu_init,
1922 .exit = intel_pstate_cpu_exit,
1923 .stop_cpu = intel_pstate_stop_cpu,
1924 .name = "intel_pstate",
1927 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
1929 struct cpudata *cpu = all_cpu_data[policy->cpu];
1931 update_turbo_state();
1932 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
1933 intel_pstate_get_max_freq(cpu));
1935 intel_pstate_adjust_policy_max(policy, cpu);
1937 intel_pstate_update_perf_limits(policy, cpu);
1942 /* Use of trace in passive mode:
1944 * In passive mode the trace core_busy field (also known as the
1945 * performance field, and lablelled as such on the graphs; also known as
1946 * core_avg_perf) is not needed and so is re-assigned to indicate if the
1947 * driver call was via the normal or fast switch path. Various graphs
1948 * output from the intel_pstate_tracer.py utility that include core_busy
1949 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
1950 * so we use 10 to indicate the the normal path through the driver, and
1951 * 90 to indicate the fast switch path through the driver.
1952 * The scaled_busy field is not used, and is set to 0.
1955 #define INTEL_PSTATE_TRACE_TARGET 10
1956 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
1958 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
1960 struct sample *sample;
1962 if (!trace_pstate_sample_enabled())
1965 if (!intel_pstate_sample(cpu, ktime_get()))
1968 sample = &cpu->sample;
1969 trace_pstate_sample(trace_type,
1972 cpu->pstate.current_pstate,
1976 get_avg_frequency(cpu),
1977 fp_toint(cpu->iowait_boost * 100));
1980 static int intel_cpufreq_target(struct cpufreq_policy *policy,
1981 unsigned int target_freq,
1982 unsigned int relation)
1984 struct cpudata *cpu = all_cpu_data[policy->cpu];
1985 struct cpufreq_freqs freqs;
1986 int target_pstate, old_pstate;
1988 update_turbo_state();
1990 freqs.old = policy->cur;
1991 freqs.new = target_freq;
1993 cpufreq_freq_transition_begin(policy, &freqs);
1995 case CPUFREQ_RELATION_L:
1996 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
1998 case CPUFREQ_RELATION_H:
1999 target_pstate = freqs.new / cpu->pstate.scaling;
2002 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2005 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2006 old_pstate = cpu->pstate.current_pstate;
2007 if (target_pstate != cpu->pstate.current_pstate) {
2008 cpu->pstate.current_pstate = target_pstate;
2009 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2010 pstate_funcs.get_val(cpu, target_pstate));
2012 freqs.new = target_pstate * cpu->pstate.scaling;
2013 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_TARGET, old_pstate);
2014 cpufreq_freq_transition_end(policy, &freqs, false);
2019 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2020 unsigned int target_freq)
2022 struct cpudata *cpu = all_cpu_data[policy->cpu];
2023 int target_pstate, old_pstate;
2025 update_turbo_state();
2027 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2028 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2029 old_pstate = cpu->pstate.current_pstate;
2030 intel_pstate_update_pstate(cpu, target_pstate);
2031 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2032 return target_pstate * cpu->pstate.scaling;
2035 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2037 int ret = __intel_pstate_cpu_init(policy);
2042 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2043 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2044 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2045 policy->cur = policy->cpuinfo.min_freq;
2050 static struct cpufreq_driver intel_cpufreq = {
2051 .flags = CPUFREQ_CONST_LOOPS,
2052 .verify = intel_cpufreq_verify_policy,
2053 .target = intel_cpufreq_target,
2054 .fast_switch = intel_cpufreq_fast_switch,
2055 .init = intel_cpufreq_cpu_init,
2056 .exit = intel_pstate_cpu_exit,
2057 .stop_cpu = intel_cpufreq_stop_cpu,
2058 .name = "intel_cpufreq",
2061 static struct cpufreq_driver *default_driver = &intel_pstate;
2063 static void intel_pstate_driver_cleanup(void)
2068 for_each_online_cpu(cpu) {
2069 if (all_cpu_data[cpu]) {
2070 if (intel_pstate_driver == &intel_pstate)
2071 intel_pstate_clear_update_util_hook(cpu);
2073 kfree(all_cpu_data[cpu]);
2074 all_cpu_data[cpu] = NULL;
2078 intel_pstate_driver = NULL;
2081 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2085 memset(&global, 0, sizeof(global));
2086 global.max_perf_pct = 100;
2088 intel_pstate_driver = driver;
2089 ret = cpufreq_register_driver(intel_pstate_driver);
2091 intel_pstate_driver_cleanup();
2095 global.min_perf_pct = min_perf_pct_min();
2100 static int intel_pstate_unregister_driver(void)
2105 cpufreq_unregister_driver(intel_pstate_driver);
2106 intel_pstate_driver_cleanup();
2111 static ssize_t intel_pstate_show_status(char *buf)
2113 if (!intel_pstate_driver)
2114 return sprintf(buf, "off\n");
2116 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2117 "active" : "passive");
2120 static int intel_pstate_update_status(const char *buf, size_t size)
2124 if (size == 3 && !strncmp(buf, "off", size))
2125 return intel_pstate_driver ?
2126 intel_pstate_unregister_driver() : -EINVAL;
2128 if (size == 6 && !strncmp(buf, "active", size)) {
2129 if (intel_pstate_driver) {
2130 if (intel_pstate_driver == &intel_pstate)
2133 ret = intel_pstate_unregister_driver();
2138 return intel_pstate_register_driver(&intel_pstate);
2141 if (size == 7 && !strncmp(buf, "passive", size)) {
2142 if (intel_pstate_driver) {
2143 if (intel_pstate_driver == &intel_cpufreq)
2146 ret = intel_pstate_unregister_driver();
2151 return intel_pstate_register_driver(&intel_cpufreq);
2157 static int no_load __initdata;
2158 static int no_hwp __initdata;
2159 static int hwp_only __initdata;
2160 static unsigned int force_load __initdata;
2162 static int __init intel_pstate_msrs_not_valid(void)
2164 if (!pstate_funcs.get_max() ||
2165 !pstate_funcs.get_min() ||
2166 !pstate_funcs.get_turbo())
2172 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2174 pstate_funcs.get_max = funcs->get_max;
2175 pstate_funcs.get_max_physical = funcs->get_max_physical;
2176 pstate_funcs.get_min = funcs->get_min;
2177 pstate_funcs.get_turbo = funcs->get_turbo;
2178 pstate_funcs.get_scaling = funcs->get_scaling;
2179 pstate_funcs.get_val = funcs->get_val;
2180 pstate_funcs.get_vid = funcs->get_vid;
2181 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
2186 static bool __init intel_pstate_no_acpi_pss(void)
2190 for_each_possible_cpu(i) {
2192 union acpi_object *pss;
2193 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2194 struct acpi_processor *pr = per_cpu(processors, i);
2199 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2200 if (ACPI_FAILURE(status))
2203 pss = buffer.pointer;
2204 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2215 static bool __init intel_pstate_has_acpi_ppc(void)
2219 for_each_possible_cpu(i) {
2220 struct acpi_processor *pr = per_cpu(processors, i);
2224 if (acpi_has_method(pr->handle, "_PPC"))
2235 /* Hardware vendor-specific info that has its own power management modes */
2236 static struct acpi_platform_list plat_info[] __initdata = {
2237 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS},
2238 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2239 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2240 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2241 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2242 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2243 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2244 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2245 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2246 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2247 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2248 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2249 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2250 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2251 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2255 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2257 const struct x86_cpu_id *id;
2261 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2263 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2264 if ( misc_pwr & (1 << 8))
2268 idx = acpi_match_platform_list(plat_info);
2272 switch (plat_info[idx].data) {
2274 return intel_pstate_no_acpi_pss();
2276 return intel_pstate_has_acpi_ppc() && !force_load;
2282 static void intel_pstate_request_control_from_smm(void)
2285 * It may be unsafe to request P-states control from SMM if _PPC support
2286 * has not been enabled.
2289 acpi_processor_pstate_control();
2291 #else /* CONFIG_ACPI not enabled */
2292 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2293 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2294 static inline void intel_pstate_request_control_from_smm(void) {}
2295 #endif /* CONFIG_ACPI */
2297 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2298 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2302 static int __init intel_pstate_init(void)
2309 if (x86_match_cpu(hwp_support_ids)) {
2310 copy_cpu_funcs(&core_funcs);
2313 intel_pstate.attr = hwp_cpufreq_attrs;
2314 goto hwp_cpu_matched;
2317 const struct x86_cpu_id *id;
2319 id = x86_match_cpu(intel_pstate_cpu_ids);
2323 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2326 if (intel_pstate_msrs_not_valid())
2331 * The Intel pstate driver will be ignored if the platform
2332 * firmware has its own power management modes.
2334 if (intel_pstate_platform_pwr_mgmt_exists())
2337 if (!hwp_active && hwp_only)
2340 pr_info("Intel P-state driver initializing\n");
2342 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2346 intel_pstate_request_control_from_smm();
2348 intel_pstate_sysfs_expose_params();
2350 mutex_lock(&intel_pstate_driver_lock);
2351 rc = intel_pstate_register_driver(default_driver);
2352 mutex_unlock(&intel_pstate_driver_lock);
2357 pr_info("HWP enabled\n");
2361 device_initcall(intel_pstate_init);
2363 static int __init intel_pstate_setup(char *str)
2368 if (!strcmp(str, "disable")) {
2370 } else if (!strcmp(str, "passive")) {
2371 pr_info("Passive mode enabled\n");
2372 default_driver = &intel_cpufreq;
2375 if (!strcmp(str, "no_hwp")) {
2376 pr_info("HWP disabled\n");
2379 if (!strcmp(str, "force"))
2381 if (!strcmp(str, "hwp_only"))
2383 if (!strcmp(str, "per_cpu_perf_limits"))
2384 per_cpu_limits = true;
2387 if (!strcmp(str, "support_acpi_ppc"))
2393 early_param("intel_pstate", intel_pstate_setup);
2395 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2396 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2397 MODULE_LICENSE("GPL");