cpufreq: imx6q: Fix handling EPROBE_DEFER from regulator
[linux-2.6-block.git] / drivers / cpufreq / imx6q-cpufreq.c
1 /*
2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8
9 #include <linux/clk.h>
10 #include <linux/cpu.h>
11 #include <linux/cpufreq.h>
12 #include <linux/err.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/pm_opp.h>
16 #include <linux/platform_device.h>
17 #include <linux/regulator/consumer.h>
18
19 #define PU_SOC_VOLTAGE_NORMAL   1250000
20 #define PU_SOC_VOLTAGE_HIGH     1275000
21 #define FREQ_1P2_GHZ            1200000000
22
23 static struct regulator *arm_reg;
24 static struct regulator *pu_reg;
25 static struct regulator *soc_reg;
26
27 static struct clk *arm_clk;
28 static struct clk *pll1_sys_clk;
29 static struct clk *pll1_sw_clk;
30 static struct clk *step_clk;
31 static struct clk *pll2_pfd2_396m_clk;
32
33 /* clk used by i.MX6UL */
34 static struct clk *pll2_bus_clk;
35 static struct clk *secondary_sel_clk;
36
37 static struct device *cpu_dev;
38 static bool free_opp;
39 static struct cpufreq_frequency_table *freq_table;
40 static unsigned int transition_latency;
41
42 static u32 *imx6_soc_volt;
43 static u32 soc_opp_count;
44
45 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
46 {
47         struct dev_pm_opp *opp;
48         unsigned long freq_hz, volt, volt_old;
49         unsigned int old_freq, new_freq;
50         int ret;
51
52         new_freq = freq_table[index].frequency;
53         freq_hz = new_freq * 1000;
54         old_freq = clk_get_rate(arm_clk) / 1000;
55
56         opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
57         if (IS_ERR(opp)) {
58                 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
59                 return PTR_ERR(opp);
60         }
61
62         volt = dev_pm_opp_get_voltage(opp);
63         dev_pm_opp_put(opp);
64
65         volt_old = regulator_get_voltage(arm_reg);
66
67         dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
68                 old_freq / 1000, volt_old / 1000,
69                 new_freq / 1000, volt / 1000);
70
71         /* scaling up?  scale voltage before frequency */
72         if (new_freq > old_freq) {
73                 if (!IS_ERR(pu_reg)) {
74                         ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
75                         if (ret) {
76                                 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
77                                 return ret;
78                         }
79                 }
80                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
81                 if (ret) {
82                         dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
83                         return ret;
84                 }
85                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
86                 if (ret) {
87                         dev_err(cpu_dev,
88                                 "failed to scale vddarm up: %d\n", ret);
89                         return ret;
90                 }
91         }
92
93         /*
94          * The setpoints are selected per PLL/PDF frequencies, so we need to
95          * reprogram PLL for frequency scaling.  The procedure of reprogramming
96          * PLL1 is as below.
97          * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
98          * flow is slightly different from other i.MX6 OSC.
99          * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
100          *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
101          *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
102          *  - Disable pll2_pfd2_396m_clk
103          */
104         if (of_machine_is_compatible("fsl,imx6ul")) {
105                 /*
106                  * When changing pll1_sw_clk's parent to pll1_sys_clk,
107                  * CPU may run at higher than 528MHz, this will lead to
108                  * the system unstable if the voltage is lower than the
109                  * voltage of 528MHz, so lower the CPU frequency to one
110                  * half before changing CPU frequency.
111                  */
112                 clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
113                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
114                 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
115                         clk_set_parent(secondary_sel_clk, pll2_bus_clk);
116                 else
117                         clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
118                 clk_set_parent(step_clk, secondary_sel_clk);
119                 clk_set_parent(pll1_sw_clk, step_clk);
120         } else {
121                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
122                 clk_set_parent(pll1_sw_clk, step_clk);
123                 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
124                         clk_set_rate(pll1_sys_clk, new_freq * 1000);
125                         clk_set_parent(pll1_sw_clk, pll1_sys_clk);
126                 }
127         }
128
129         /* Ensure the arm clock divider is what we expect */
130         ret = clk_set_rate(arm_clk, new_freq * 1000);
131         if (ret) {
132                 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
133                 regulator_set_voltage_tol(arm_reg, volt_old, 0);
134                 return ret;
135         }
136
137         /* scaling down?  scale voltage after frequency */
138         if (new_freq < old_freq) {
139                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
140                 if (ret) {
141                         dev_warn(cpu_dev,
142                                  "failed to scale vddarm down: %d\n", ret);
143                         ret = 0;
144                 }
145                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
146                 if (ret) {
147                         dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
148                         ret = 0;
149                 }
150                 if (!IS_ERR(pu_reg)) {
151                         ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
152                         if (ret) {
153                                 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
154                                 ret = 0;
155                         }
156                 }
157         }
158
159         return 0;
160 }
161
162 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
163 {
164         policy->clk = arm_clk;
165         return cpufreq_generic_init(policy, freq_table, transition_latency);
166 }
167
168 static struct cpufreq_driver imx6q_cpufreq_driver = {
169         .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
170         .verify = cpufreq_generic_frequency_table_verify,
171         .target_index = imx6q_set_target,
172         .get = cpufreq_generic_get,
173         .init = imx6q_cpufreq_init,
174         .name = "imx6q-cpufreq",
175         .attr = cpufreq_generic_attr,
176 };
177
178 static int imx6q_cpufreq_probe(struct platform_device *pdev)
179 {
180         struct device_node *np;
181         struct dev_pm_opp *opp;
182         unsigned long min_volt, max_volt;
183         int num, ret;
184         const struct property *prop;
185         const __be32 *val;
186         u32 nr, i, j;
187
188         cpu_dev = get_cpu_device(0);
189         if (!cpu_dev) {
190                 pr_err("failed to get cpu0 device\n");
191                 return -ENODEV;
192         }
193
194         np = of_node_get(cpu_dev->of_node);
195         if (!np) {
196                 dev_err(cpu_dev, "failed to find cpu0 node\n");
197                 return -ENOENT;
198         }
199
200         arm_clk = clk_get(cpu_dev, "arm");
201         pll1_sys_clk = clk_get(cpu_dev, "pll1_sys");
202         pll1_sw_clk = clk_get(cpu_dev, "pll1_sw");
203         step_clk = clk_get(cpu_dev, "step");
204         pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m");
205         if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
206             IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
207                 dev_err(cpu_dev, "failed to get clocks\n");
208                 ret = -ENOENT;
209                 goto put_clk;
210         }
211
212         if (of_machine_is_compatible("fsl,imx6ul")) {
213                 pll2_bus_clk = clk_get(cpu_dev, "pll2_bus");
214                 secondary_sel_clk = clk_get(cpu_dev, "secondary_sel");
215                 if (IS_ERR(pll2_bus_clk) || IS_ERR(secondary_sel_clk)) {
216                         dev_err(cpu_dev, "failed to get clocks specific to imx6ul\n");
217                         ret = -ENOENT;
218                         goto put_clk;
219                 }
220         }
221
222         arm_reg = regulator_get(cpu_dev, "arm");
223         pu_reg = regulator_get_optional(cpu_dev, "pu");
224         soc_reg = regulator_get(cpu_dev, "soc");
225         if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
226                         PTR_ERR(soc_reg) == -EPROBE_DEFER ||
227                         PTR_ERR(pu_reg) == -EPROBE_DEFER) {
228                 ret = -EPROBE_DEFER;
229                 dev_dbg(cpu_dev, "regulators not ready, defer\n");
230                 goto put_reg;
231         }
232         if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
233                 dev_err(cpu_dev, "failed to get regulators\n");
234                 ret = -ENOENT;
235                 goto put_reg;
236         }
237
238         /*
239          * We expect an OPP table supplied by platform.
240          * Just, incase the platform did not supply the OPP
241          * table, it will try to get it.
242          */
243         num = dev_pm_opp_get_opp_count(cpu_dev);
244         if (num < 0) {
245                 ret = dev_pm_opp_of_add_table(cpu_dev);
246                 if (ret < 0) {
247                         dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
248                         goto put_reg;
249                 }
250
251                 /* Because we have added the OPPs here, we must free them */
252                 free_opp = true;
253
254                 num = dev_pm_opp_get_opp_count(cpu_dev);
255                 if (num < 0) {
256                         ret = num;
257                         dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
258                         goto out_free_opp;
259                 }
260         }
261
262         ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
263         if (ret) {
264                 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
265                 goto put_reg;
266         }
267
268         /* Make imx6_soc_volt array's size same as arm opp number */
269         imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL);
270         if (imx6_soc_volt == NULL) {
271                 ret = -ENOMEM;
272                 goto free_freq_table;
273         }
274
275         prop = of_find_property(np, "fsl,soc-operating-points", NULL);
276         if (!prop || !prop->value)
277                 goto soc_opp_out;
278
279         /*
280          * Each OPP is a set of tuples consisting of frequency and
281          * voltage like <freq-kHz vol-uV>.
282          */
283         nr = prop->length / sizeof(u32);
284         if (nr % 2 || (nr / 2) < num)
285                 goto soc_opp_out;
286
287         for (j = 0; j < num; j++) {
288                 val = prop->value;
289                 for (i = 0; i < nr / 2; i++) {
290                         unsigned long freq = be32_to_cpup(val++);
291                         unsigned long volt = be32_to_cpup(val++);
292                         if (freq_table[j].frequency == freq) {
293                                 imx6_soc_volt[soc_opp_count++] = volt;
294                                 break;
295                         }
296                 }
297         }
298
299 soc_opp_out:
300         /* use fixed soc opp volt if no valid soc opp info found in dtb */
301         if (soc_opp_count != num) {
302                 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
303                 for (j = 0; j < num; j++)
304                         imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
305                 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
306                         imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
307         }
308
309         if (of_property_read_u32(np, "clock-latency", &transition_latency))
310                 transition_latency = CPUFREQ_ETERNAL;
311
312         /*
313          * Calculate the ramp time for max voltage change in the
314          * VDDSOC and VDDPU regulators.
315          */
316         ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
317         if (ret > 0)
318                 transition_latency += ret * 1000;
319         if (!IS_ERR(pu_reg)) {
320                 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
321                 if (ret > 0)
322                         transition_latency += ret * 1000;
323         }
324
325         /*
326          * OPP is maintained in order of increasing frequency, and
327          * freq_table initialised from OPP is therefore sorted in the
328          * same order.
329          */
330         opp = dev_pm_opp_find_freq_exact(cpu_dev,
331                                   freq_table[0].frequency * 1000, true);
332         min_volt = dev_pm_opp_get_voltage(opp);
333         dev_pm_opp_put(opp);
334         opp = dev_pm_opp_find_freq_exact(cpu_dev,
335                                   freq_table[--num].frequency * 1000, true);
336         max_volt = dev_pm_opp_get_voltage(opp);
337         dev_pm_opp_put(opp);
338
339         ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
340         if (ret > 0)
341                 transition_latency += ret * 1000;
342
343         ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
344         if (ret) {
345                 dev_err(cpu_dev, "failed register driver: %d\n", ret);
346                 goto free_freq_table;
347         }
348
349         of_node_put(np);
350         return 0;
351
352 free_freq_table:
353         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
354 out_free_opp:
355         if (free_opp)
356                 dev_pm_opp_of_remove_table(cpu_dev);
357 put_reg:
358         if (!IS_ERR(arm_reg))
359                 regulator_put(arm_reg);
360         if (!IS_ERR(pu_reg))
361                 regulator_put(pu_reg);
362         if (!IS_ERR(soc_reg))
363                 regulator_put(soc_reg);
364 put_clk:
365         if (!IS_ERR(arm_clk))
366                 clk_put(arm_clk);
367         if (!IS_ERR(pll1_sys_clk))
368                 clk_put(pll1_sys_clk);
369         if (!IS_ERR(pll1_sw_clk))
370                 clk_put(pll1_sw_clk);
371         if (!IS_ERR(step_clk))
372                 clk_put(step_clk);
373         if (!IS_ERR(pll2_pfd2_396m_clk))
374                 clk_put(pll2_pfd2_396m_clk);
375         if (!IS_ERR(pll2_bus_clk))
376                 clk_put(pll2_bus_clk);
377         if (!IS_ERR(secondary_sel_clk))
378                 clk_put(secondary_sel_clk);
379         of_node_put(np);
380         return ret;
381 }
382
383 static int imx6q_cpufreq_remove(struct platform_device *pdev)
384 {
385         cpufreq_unregister_driver(&imx6q_cpufreq_driver);
386         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
387         if (free_opp)
388                 dev_pm_opp_of_remove_table(cpu_dev);
389         regulator_put(arm_reg);
390         if (!IS_ERR(pu_reg))
391                 regulator_put(pu_reg);
392         regulator_put(soc_reg);
393         clk_put(arm_clk);
394         clk_put(pll1_sys_clk);
395         clk_put(pll1_sw_clk);
396         clk_put(step_clk);
397         clk_put(pll2_pfd2_396m_clk);
398         clk_put(pll2_bus_clk);
399         clk_put(secondary_sel_clk);
400
401         return 0;
402 }
403
404 static struct platform_driver imx6q_cpufreq_platdrv = {
405         .driver = {
406                 .name   = "imx6q-cpufreq",
407         },
408         .probe          = imx6q_cpufreq_probe,
409         .remove         = imx6q_cpufreq_remove,
410 };
411 module_platform_driver(imx6q_cpufreq_platdrv);
412
413 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
414 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
415 MODULE_LICENSE("GPL");