drivers/counter/microchip-tcb-capture.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2020 Microchip
   4  *
   5  * Author: Kamel Bouhara <kamel.bouhara@bootlin.com>
   6  */
   7 #include <linux/clk.h>
   8 #include <linux/counter.h>
   9 #include <linux/mfd/syscon.h>
  10 #include <linux/module.h>
  11 #include <linux/mutex.h>
  12 #include <linux/of.h>
  13 #include <linux/of_device.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/regmap.h>
  16 #include <soc/at91/atmel_tcb.h>
  17
  18 #define ATMEL_TC_CMR_MASK       (ATMEL_TC_LDRA_RISING | ATMEL_TC_LDRB_FALLING | \
  19                                  ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_LDBDIS | \
  20                                  ATMEL_TC_LDBSTOP)
  21
  22 #define ATMEL_TC_QDEN                   BIT(8)
  23 #define ATMEL_TC_POSEN                  BIT(9)
  24
  25 struct mchp_tc_data {
  26         const struct atmel_tcb_config *tc_cfg;
  27         struct regmap *regmap;
  28         int qdec_mode;
  29         int num_channels;
  30         int channel[2];
  31 };
  32
  33 static const enum counter_function mchp_tc_count_functions[] = {
  34         COUNTER_FUNCTION_INCREASE,
  35         COUNTER_FUNCTION_QUADRATURE_X4,
  36 };
  37
  38 static const enum counter_synapse_action mchp_tc_synapse_actions[] = {
  39         COUNTER_SYNAPSE_ACTION_NONE,
  40         COUNTER_SYNAPSE_ACTION_RISING_EDGE,
  41         COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
  42         COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
  43 };
  44
  45 static struct counter_signal mchp_tc_count_signals[] = {
  46         {
  47                 .id = 0,
  48                 .name = "Channel A",
  49         },
  50         {
  51                 .id = 1,
  52                 .name = "Channel B",
  53         }
  54 };
  55
  56 static struct counter_synapse mchp_tc_count_synapses[] = {
  57         {
  58                 .actions_list = mchp_tc_synapse_actions,
  59                 .num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
  60                 .signal = &mchp_tc_count_signals[0]
  61         },
  62         {
  63                 .actions_list = mchp_tc_synapse_actions,
  64                 .num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
  65                 .signal = &mchp_tc_count_signals[1]
  66         }
  67 };
  68
  69 static int mchp_tc_count_function_read(struct counter_device *counter,
  70                                        struct counter_count *count,
  71                                        enum counter_function *function)
  72 {
  73         struct mchp_tc_data *const priv = counter_priv(counter);
  74
  75         if (priv->qdec_mode)
  76                 *function = COUNTER_FUNCTION_QUADRATURE_X4;
  77         else
  78                 *function = COUNTER_FUNCTION_INCREASE;
  79
  80         return 0;
  81 }
  82
  83 static int mchp_tc_count_function_write(struct counter_device *counter,
  84                                         struct counter_count *count,
  85                                         enum counter_function function)
  86 {
  87         struct mchp_tc_data *const priv = counter_priv(counter);
  88         u32 bmr, cmr;
  89
  90         regmap_read(priv->regmap, ATMEL_TC_BMR, &bmr);
  91         regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
  92
  93         /* Set capture mode */
  94         cmr &= ~ATMEL_TC_WAVE;
  95
  96         switch (function) {
  97         case COUNTER_FUNCTION_INCREASE:
  98                 priv->qdec_mode = 0;
  99                 /* Set highest rate based on whether soc has gclk or not */
 100                 bmr &= ~(ATMEL_TC_QDEN | ATMEL_TC_POSEN);
 101                 if (priv->tc_cfg->has_gclk)
 102                         cmr |= ATMEL_TC_TIMER_CLOCK2;
 103                 else
 104                         cmr |= ATMEL_TC_TIMER_CLOCK1;
 105                 /* Setup the period capture mode */
 106                 cmr |=  ATMEL_TC_CMR_MASK;
 107                 cmr &= ~(ATMEL_TC_ABETRG | ATMEL_TC_XC0);
 108                 break;
 109         case COUNTER_FUNCTION_QUADRATURE_X4:
 110                 if (!priv->tc_cfg->has_qdec)
 111                         return -EINVAL;
 112                 /* In QDEC mode settings both channels 0 and 1 are required */
 113                 if (priv->num_channels < 2 || priv->channel[0] != 0 ||
 114                     priv->channel[1] != 1) {
 115                         pr_err("Invalid channels number or id for quadrature mode\n");
 116                         return -EINVAL;
 117                 }
 118                 priv->qdec_mode = 1;
 119                 bmr |= ATMEL_TC_QDEN | ATMEL_TC_POSEN;
 120                 cmr |= ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_ABETRG | ATMEL_TC_XC0;
 121                 break;
 122         default:
 123                 /* should never reach this path */
 124                 return -EINVAL;
 125         }
 126
 127         regmap_write(priv->regmap, ATMEL_TC_BMR, bmr);
 128         regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), cmr);
 129
 130         /* Enable clock and trigger counter */
 131         regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR),
 132                      ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
 133
 134         if (priv->qdec_mode) {
 135                 regmap_write(priv->regmap,
 136                              ATMEL_TC_REG(priv->channel[1], CMR), cmr);
 137                 regmap_write(priv->regmap,
 138                              ATMEL_TC_REG(priv->channel[1], CCR),
 139                              ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
 140         }
 141
 142         return 0;
 143 }
 144
 145 static int mchp_tc_count_signal_read(struct counter_device *counter,
 146                                      struct counter_signal *signal,
 147                                      enum counter_signal_level *lvl)
 148 {
 149         struct mchp_tc_data *const priv = counter_priv(counter);
 150         bool sigstatus;
 151         u32 sr;
 152
 153         regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], SR), &sr);
 154
 155         if (signal->id == 1)
 156                 sigstatus = (sr & ATMEL_TC_MTIOB);
 157         else
 158                 sigstatus = (sr & ATMEL_TC_MTIOA);
 159
 160         *lvl = sigstatus ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW;
 161
 162         return 0;
 163 }
 164
 165 static int mchp_tc_count_action_read(struct counter_device *counter,
 166                                      struct counter_count *count,
 167                                      struct counter_synapse *synapse,
 168                                      enum counter_synapse_action *action)
 169 {
 170         struct mchp_tc_data *const priv = counter_priv(counter);
 171         u32 cmr;
 172
 173         if (priv->qdec_mode) {
 174                 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
 175                 return 0;
 176         }
 177
 178         /* Only TIOA signal is evaluated in non-QDEC mode */
 179         if (synapse->signal->id != 0) {
 180                 *action = COUNTER_SYNAPSE_ACTION_NONE;
 181                 return 0;
 182         }
 183
 184         regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
 185
 186         switch (cmr & ATMEL_TC_ETRGEDG) {
 187         default:
 188                 *action = COUNTER_SYNAPSE_ACTION_NONE;
 189                 break;
 190         case ATMEL_TC_ETRGEDG_RISING:
 191                 *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
 192                 break;
 193         case ATMEL_TC_ETRGEDG_FALLING:
 194                 *action = COUNTER_SYNAPSE_ACTION_FALLING_EDGE;
 195                 break;
 196         case ATMEL_TC_ETRGEDG_BOTH:
 197                 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
 198                 break;
 199         }
 200
 201         return 0;
 202 }
 203
 204 static int mchp_tc_count_action_write(struct counter_device *counter,
 205                                       struct counter_count *count,
 206                                       struct counter_synapse *synapse,
 207                                       enum counter_synapse_action action)
 208 {
 209         struct mchp_tc_data *const priv = counter_priv(counter);
 210         u32 edge = ATMEL_TC_ETRGEDG_NONE;
 211
 212         /* QDEC mode is rising edge only; only TIOA handled in non-QDEC mode */
 213         if (priv->qdec_mode || synapse->signal->id != 0)
 214                 return -EINVAL;
 215
 216         switch (action) {
 217         case COUNTER_SYNAPSE_ACTION_NONE:
 218                 edge = ATMEL_TC_ETRGEDG_NONE;
 219                 break;
 220         case COUNTER_SYNAPSE_ACTION_RISING_EDGE:
 221                 edge = ATMEL_TC_ETRGEDG_RISING;
 222                 break;
 223         case COUNTER_SYNAPSE_ACTION_FALLING_EDGE:
 224                 edge = ATMEL_TC_ETRGEDG_FALLING;
 225                 break;
 226         case COUNTER_SYNAPSE_ACTION_BOTH_EDGES:
 227                 edge = ATMEL_TC_ETRGEDG_BOTH;
 228                 break;
 229         default:
 230                 /* should never reach this path */
 231                 return -EINVAL;
 232         }
 233
 234         return regmap_write_bits(priv->regmap,
 235                                 ATMEL_TC_REG(priv->channel[0], CMR),
 236                                 ATMEL_TC_ETRGEDG, edge);
 237 }
 238
 239 static int mchp_tc_count_read(struct counter_device *counter,
 240                               struct counter_count *count, u64 *val)
 241 {
 242         struct mchp_tc_data *const priv = counter_priv(counter);
 243         u32 cnt;
 244
 245         regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CV), &cnt);
 246         *val = cnt;
 247
 248         return 0;
 249 }
 250
 251 static struct counter_count mchp_tc_counts[] = {
 252         {
 253                 .id = 0,
 254                 .name = "Timer Counter",
 255                 .functions_list = mchp_tc_count_functions,
 256                 .num_functions = ARRAY_SIZE(mchp_tc_count_functions),
 257                 .synapses = mchp_tc_count_synapses,
 258                 .num_synapses = ARRAY_SIZE(mchp_tc_count_synapses),
 259         },
 260 };
 261
 262 static const struct counter_ops mchp_tc_ops = {
 263         .signal_read    = mchp_tc_count_signal_read,
 264         .count_read     = mchp_tc_count_read,
 265         .function_read  = mchp_tc_count_function_read,
 266         .function_write = mchp_tc_count_function_write,
 267         .action_read    = mchp_tc_count_action_read,
 268         .action_write   = mchp_tc_count_action_write
 269 };
 270
 271 static const struct atmel_tcb_config tcb_rm9200_config = {
 272                 .counter_width = 16,
 273 };
 274
 275 static const struct atmel_tcb_config tcb_sam9x5_config = {
 276                 .counter_width = 32,
 277 };
 278
 279 static const struct atmel_tcb_config tcb_sama5d2_config = {
 280                 .counter_width = 32,
 281                 .has_gclk = true,
 282                 .has_qdec = true,
 283 };
 284
 285 static const struct atmel_tcb_config tcb_sama5d3_config = {
 286                 .counter_width = 32,
 287                 .has_qdec = true,
 288 };
 289
 290 static const struct of_device_id atmel_tc_of_match[] = {
 291         { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
 292         { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
 293         { .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
 294         { .compatible = "atmel,sama5d3-tcb", .data = &tcb_sama5d3_config, },
 295         { /* sentinel */ }
 296 };
 297
 298 static void mchp_tc_clk_remove(void *ptr)
 299 {
 300         clk_disable_unprepare((struct clk *)ptr);
 301 }
 302
 303 static int mchp_tc_probe(struct platform_device *pdev)
 304 {
 305         struct device_node *np = pdev->dev.of_node;
 306         const struct atmel_tcb_config *tcb_config;
 307         const struct of_device_id *match;
 308         struct counter_device *counter;
 309         struct mchp_tc_data *priv;
 310         char clk_name[7];
 311         struct regmap *regmap;
 312         struct clk *clk[3];
 313         int channel;
 314         int ret, i;
 315
 316         counter = devm_counter_alloc(&pdev->dev, sizeof(*priv));
 317         if (!counter)
 318                 return -ENOMEM;
 319         priv = counter_priv(counter);
 320
 321         match = of_match_node(atmel_tc_of_match, np->parent);
 322         tcb_config = match->data;
 323         if (!tcb_config) {
 324                 dev_err(&pdev->dev, "No matching parent node found\n");
 325                 return -ENODEV;
 326         }
 327
 328         regmap = syscon_node_to_regmap(np->parent);
 329         if (IS_ERR(regmap))
 330                 return PTR_ERR(regmap);
 331
 332         /* max. channels number is 2 when in QDEC mode */
 333         priv->num_channels = of_property_count_u32_elems(np, "reg");
 334         if (priv->num_channels < 0) {
 335                 dev_err(&pdev->dev, "Invalid or missing channel\n");
 336                 return -EINVAL;
 337         }
 338
 339         /* Register channels and initialize clocks */
 340         for (i = 0; i < priv->num_channels; i++) {
 341                 ret = of_property_read_u32_index(np, "reg", i, &channel);
 342                 if (ret < 0 || channel > 2)
 343                         return -ENODEV;
 344
 345                 priv->channel[i] = channel;
 346
 347                 snprintf(clk_name, sizeof(clk_name), "t%d_clk", channel);
 348
 349                 clk[i] = of_clk_get_by_name(np->parent, clk_name);
 350                 if (IS_ERR(clk[i])) {
 351                         /* Fallback to t0_clk */
 352                         clk[i] = of_clk_get_by_name(np->parent, "t0_clk");
 353                         if (IS_ERR(clk[i]))
 354                                 return PTR_ERR(clk[i]);
 355                 }
 356
 357                 ret = clk_prepare_enable(clk[i]);
 358                 if (ret)
 359                         return ret;
 360
 361                 ret = devm_add_action_or_reset(&pdev->dev,
 362                                                mchp_tc_clk_remove,
 363                                                clk[i]);
 364                 if (ret)
 365                         return ret;
 366
 367                 dev_dbg(&pdev->dev,
 368                         "Initialized capture mode on channel %d\n",
 369                         channel);
 370         }
 371
 372         priv->tc_cfg = tcb_config;
 373         priv->regmap = regmap;
 374         counter->name = dev_name(&pdev->dev);
 375         counter->parent = &pdev->dev;
 376         counter->ops = &mchp_tc_ops;
 377         counter->num_counts = ARRAY_SIZE(mchp_tc_counts);
 378         counter->counts = mchp_tc_counts;
 379         counter->num_signals = ARRAY_SIZE(mchp_tc_count_signals);
 380         counter->signals = mchp_tc_count_signals;
 381
 382         ret = devm_counter_add(&pdev->dev, counter);
 383         if (ret < 0)
 384                 return dev_err_probe(&pdev->dev, ret, "Failed to add counter\n");
 385
 386         return 0;
 387 }
 388
 389 static const struct of_device_id mchp_tc_dt_ids[] = {
 390         { .compatible = "microchip,tcb-capture", },
 391         { /* sentinel */ },
 392 };
 393 MODULE_DEVICE_TABLE(of, mchp_tc_dt_ids);
 394
 395 static struct platform_driver mchp_tc_driver = {
 396         .probe = mchp_tc_probe,
 397         .driver = {
 398                 .name = "microchip-tcb-capture",
 399                 .of_match_table = mchp_tc_dt_ids,
 400         },
 401 };
 402 module_platform_driver(mchp_tc_driver);
 403
 404 MODULE_AUTHOR("Kamel Bouhara <kamel.bouhara@bootlin.com>");
 405 MODULE_DESCRIPTION("Microchip TCB Capture driver");
 406 MODULE_LICENSE("GPL v2");
 407 MODULE_IMPORT_NS(COUNTER);