drivers/clocksource/timer-fttmr010.c

   1 /*
   2  * Faraday Technology FTTMR010 timer driver
   3  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
   4  *
   5  * Based on a rewrite of arch/arm/mach-gemini/timer.c:
   6  * Copyright (C) 2001-2006 Storlink, Corp.
   7  * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
   8  */
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/of.h>
  12 #include <linux/of_address.h>
  13 #include <linux/of_irq.h>
  14 #include <linux/clockchips.h>
  15 #include <linux/clocksource.h>
  16 #include <linux/sched_clock.h>
  17 #include <linux/clk.h>
  18 #include <linux/slab.h>
  19 #include <linux/bitops.h>
  20
  21 /*
  22  * Register definitions for the timers
  23  */
  24 #define TIMER1_COUNT            (0x00)
  25 #define TIMER1_LOAD             (0x04)
  26 #define TIMER1_MATCH1           (0x08)
  27 #define TIMER1_MATCH2           (0x0c)
  28 #define TIMER2_COUNT            (0x10)
  29 #define TIMER2_LOAD             (0x14)
  30 #define TIMER2_MATCH1           (0x18)
  31 #define TIMER2_MATCH2           (0x1c)
  32 #define TIMER3_COUNT            (0x20)
  33 #define TIMER3_LOAD             (0x24)
  34 #define TIMER3_MATCH1           (0x28)
  35 #define TIMER3_MATCH2           (0x2c)
  36 #define TIMER_CR                (0x30)
  37 #define TIMER_INTR_STATE        (0x34)
  38 #define TIMER_INTR_MASK         (0x38)
  39
  40 #define TIMER_1_CR_ENABLE       BIT(0)
  41 #define TIMER_1_CR_CLOCK        BIT(1)
  42 #define TIMER_1_CR_INT          BIT(2)
  43 #define TIMER_2_CR_ENABLE       BIT(3)
  44 #define TIMER_2_CR_CLOCK        BIT(4)
  45 #define TIMER_2_CR_INT          BIT(5)
  46 #define TIMER_3_CR_ENABLE       BIT(6)
  47 #define TIMER_3_CR_CLOCK        BIT(7)
  48 #define TIMER_3_CR_INT          BIT(8)
  49 #define TIMER_1_CR_UPDOWN       BIT(9)
  50 #define TIMER_2_CR_UPDOWN       BIT(10)
  51 #define TIMER_3_CR_UPDOWN       BIT(11)
  52
  53 /*
  54  * The Aspeed AST2400 moves bits around in the control register
  55  * and lacks bits for setting the timer to count upwards.
  56  */
  57 #define TIMER_1_CR_ASPEED_ENABLE        BIT(0)
  58 #define TIMER_1_CR_ASPEED_CLOCK         BIT(1)
  59 #define TIMER_1_CR_ASPEED_INT           BIT(2)
  60 #define TIMER_2_CR_ASPEED_ENABLE        BIT(4)
  61 #define TIMER_2_CR_ASPEED_CLOCK         BIT(5)
  62 #define TIMER_2_CR_ASPEED_INT           BIT(6)
  63 #define TIMER_3_CR_ASPEED_ENABLE        BIT(8)
  64 #define TIMER_3_CR_ASPEED_CLOCK         BIT(9)
  65 #define TIMER_3_CR_ASPEED_INT           BIT(10)
  66
  67 #define TIMER_1_INT_MATCH1      BIT(0)
  68 #define TIMER_1_INT_MATCH2      BIT(1)
  69 #define TIMER_1_INT_OVERFLOW    BIT(2)
  70 #define TIMER_2_INT_MATCH1      BIT(3)
  71 #define TIMER_2_INT_MATCH2      BIT(4)
  72 #define TIMER_2_INT_OVERFLOW    BIT(5)
  73 #define TIMER_3_INT_MATCH1      BIT(6)
  74 #define TIMER_3_INT_MATCH2      BIT(7)
  75 #define TIMER_3_INT_OVERFLOW    BIT(8)
  76 #define TIMER_INT_ALL_MASK      0x1ff
  77
  78 struct fttmr010 {
  79         void __iomem *base;
  80         unsigned int tick_rate;
  81         bool count_down;
  82         u32 t1_enable_val;
  83         struct clock_event_device clkevt;
  84 };
  85
  86 /* A local singleton used by sched_clock, which is stateless */
  87 static struct fttmr010 *local_fttmr;
  88
  89 static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt)
  90 {
  91         return container_of(evt, struct fttmr010, clkevt);
  92 }
  93
  94 static u64 notrace fttmr010_read_sched_clock_up(void)
  95 {
  96         return readl(local_fttmr->base + TIMER2_COUNT);
  97 }
  98
  99 static u64 notrace fttmr010_read_sched_clock_down(void)
 100 {
 101         return ~readl(local_fttmr->base + TIMER2_COUNT);
 102 }
 103
 104 static int fttmr010_timer_set_next_event(unsigned long cycles,
 105                                        struct clock_event_device *evt)
 106 {
 107         struct fttmr010 *fttmr010 = to_fttmr010(evt);
 108         u32 cr;
 109
 110         /* Stop */
 111         cr = readl(fttmr010->base + TIMER_CR);
 112         cr &= ~fttmr010->t1_enable_val;
 113         writel(cr, fttmr010->base + TIMER_CR);
 114
 115         /* Setup the match register forward/backward in time */
 116         cr = readl(fttmr010->base + TIMER1_COUNT);
 117         if (fttmr010->count_down)
 118                 cr -= cycles;
 119         else
 120                 cr += cycles;
 121         writel(cr, fttmr010->base + TIMER1_MATCH1);
 122
 123         /* Start */
 124         cr = readl(fttmr010->base + TIMER_CR);
 125         cr |= fttmr010->t1_enable_val;
 126         writel(cr, fttmr010->base + TIMER_CR);
 127
 128         return 0;
 129 }
 130
 131 static int fttmr010_timer_shutdown(struct clock_event_device *evt)
 132 {
 133         struct fttmr010 *fttmr010 = to_fttmr010(evt);
 134         u32 cr;
 135
 136         /* Stop */
 137         cr = readl(fttmr010->base + TIMER_CR);
 138         cr &= ~fttmr010->t1_enable_val;
 139         writel(cr, fttmr010->base + TIMER_CR);
 140
 141         return 0;
 142 }
 143
 144 static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
 145 {
 146         struct fttmr010 *fttmr010 = to_fttmr010(evt);
 147         u32 cr;
 148
 149         /* Stop */
 150         cr = readl(fttmr010->base + TIMER_CR);
 151         cr &= ~fttmr010->t1_enable_val;
 152         writel(cr, fttmr010->base + TIMER_CR);
 153
 154         /* Setup counter start from 0 or ~0 */
 155         writel(0, fttmr010->base + TIMER1_COUNT);
 156         if (fttmr010->count_down)
 157                 writel(~0, fttmr010->base + TIMER1_LOAD);
 158         else
 159                 writel(0, fttmr010->base + TIMER1_LOAD);
 160
 161         /* Enable interrupt */
 162         cr = readl(fttmr010->base + TIMER_INTR_MASK);
 163         cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
 164         cr |= TIMER_1_INT_MATCH1;
 165         writel(cr, fttmr010->base + TIMER_INTR_MASK);
 166
 167         return 0;
 168 }
 169
 170 static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
 171 {
 172         struct fttmr010 *fttmr010 = to_fttmr010(evt);
 173         u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
 174         u32 cr;
 175
 176         /* Stop */
 177         cr = readl(fttmr010->base + TIMER_CR);
 178         cr &= ~fttmr010->t1_enable_val;
 179         writel(cr, fttmr010->base + TIMER_CR);
 180
 181         /* Setup timer to fire at 1/HZ intervals. */
 182         if (fttmr010->count_down) {
 183                 writel(period, fttmr010->base + TIMER1_LOAD);
 184                 writel(0, fttmr010->base + TIMER1_MATCH1);
 185         } else {
 186                 cr = 0xffffffff - (period - 1);
 187                 writel(cr, fttmr010->base + TIMER1_COUNT);
 188                 writel(cr, fttmr010->base + TIMER1_LOAD);
 189
 190                 /* Enable interrupt on overflow */
 191                 cr = readl(fttmr010->base + TIMER_INTR_MASK);
 192                 cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
 193                 cr |= TIMER_1_INT_OVERFLOW;
 194                 writel(cr, fttmr010->base + TIMER_INTR_MASK);
 195         }
 196
 197         /* Start the timer */
 198         cr = readl(fttmr010->base + TIMER_CR);
 199         cr |= fttmr010->t1_enable_val;
 200         writel(cr, fttmr010->base + TIMER_CR);
 201
 202         return 0;
 203 }
 204
 205 /*
 206  * IRQ handler for the timer
 207  */
 208 static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
 209 {
 210         struct clock_event_device *evt = dev_id;
 211
 212         evt->event_handler(evt);
 213         return IRQ_HANDLED;
 214 }
 215
 216 static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed)
 217 {
 218         struct fttmr010 *fttmr010;
 219         int irq;
 220         struct clk *clk;
 221         int ret;
 222         u32 val;
 223
 224         /*
 225          * These implementations require a clock reference.
 226          * FIXME: we currently only support clocking using PCLK
 227          * and using EXTCLK is not supported in the driver.
 228          */
 229         clk = of_clk_get_by_name(np, "PCLK");
 230         if (IS_ERR(clk)) {
 231                 pr_err("could not get PCLK\n");
 232                 return PTR_ERR(clk);
 233         }
 234         ret = clk_prepare_enable(clk);
 235         if (ret) {
 236                 pr_err("failed to enable PCLK\n");
 237                 return ret;
 238         }
 239
 240         fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
 241         if (!fttmr010) {
 242                 ret = -ENOMEM;
 243                 goto out_disable_clock;
 244         }
 245         fttmr010->tick_rate = clk_get_rate(clk);
 246
 247         fttmr010->base = of_iomap(np, 0);
 248         if (!fttmr010->base) {
 249                 pr_err("Can't remap registers");
 250                 ret = -ENXIO;
 251                 goto out_free;
 252         }
 253         /* IRQ for timer 1 */
 254         irq = irq_of_parse_and_map(np, 0);
 255         if (irq <= 0) {
 256                 pr_err("Can't parse IRQ");
 257                 ret = -EINVAL;
 258                 goto out_unmap;
 259         }
 260
 261         /*
 262          * The Aspeed AST2400 moves bits around in the control register,
 263          * otherwise it works the same.
 264          */
 265         if (is_aspeed) {
 266                 fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE |
 267                         TIMER_1_CR_ASPEED_INT;
 268                 /* Downward not available */
 269                 fttmr010->count_down = true;
 270         } else {
 271                 fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT;
 272         }
 273
 274         /*
 275          * Reset the interrupt mask and status
 276          */
 277         writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
 278         writel(0, fttmr010->base + TIMER_INTR_STATE);
 279
 280         /*
 281          * Enable timer 1 count up, timer 2 count up, except on Aspeed,
 282          * where everything just counts down.
 283          */
 284         if (is_aspeed)
 285                 val = TIMER_2_CR_ASPEED_ENABLE;
 286         else {
 287                 val = TIMER_2_CR_ENABLE;
 288                 if (!fttmr010->count_down)
 289                         val |= TIMER_1_CR_UPDOWN | TIMER_2_CR_UPDOWN;
 290         }
 291         writel(val, fttmr010->base + TIMER_CR);
 292
 293         /*
 294          * Setup free-running clocksource timer (interrupts
 295          * disabled.)
 296          */
 297         local_fttmr = fttmr010;
 298         writel(0, fttmr010->base + TIMER2_COUNT);
 299         writel(0, fttmr010->base + TIMER2_MATCH1);
 300         writel(0, fttmr010->base + TIMER2_MATCH2);
 301
 302         if (fttmr010->count_down) {
 303                 writel(~0, fttmr010->base + TIMER2_LOAD);
 304                 clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
 305                                       "FTTMR010-TIMER2",
 306                                       fttmr010->tick_rate,
 307                                       300, 32, clocksource_mmio_readl_down);
 308                 sched_clock_register(fttmr010_read_sched_clock_down, 32,
 309                                      fttmr010->tick_rate);
 310         } else {
 311                 writel(0, fttmr010->base + TIMER2_LOAD);
 312                 clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
 313                                       "FTTMR010-TIMER2",
 314                                       fttmr010->tick_rate,
 315                                       300, 32, clocksource_mmio_readl_up);
 316                 sched_clock_register(fttmr010_read_sched_clock_up, 32,
 317                                      fttmr010->tick_rate);
 318         }
 319
 320         /*
 321          * Setup clockevent timer (interrupt-driven) on timer 1.
 322          */
 323         writel(0, fttmr010->base + TIMER1_COUNT);
 324         writel(0, fttmr010->base + TIMER1_LOAD);
 325         writel(0, fttmr010->base + TIMER1_MATCH1);
 326         writel(0, fttmr010->base + TIMER1_MATCH2);
 327         ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER,
 328                           "FTTMR010-TIMER1", &fttmr010->clkevt);
 329         if (ret) {
 330                 pr_err("FTTMR010-TIMER1 no IRQ\n");
 331                 goto out_unmap;
 332         }
 333
 334         fttmr010->clkevt.name = "FTTMR010-TIMER1";
 335         /* Reasonably fast and accurate clock event */
 336         fttmr010->clkevt.rating = 300;
 337         fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
 338                 CLOCK_EVT_FEAT_ONESHOT;
 339         fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
 340         fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown;
 341         fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
 342         fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
 343         fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown;
 344         fttmr010->clkevt.cpumask = cpumask_of(0);
 345         fttmr010->clkevt.irq = irq;
 346         clockevents_config_and_register(&fttmr010->clkevt,
 347                                         fttmr010->tick_rate,
 348                                         1, 0xffffffff);
 349
 350         return 0;
 351
 352 out_unmap:
 353         iounmap(fttmr010->base);
 354 out_free:
 355         kfree(fttmr010);
 356 out_disable_clock:
 357         clk_disable_unprepare(clk);
 358
 359         return ret;
 360 }
 361
 362 static __init int aspeed_timer_init(struct device_node *np)
 363 {
 364         return fttmr010_common_init(np, true);
 365 }
 366
 367 static __init int fttmr010_timer_init(struct device_node *np)
 368 {
 369         return fttmr010_common_init(np, false);
 370 }
 371
 372 TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
 373 TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
 374 TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
 375 TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
 376 TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);