drivers/clocksource/timer-fttmr010.c

   1 /*
   2  * Faraday Technology FTTMR010 timer driver
   3  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
   4  *
   5  * Based on a rewrite of arch/arm/mach-gemini/timer.c:
   6  * Copyright (C) 2001-2006 Storlink, Corp.
   7  * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
   8  */
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/of.h>
  12 #include <linux/of_address.h>
  13 #include <linux/of_irq.h>
  14 #include <linux/clockchips.h>
  15 #include <linux/clocksource.h>
  16 #include <linux/sched_clock.h>
  17 #include <linux/clk.h>
  18 #include <linux/slab.h>
  19 #include <linux/bitops.h>
  20 #include <linux/delay.h>
  21
  22 /*
  23  * Register definitions for the timers
  24  */
  25 #define TIMER1_COUNT            (0x00)
  26 #define TIMER1_LOAD             (0x04)
  27 #define TIMER1_MATCH1           (0x08)
  28 #define TIMER1_MATCH2           (0x0c)
  29 #define TIMER2_COUNT            (0x10)
  30 #define TIMER2_LOAD             (0x14)
  31 #define TIMER2_MATCH1           (0x18)
  32 #define TIMER2_MATCH2           (0x1c)
  33 #define TIMER3_COUNT            (0x20)
  34 #define TIMER3_LOAD             (0x24)
  35 #define TIMER3_MATCH1           (0x28)
  36 #define TIMER3_MATCH2           (0x2c)
  37 #define TIMER_CR                (0x30)
  38 #define TIMER_INTR_STATE        (0x34)
  39 #define TIMER_INTR_MASK         (0x38)
  40
  41 #define TIMER_1_CR_ENABLE       BIT(0)
  42 #define TIMER_1_CR_CLOCK        BIT(1)
  43 #define TIMER_1_CR_INT          BIT(2)
  44 #define TIMER_2_CR_ENABLE       BIT(3)
  45 #define TIMER_2_CR_CLOCK        BIT(4)
  46 #define TIMER_2_CR_INT          BIT(5)
  47 #define TIMER_3_CR_ENABLE       BIT(6)
  48 #define TIMER_3_CR_CLOCK        BIT(7)
  49 #define TIMER_3_CR_INT          BIT(8)
  50 #define TIMER_1_CR_UPDOWN       BIT(9)
  51 #define TIMER_2_CR_UPDOWN       BIT(10)
  52 #define TIMER_3_CR_UPDOWN       BIT(11)
  53
  54 /*
  55  * The Aspeed AST2400 moves bits around in the control register
  56  * and lacks bits for setting the timer to count upwards.
  57  */
  58 #define TIMER_1_CR_ASPEED_ENABLE        BIT(0)
  59 #define TIMER_1_CR_ASPEED_CLOCK         BIT(1)
  60 #define TIMER_1_CR_ASPEED_INT           BIT(2)
  61 #define TIMER_2_CR_ASPEED_ENABLE        BIT(4)
  62 #define TIMER_2_CR_ASPEED_CLOCK         BIT(5)
  63 #define TIMER_2_CR_ASPEED_INT           BIT(6)
  64 #define TIMER_3_CR_ASPEED_ENABLE        BIT(8)
  65 #define TIMER_3_CR_ASPEED_CLOCK         BIT(9)
  66 #define TIMER_3_CR_ASPEED_INT           BIT(10)
  67
  68 #define TIMER_1_INT_MATCH1      BIT(0)
  69 #define TIMER_1_INT_MATCH2      BIT(1)
  70 #define TIMER_1_INT_OVERFLOW    BIT(2)
  71 #define TIMER_2_INT_MATCH1      BIT(3)
  72 #define TIMER_2_INT_MATCH2      BIT(4)
  73 #define TIMER_2_INT_OVERFLOW    BIT(5)
  74 #define TIMER_3_INT_MATCH1      BIT(6)
  75 #define TIMER_3_INT_MATCH2      BIT(7)
  76 #define TIMER_3_INT_OVERFLOW    BIT(8)
  77 #define TIMER_INT_ALL_MASK      0x1ff
  78
  79 struct fttmr010 {
  80         void __iomem *base;
  81         unsigned int tick_rate;
  82         bool count_down;
  83         u32 t1_enable_val;
  84         struct clock_event_device clkevt;
  85 #ifdef CONFIG_ARM
  86         struct delay_timer delay_timer;
  87 #endif
  88 };
  89
  90 /*
  91  * A local singleton used by sched_clock and delay timer reads, which are
  92  * fast and stateless
  93  */
  94 static struct fttmr010 *local_fttmr;
  95
  96 static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt)
  97 {
  98         return container_of(evt, struct fttmr010, clkevt);
  99 }
 100
 101 static unsigned long fttmr010_read_current_timer_up(void)
 102 {
 103         return readl(local_fttmr->base + TIMER2_COUNT);
 104 }
 105
 106 static unsigned long fttmr010_read_current_timer_down(void)
 107 {
 108         return ~readl(local_fttmr->base + TIMER2_COUNT);
 109 }
 110
 111 static u64 notrace fttmr010_read_sched_clock_up(void)
 112 {
 113         return fttmr010_read_current_timer_up();
 114 }
 115
 116 static u64 notrace fttmr010_read_sched_clock_down(void)
 117 {
 118         return fttmr010_read_current_timer_down();
 119 }
 120
 121 static int fttmr010_timer_set_next_event(unsigned long cycles,
 122                                        struct clock_event_device *evt)
 123 {
 124         struct fttmr010 *fttmr010 = to_fttmr010(evt);
 125         u32 cr;
 126
 127         /* Stop */
 128         cr = readl(fttmr010->base + TIMER_CR);
 129         cr &= ~fttmr010->t1_enable_val;
 130         writel(cr, fttmr010->base + TIMER_CR);
 131
 132         /* Setup the match register forward/backward in time */
 133         cr = readl(fttmr010->base + TIMER1_COUNT);
 134         if (fttmr010->count_down)
 135                 cr -= cycles;
 136         else
 137                 cr += cycles;
 138         writel(cr, fttmr010->base + TIMER1_MATCH1);
 139
 140         /* Start */
 141         cr = readl(fttmr010->base + TIMER_CR);
 142         cr |= fttmr010->t1_enable_val;
 143         writel(cr, fttmr010->base + TIMER_CR);
 144
 145         return 0;
 146 }
 147
 148 static int fttmr010_timer_shutdown(struct clock_event_device *evt)
 149 {
 150         struct fttmr010 *fttmr010 = to_fttmr010(evt);
 151         u32 cr;
 152
 153         /* Stop */
 154         cr = readl(fttmr010->base + TIMER_CR);
 155         cr &= ~fttmr010->t1_enable_val;
 156         writel(cr, fttmr010->base + TIMER_CR);
 157
 158         return 0;
 159 }
 160
 161 static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
 162 {
 163         struct fttmr010 *fttmr010 = to_fttmr010(evt);
 164         u32 cr;
 165
 166         /* Stop */
 167         cr = readl(fttmr010->base + TIMER_CR);
 168         cr &= ~fttmr010->t1_enable_val;
 169         writel(cr, fttmr010->base + TIMER_CR);
 170
 171         /* Setup counter start from 0 or ~0 */
 172         writel(0, fttmr010->base + TIMER1_COUNT);
 173         if (fttmr010->count_down)
 174                 writel(~0, fttmr010->base + TIMER1_LOAD);
 175         else
 176                 writel(0, fttmr010->base + TIMER1_LOAD);
 177
 178         /* Enable interrupt */
 179         cr = readl(fttmr010->base + TIMER_INTR_MASK);
 180         cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
 181         cr |= TIMER_1_INT_MATCH1;
 182         writel(cr, fttmr010->base + TIMER_INTR_MASK);
 183
 184         return 0;
 185 }
 186
 187 static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
 188 {
 189         struct fttmr010 *fttmr010 = to_fttmr010(evt);
 190         u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
 191         u32 cr;
 192
 193         /* Stop */
 194         cr = readl(fttmr010->base + TIMER_CR);
 195         cr &= ~fttmr010->t1_enable_val;
 196         writel(cr, fttmr010->base + TIMER_CR);
 197
 198         /* Setup timer to fire at 1/HZ intervals. */
 199         if (fttmr010->count_down) {
 200                 writel(period, fttmr010->base + TIMER1_LOAD);
 201                 writel(0, fttmr010->base + TIMER1_MATCH1);
 202         } else {
 203                 cr = 0xffffffff - (period - 1);
 204                 writel(cr, fttmr010->base + TIMER1_COUNT);
 205                 writel(cr, fttmr010->base + TIMER1_LOAD);
 206
 207                 /* Enable interrupt on overflow */
 208                 cr = readl(fttmr010->base + TIMER_INTR_MASK);
 209                 cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
 210                 cr |= TIMER_1_INT_OVERFLOW;
 211                 writel(cr, fttmr010->base + TIMER_INTR_MASK);
 212         }
 213
 214         /* Start the timer */
 215         cr = readl(fttmr010->base + TIMER_CR);
 216         cr |= fttmr010->t1_enable_val;
 217         writel(cr, fttmr010->base + TIMER_CR);
 218
 219         return 0;
 220 }
 221
 222 /*
 223  * IRQ handler for the timer
 224  */
 225 static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
 226 {
 227         struct clock_event_device *evt = dev_id;
 228
 229         evt->event_handler(evt);
 230         return IRQ_HANDLED;
 231 }
 232
 233 static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed)
 234 {
 235         struct fttmr010 *fttmr010;
 236         int irq;
 237         struct clk *clk;
 238         int ret;
 239         u32 val;
 240
 241         /*
 242          * These implementations require a clock reference.
 243          * FIXME: we currently only support clocking using PCLK
 244          * and using EXTCLK is not supported in the driver.
 245          */
 246         clk = of_clk_get_by_name(np, "PCLK");
 247         if (IS_ERR(clk)) {
 248                 pr_err("could not get PCLK\n");
 249                 return PTR_ERR(clk);
 250         }
 251         ret = clk_prepare_enable(clk);
 252         if (ret) {
 253                 pr_err("failed to enable PCLK\n");
 254                 return ret;
 255         }
 256
 257         fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
 258         if (!fttmr010) {
 259                 ret = -ENOMEM;
 260                 goto out_disable_clock;
 261         }
 262         fttmr010->tick_rate = clk_get_rate(clk);
 263
 264         fttmr010->base = of_iomap(np, 0);
 265         if (!fttmr010->base) {
 266                 pr_err("Can't remap registers");
 267                 ret = -ENXIO;
 268                 goto out_free;
 269         }
 270         /* IRQ for timer 1 */
 271         irq = irq_of_parse_and_map(np, 0);
 272         if (irq <= 0) {
 273                 pr_err("Can't parse IRQ");
 274                 ret = -EINVAL;
 275                 goto out_unmap;
 276         }
 277
 278         /*
 279          * The Aspeed AST2400 moves bits around in the control register,
 280          * otherwise it works the same.
 281          */
 282         if (is_aspeed) {
 283                 fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE |
 284                         TIMER_1_CR_ASPEED_INT;
 285                 /* Downward not available */
 286                 fttmr010->count_down = true;
 287         } else {
 288                 fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT;
 289         }
 290
 291         /*
 292          * Reset the interrupt mask and status
 293          */
 294         writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
 295         writel(0, fttmr010->base + TIMER_INTR_STATE);
 296
 297         /*
 298          * Enable timer 1 count up, timer 2 count up, except on Aspeed,
 299          * where everything just counts down.
 300          */
 301         if (is_aspeed)
 302                 val = TIMER_2_CR_ASPEED_ENABLE;
 303         else {
 304                 val = TIMER_2_CR_ENABLE;
 305                 if (!fttmr010->count_down)
 306                         val |= TIMER_1_CR_UPDOWN | TIMER_2_CR_UPDOWN;
 307         }
 308         writel(val, fttmr010->base + TIMER_CR);
 309
 310         /*
 311          * Setup free-running clocksource timer (interrupts
 312          * disabled.)
 313          */
 314         local_fttmr = fttmr010;
 315         writel(0, fttmr010->base + TIMER2_COUNT);
 316         writel(0, fttmr010->base + TIMER2_MATCH1);
 317         writel(0, fttmr010->base + TIMER2_MATCH2);
 318
 319         if (fttmr010->count_down) {
 320                 writel(~0, fttmr010->base + TIMER2_LOAD);
 321                 clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
 322                                       "FTTMR010-TIMER2",
 323                                       fttmr010->tick_rate,
 324                                       300, 32, clocksource_mmio_readl_down);
 325                 sched_clock_register(fttmr010_read_sched_clock_down, 32,
 326                                      fttmr010->tick_rate);
 327         } else {
 328                 writel(0, fttmr010->base + TIMER2_LOAD);
 329                 clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
 330                                       "FTTMR010-TIMER2",
 331                                       fttmr010->tick_rate,
 332                                       300, 32, clocksource_mmio_readl_up);
 333                 sched_clock_register(fttmr010_read_sched_clock_up, 32,
 334                                      fttmr010->tick_rate);
 335         }
 336
 337         /*
 338          * Setup clockevent timer (interrupt-driven) on timer 1.
 339          */
 340         writel(0, fttmr010->base + TIMER1_COUNT);
 341         writel(0, fttmr010->base + TIMER1_LOAD);
 342         writel(0, fttmr010->base + TIMER1_MATCH1);
 343         writel(0, fttmr010->base + TIMER1_MATCH2);
 344         ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER,
 345                           "FTTMR010-TIMER1", &fttmr010->clkevt);
 346         if (ret) {
 347                 pr_err("FTTMR010-TIMER1 no IRQ\n");
 348                 goto out_unmap;
 349         }
 350
 351         fttmr010->clkevt.name = "FTTMR010-TIMER1";
 352         /* Reasonably fast and accurate clock event */
 353         fttmr010->clkevt.rating = 300;
 354         fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
 355                 CLOCK_EVT_FEAT_ONESHOT;
 356         fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
 357         fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown;
 358         fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
 359         fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
 360         fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown;
 361         fttmr010->clkevt.cpumask = cpumask_of(0);
 362         fttmr010->clkevt.irq = irq;
 363         clockevents_config_and_register(&fttmr010->clkevt,
 364                                         fttmr010->tick_rate,
 365                                         1, 0xffffffff);
 366
 367 #ifdef CONFIG_ARM
 368         /* Also use this timer for delays */
 369         if (fttmr010->count_down)
 370                 fttmr010->delay_timer.read_current_timer =
 371                         fttmr010_read_current_timer_down;
 372         else
 373                 fttmr010->delay_timer.read_current_timer =
 374                         fttmr010_read_current_timer_up;
 375         fttmr010->delay_timer.freq = fttmr010->tick_rate;
 376         register_current_timer_delay(&fttmr010->delay_timer);
 377 #endif
 378
 379         return 0;
 380
 381 out_unmap:
 382         iounmap(fttmr010->base);
 383 out_free:
 384         kfree(fttmr010);
 385 out_disable_clock:
 386         clk_disable_unprepare(clk);
 387
 388         return ret;
 389 }
 390
 391 static __init int aspeed_timer_init(struct device_node *np)
 392 {
 393         return fttmr010_common_init(np, true);
 394 }
 395
 396 static __init int fttmr010_timer_init(struct device_node *np)
 397 {
 398         return fttmr010_common_init(np, false);
 399 }
 400
 401 TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
 402 TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
 403 TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
 404 TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
 405 TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);