drivers/clocksource/sh_mtu2.c

   1 /*
   2  * SuperH Timer Support - MTU2
   3  *
   4  *  Copyright (C) 2009 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/delay.h>
  26 #include <linux/io.h>
  27 #include <linux/clk.h>
  28 #include <linux/irq.h>
  29 #include <linux/err.h>
  30 #include <linux/clockchips.h>
  31 #include <linux/sh_timer.h>
  32 #include <linux/slab.h>
  33 #include <linux/module.h>
  34 #include <linux/pm_domain.h>
  35
  36 struct sh_mtu2_priv {
  37         void __iomem *mapbase;
  38         struct clk *clk;
  39         struct irqaction irqaction;
  40         struct platform_device *pdev;
  41         unsigned long rate;
  42         unsigned long periodic;
  43         struct clock_event_device ced;
  44 };
  45
  46 static DEFINE_RAW_SPINLOCK(sh_mtu2_lock);
  47
  48 #define TSTR -1 /* shared register */
  49 #define TCR  0 /* channel register */
  50 #define TMDR 1 /* channel register */
  51 #define TIOR 2 /* channel register */
  52 #define TIER 3 /* channel register */
  53 #define TSR  4 /* channel register */
  54 #define TCNT 5 /* channel register */
  55 #define TGR  6 /* channel register */
  56
  57 static unsigned long mtu2_reg_offs[] = {
  58         [TCR] = 0,
  59         [TMDR] = 1,
  60         [TIOR] = 2,
  61         [TIER] = 4,
  62         [TSR] = 5,
  63         [TCNT] = 6,
  64         [TGR] = 8,
  65 };
  66
  67 static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr)
  68 {
  69         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
  70         void __iomem *base = p->mapbase;
  71         unsigned long offs;
  72
  73         if (reg_nr == TSTR)
  74                 return ioread8(base + cfg->channel_offset);
  75
  76         offs = mtu2_reg_offs[reg_nr];
  77
  78         if ((reg_nr == TCNT) || (reg_nr == TGR))
  79                 return ioread16(base + offs);
  80         else
  81                 return ioread8(base + offs);
  82 }
  83
  84 static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr,
  85                                 unsigned long value)
  86 {
  87         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
  88         void __iomem *base = p->mapbase;
  89         unsigned long offs;
  90
  91         if (reg_nr == TSTR) {
  92                 iowrite8(value, base + cfg->channel_offset);
  93                 return;
  94         }
  95
  96         offs = mtu2_reg_offs[reg_nr];
  97
  98         if ((reg_nr == TCNT) || (reg_nr == TGR))
  99                 iowrite16(value, base + offs);
 100         else
 101                 iowrite8(value, base + offs);
 102 }
 103
 104 static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
 105 {
 106         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
 107         unsigned long flags, value;
 108
 109         /* start stop register shared by multiple timer channels */
 110         raw_spin_lock_irqsave(&sh_mtu2_lock, flags);
 111         value = sh_mtu2_read(p, TSTR);
 112
 113         if (start)
 114                 value |= 1 << cfg->timer_bit;
 115         else
 116                 value &= ~(1 << cfg->timer_bit);
 117
 118         sh_mtu2_write(p, TSTR, value);
 119         raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags);
 120 }
 121
 122 static int sh_mtu2_enable(struct sh_mtu2_priv *p)
 123 {
 124         int ret;
 125
 126         /* enable clock */
 127         ret = clk_enable(p->clk);
 128         if (ret) {
 129                 dev_err(&p->pdev->dev, "cannot enable clock\n");
 130                 return ret;
 131         }
 132
 133         /* make sure channel is disabled */
 134         sh_mtu2_start_stop_ch(p, 0);
 135
 136         p->rate = clk_get_rate(p->clk) / 64;
 137         p->periodic = (p->rate + HZ/2) / HZ;
 138
 139         /* "Periodic Counter Operation" */
 140         sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */
 141         sh_mtu2_write(p, TIOR, 0);
 142         sh_mtu2_write(p, TGR, p->periodic);
 143         sh_mtu2_write(p, TCNT, 0);
 144         sh_mtu2_write(p, TMDR, 0);
 145         sh_mtu2_write(p, TIER, 0x01);
 146
 147         /* enable channel */
 148         sh_mtu2_start_stop_ch(p, 1);
 149
 150         return 0;
 151 }
 152
 153 static void sh_mtu2_disable(struct sh_mtu2_priv *p)
 154 {
 155         /* disable channel */
 156         sh_mtu2_start_stop_ch(p, 0);
 157
 158         /* stop clock */
 159         clk_disable(p->clk);
 160 }
 161
 162 static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
 163 {
 164         struct sh_mtu2_priv *p = dev_id;
 165
 166         /* acknowledge interrupt */
 167         sh_mtu2_read(p, TSR);
 168         sh_mtu2_write(p, TSR, 0xfe);
 169
 170         /* notify clockevent layer */
 171         p->ced.event_handler(&p->ced);
 172         return IRQ_HANDLED;
 173 }
 174
 175 static struct sh_mtu2_priv *ced_to_sh_mtu2(struct clock_event_device *ced)
 176 {
 177         return container_of(ced, struct sh_mtu2_priv, ced);
 178 }
 179
 180 static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
 181                                     struct clock_event_device *ced)
 182 {
 183         struct sh_mtu2_priv *p = ced_to_sh_mtu2(ced);
 184         int disabled = 0;
 185
 186         /* deal with old setting first */
 187         switch (ced->mode) {
 188         case CLOCK_EVT_MODE_PERIODIC:
 189                 sh_mtu2_disable(p);
 190                 disabled = 1;
 191                 break;
 192         default:
 193                 break;
 194         }
 195
 196         switch (mode) {
 197         case CLOCK_EVT_MODE_PERIODIC:
 198                 dev_info(&p->pdev->dev, "used for periodic clock events\n");
 199                 sh_mtu2_enable(p);
 200                 break;
 201         case CLOCK_EVT_MODE_UNUSED:
 202                 if (!disabled)
 203                         sh_mtu2_disable(p);
 204                 break;
 205         case CLOCK_EVT_MODE_SHUTDOWN:
 206         default:
 207                 break;
 208         }
 209 }
 210
 211 static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced)
 212 {
 213         pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->pdev->dev);
 214 }
 215
 216 static void sh_mtu2_clock_event_resume(struct clock_event_device *ced)
 217 {
 218         pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->pdev->dev);
 219 }
 220
 221 static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
 222                                        char *name, unsigned long rating)
 223 {
 224         struct clock_event_device *ced = &p->ced;
 225         int ret;
 226
 227         memset(ced, 0, sizeof(*ced));
 228
 229         ced->name = name;
 230         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 231         ced->rating = rating;
 232         ced->cpumask = cpumask_of(0);
 233         ced->set_mode = sh_mtu2_clock_event_mode;
 234         ced->suspend = sh_mtu2_clock_event_suspend;
 235         ced->resume = sh_mtu2_clock_event_resume;
 236
 237         dev_info(&p->pdev->dev, "used for clock events\n");
 238         clockevents_register_device(ced);
 239
 240         ret = setup_irq(p->irqaction.irq, &p->irqaction);
 241         if (ret) {
 242                 dev_err(&p->pdev->dev, "failed to request irq %d\n",
 243                         p->irqaction.irq);
 244                 return;
 245         }
 246 }
 247
 248 static int sh_mtu2_register(struct sh_mtu2_priv *p, char *name,
 249                             unsigned long clockevent_rating)
 250 {
 251         if (clockevent_rating)
 252                 sh_mtu2_register_clockevent(p, name, clockevent_rating);
 253
 254         return 0;
 255 }
 256
 257 static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
 258 {
 259         struct sh_timer_config *cfg = pdev->dev.platform_data;
 260         struct resource *res;
 261         int irq, ret;
 262         ret = -ENXIO;
 263
 264         memset(p, 0, sizeof(*p));
 265         p->pdev = pdev;
 266
 267         if (!cfg) {
 268                 dev_err(&p->pdev->dev, "missing platform data\n");
 269                 goto err0;
 270         }
 271
 272         platform_set_drvdata(pdev, p);
 273
 274         res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
 275         if (!res) {
 276                 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
 277                 goto err0;
 278         }
 279
 280         irq = platform_get_irq(p->pdev, 0);
 281         if (irq < 0) {
 282                 dev_err(&p->pdev->dev, "failed to get irq\n");
 283                 goto err0;
 284         }
 285
 286         /* map memory, let mapbase point to our channel */
 287         p->mapbase = ioremap_nocache(res->start, resource_size(res));
 288         if (p->mapbase == NULL) {
 289                 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
 290                 goto err0;
 291         }
 292
 293         /* setup data for setup_irq() (too early for request_irq()) */
 294         p->irqaction.name = dev_name(&p->pdev->dev);
 295         p->irqaction.handler = sh_mtu2_interrupt;
 296         p->irqaction.dev_id = p;
 297         p->irqaction.irq = irq;
 298         p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
 299                              IRQF_IRQPOLL  | IRQF_NOBALANCING;
 300
 301         /* get hold of clock */
 302         p->clk = clk_get(&p->pdev->dev, "mtu2_fck");
 303         if (IS_ERR(p->clk)) {
 304                 dev_err(&p->pdev->dev, "cannot get clock\n");
 305                 ret = PTR_ERR(p->clk);
 306                 goto err1;
 307         }
 308
 309         return sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev),
 310                                 cfg->clockevent_rating);
 311  err1:
 312         iounmap(p->mapbase);
 313  err0:
 314         return ret;
 315 }
 316
 317 static int __devinit sh_mtu2_probe(struct platform_device *pdev)
 318 {
 319         struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
 320         int ret;
 321
 322         if (!is_early_platform_device(pdev)) {
 323                 struct sh_timer_config *cfg = pdev->dev.platform_data;
 324
 325                 if (cfg->clockevent_rating)
 326                         dev_pm_syscore_device(&pdev->dev, true);
 327         }
 328
 329         if (p) {
 330                 dev_info(&pdev->dev, "kept as earlytimer\n");
 331                 return 0;
 332         }
 333
 334         p = kmalloc(sizeof(*p), GFP_KERNEL);
 335         if (p == NULL) {
 336                 dev_err(&pdev->dev, "failed to allocate driver data\n");
 337                 return -ENOMEM;
 338         }
 339
 340         ret = sh_mtu2_setup(p, pdev);
 341         if (ret) {
 342                 kfree(p);
 343                 platform_set_drvdata(pdev, NULL);
 344         }
 345         return ret;
 346 }
 347
 348 static int __devexit sh_mtu2_remove(struct platform_device *pdev)
 349 {
 350         return -EBUSY; /* cannot unregister clockevent */
 351 }
 352
 353 static struct platform_driver sh_mtu2_device_driver = {
 354         .probe          = sh_mtu2_probe,
 355         .remove         = __devexit_p(sh_mtu2_remove),
 356         .driver         = {
 357                 .name   = "sh_mtu2",
 358         }
 359 };
 360
 361 static int __init sh_mtu2_init(void)
 362 {
 363         return platform_driver_register(&sh_mtu2_device_driver);
 364 }
 365
 366 static void __exit sh_mtu2_exit(void)
 367 {
 368         platform_driver_unregister(&sh_mtu2_device_driver);
 369 }
 370
 371 early_platform_init("earlytimer", &sh_mtu2_device_driver);
 372 module_init(sh_mtu2_init);
 373 module_exit(sh_mtu2_exit);
 374
 375 MODULE_AUTHOR("Magnus Damm");
 376 MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
 377 MODULE_LICENSE("GPL v2");