2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 #include <linux/clockchips.h>
10 #include <linux/cpu.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/notifier.h>
14 #include <linux/of_irq.h>
15 #include <linux/percpu.h>
16 #include <linux/smp.h>
17 #include <linux/time.h>
18 #include <asm/mips-cps.h>
20 static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
21 static int gic_timer_irq;
22 static unsigned int gic_frequency;
24 static u64 notrace gic_read_count(void)
26 unsigned int hi, hi2, lo;
29 return read_gic_counter();
32 hi = read_gic_counter_32h();
33 lo = read_gic_counter_32l();
34 hi2 = read_gic_counter_32h();
37 return (((u64) hi) << 32) + lo;
40 static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
42 int cpu = cpumask_first(evt->cpumask);
46 cnt = gic_read_count();
48 if (cpu == raw_smp_processor_id()) {
49 write_gic_vl_compare(cnt);
51 write_gic_vl_other(mips_cm_vp_id(cpu));
52 write_gic_vo_compare(cnt);
54 res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
58 static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
60 struct clock_event_device *cd = dev_id;
62 write_gic_vl_compare(read_gic_vl_compare());
63 cd->event_handler(cd);
67 struct irqaction gic_compare_irqaction = {
68 .handler = gic_compare_interrupt,
69 .percpu_dev_id = &gic_clockevent_device,
70 .flags = IRQF_PERCPU | IRQF_TIMER,
74 static void gic_clockevent_cpu_init(unsigned int cpu,
75 struct clock_event_device *cd)
77 cd->name = "MIPS GIC";
78 cd->features = CLOCK_EVT_FEAT_ONESHOT |
79 CLOCK_EVT_FEAT_C3STOP;
82 cd->irq = gic_timer_irq;
83 cd->cpumask = cpumask_of(cpu);
84 cd->set_next_event = gic_next_event;
86 clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff);
88 enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE);
91 static void gic_clockevent_cpu_exit(struct clock_event_device *cd)
93 disable_percpu_irq(gic_timer_irq);
96 static void gic_update_frequency(void *data)
98 unsigned long rate = (unsigned long)data;
100 clockevents_update_freq(this_cpu_ptr(&gic_clockevent_device), rate);
103 static int gic_starting_cpu(unsigned int cpu)
105 gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device));
109 static int gic_clk_notifier(struct notifier_block *nb, unsigned long action,
112 struct clk_notifier_data *cnd = data;
114 if (action == POST_RATE_CHANGE)
115 on_each_cpu(gic_update_frequency, (void *)cnd->new_rate, 1);
120 static int gic_dying_cpu(unsigned int cpu)
122 gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device));
126 static struct notifier_block gic_clk_nb = {
127 .notifier_call = gic_clk_notifier,
130 static int gic_clockevent_init(void)
137 ret = setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
139 pr_err("GIC timer IRQ %d setup failed: %d\n",
144 cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING,
145 "clockevents/mips/gic/timer:starting",
146 gic_starting_cpu, gic_dying_cpu);
150 static u64 gic_hpt_read(struct clocksource *cs)
152 return gic_read_count();
155 static struct clocksource gic_clocksource = {
157 .read = gic_hpt_read,
158 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
159 .archdata = { .vdso_clock_mode = VDSO_CLOCK_GIC },
162 static int __init __gic_clocksource_init(void)
164 unsigned int count_width;
167 /* Set clocksource mask. */
168 count_width = read_gic_config() & GIC_CONFIG_COUNTBITS;
169 count_width >>= __ffs(GIC_CONFIG_COUNTBITS);
172 gic_clocksource.mask = CLOCKSOURCE_MASK(count_width);
174 /* Calculate a somewhat reasonable rating value. */
175 gic_clocksource.rating = 200 + gic_frequency / 10000000;
177 ret = clocksource_register_hz(&gic_clocksource, gic_frequency);
179 pr_warn("GIC: Unable to register clocksource\n");
184 static int __init gic_clocksource_of_init(struct device_node *node)
189 if (!mips_gic_present() || !node->parent ||
190 !of_device_is_compatible(node->parent, "mti,gic")) {
191 pr_warn("No DT definition for the mips gic driver\n");
195 clk = of_clk_get(node, 0);
197 ret = clk_prepare_enable(clk);
199 pr_err("GIC failed to enable clock\n");
204 gic_frequency = clk_get_rate(clk);
205 } else if (of_property_read_u32(node, "clock-frequency",
207 pr_err("GIC frequency not specified.\n");
210 gic_timer_irq = irq_of_parse_and_map(node, 0);
211 if (!gic_timer_irq) {
212 pr_err("GIC timer IRQ not specified.\n");
216 ret = __gic_clocksource_init();
220 ret = gic_clockevent_init();
221 if (!ret && !IS_ERR(clk)) {
222 if (clk_notifier_register(clk, &gic_clk_nb) < 0)
223 pr_warn("GIC: Unable to register clock notifier\n");
226 /* And finally start the counter */
227 clear_gic_config(GIC_CONFIG_COUNTSTOP);
231 TIMER_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
232 gic_clocksource_of_init);