2 * Copyright (C) 2012 Altera Corporation
3 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
5 * Modified from mach-picoxcell/time.c
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/delay.h>
20 #include <linux/dw_apb_timer.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
24 #include <linux/clk.h>
25 #include <linux/reset.h>
26 #include <linux/sched_clock.h>
28 static void __init timer_get_base_and_rate(struct device_node *np,
29 void __iomem **base, u32 *rate)
31 struct clk *timer_clk;
33 struct reset_control *rstc;
35 *base = of_iomap(np, 0);
38 panic("Unable to map regs for %pOFn", np);
41 * Reset the timer if the reset control is available, wiping
42 * out the state the firmware may have left it
44 rstc = of_reset_control_get(np, NULL);
46 reset_control_assert(rstc);
47 reset_control_deassert(rstc);
51 * Not all implementations use a periphal clock, so don't panic
54 pclk = of_clk_get_by_name(np, "pclk");
56 if (clk_prepare_enable(pclk))
57 pr_warn("pclk for %pOFn is present, but could not be activated\n",
60 timer_clk = of_clk_get_by_name(np, "timer");
61 if (IS_ERR(timer_clk))
64 if (!clk_prepare_enable(timer_clk)) {
65 *rate = clk_get_rate(timer_clk);
70 if (of_property_read_u32(np, "clock-freq", rate) &&
71 of_property_read_u32(np, "clock-frequency", rate))
72 panic("No clock nor clock-frequency property for %pOFn", np);
75 static void __init add_clockevent(struct device_node *event_timer)
78 struct dw_apb_clock_event_device *ced;
81 irq = irq_of_parse_and_map(event_timer, 0);
83 panic("No IRQ for clock event timer");
85 timer_get_base_and_rate(event_timer, &iobase, &rate);
87 ced = dw_apb_clockevent_init(0, event_timer->name, 300, iobase, irq,
90 panic("Unable to initialise clockevent device");
92 dw_apb_clockevent_register(ced);
95 static void __iomem *sched_io_base;
96 static u32 sched_rate;
98 static void __init add_clocksource(struct device_node *source_timer)
100 void __iomem *iobase;
101 struct dw_apb_clocksource *cs;
104 timer_get_base_and_rate(source_timer, &iobase, &rate);
106 cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate);
108 panic("Unable to initialise clocksource device");
110 dw_apb_clocksource_start(cs);
111 dw_apb_clocksource_register(cs);
114 * Fallback to use the clocksource as sched_clock if no separate
115 * timer is found. sched_io_base then points to the current_value
116 * register of the clocksource timer.
118 sched_io_base = iobase + 0x04;
122 static u64 notrace read_sched_clock(void)
124 return ~readl_relaxed(sched_io_base);
127 static const struct of_device_id sptimer_ids[] __initconst = {
128 { .compatible = "picochip,pc3x2-rtc" },
132 static void __init init_sched_clock(void)
134 struct device_node *sched_timer;
136 sched_timer = of_find_matching_node(NULL, sptimer_ids);
138 timer_get_base_and_rate(sched_timer, &sched_io_base,
140 of_node_put(sched_timer);
143 sched_clock_register(read_sched_clock, 32, sched_rate);
147 static unsigned long dw_apb_delay_timer_read(void)
149 return ~readl_relaxed(sched_io_base);
152 static struct delay_timer dw_apb_delay_timer = {
153 .read_current_timer = dw_apb_delay_timer_read,
157 static int num_called;
158 static int __init dw_apb_timer_init(struct device_node *timer)
160 switch (num_called) {
162 pr_debug("%s: found clockevent timer\n", __func__);
163 add_clockevent(timer);
166 pr_debug("%s: found clocksource timer\n", __func__);
167 add_clocksource(timer);
170 dw_apb_delay_timer.freq = sched_rate;
171 register_current_timer_delay(&dw_apb_delay_timer);
182 TIMER_OF_DECLARE(pc3x2_timer, "picochip,pc3x2-timer", dw_apb_timer_init);
183 TIMER_OF_DECLARE(apb_timer_osc, "snps,dw-apb-timer-osc", dw_apb_timer_init);
184 TIMER_OF_DECLARE(apb_timer_sp, "snps,dw-apb-timer-sp", dw_apb_timer_init);
185 TIMER_OF_DECLARE(apb_timer, "snps,dw-apb-timer", dw_apb_timer_init);