2 * drivers/clocksource/arm_global_timer.c
4 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
5 * Author: Stuart Menefy <stuart.menefy@st.com>
6 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/clocksource.h>
16 #include <linux/clockchips.h>
17 #include <linux/cpu.h>
18 #include <linux/clk.h>
19 #include <linux/err.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
24 #include <linux/sched_clock.h>
26 #include <asm/cputype.h>
28 #define GT_COUNTER0 0x00
29 #define GT_COUNTER1 0x04
31 #define GT_CONTROL 0x08
32 #define GT_CONTROL_TIMER_ENABLE BIT(0) /* this bit is NOT banked */
33 #define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */
34 #define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */
35 #define GT_CONTROL_AUTO_INC BIT(3) /* banked */
37 #define GT_INT_STATUS 0x0c
38 #define GT_INT_STATUS_EVENT_FLAG BIT(0)
42 #define GT_AUTO_INC 0x18
45 * We are expecting to be clocked by the ARM peripheral clock.
47 * Note: it is assumed we are using a prescaler value of zero, so this is
48 * the units for all operations.
50 static void __iomem *gt_base;
51 static unsigned long gt_clk_rate;
53 static struct clock_event_device __percpu *gt_evt;
56 * To get the value from the Global Timer Counter register proceed as follows:
57 * 1. Read the upper 32-bit timer counter register
58 * 2. Read the lower 32-bit timer counter register
59 * 3. Read the upper 32-bit timer counter register again. If the value is
60 * different to the 32-bit upper value read previously, go back to step 2.
61 * Otherwise the 64-bit timer counter value is correct.
63 static u64 notrace _gt_counter_read(void)
69 upper = readl_relaxed(gt_base + GT_COUNTER1);
72 lower = readl_relaxed(gt_base + GT_COUNTER0);
73 upper = readl_relaxed(gt_base + GT_COUNTER1);
74 } while (upper != old_upper);
82 static u64 gt_counter_read(void)
84 return _gt_counter_read();
88 * To ensure that updates to comparator value register do not set the
89 * Interrupt Status Register proceed as follows:
90 * 1. Clear the Comp Enable bit in the Timer Control Register.
91 * 2. Write the lower 32-bit Comparator Value Register.
92 * 3. Write the upper 32-bit Comparator Value Register.
93 * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.
95 static void gt_compare_set(unsigned long delta, int periodic)
97 u64 counter = gt_counter_read();
101 ctrl = GT_CONTROL_TIMER_ENABLE;
102 writel_relaxed(ctrl, gt_base + GT_CONTROL);
103 writel_relaxed(lower_32_bits(counter), gt_base + GT_COMP0);
104 writel_relaxed(upper_32_bits(counter), gt_base + GT_COMP1);
107 writel_relaxed(delta, gt_base + GT_AUTO_INC);
108 ctrl |= GT_CONTROL_AUTO_INC;
111 ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
112 writel_relaxed(ctrl, gt_base + GT_CONTROL);
115 static int gt_clockevent_shutdown(struct clock_event_device *evt)
119 ctrl = readl(gt_base + GT_CONTROL);
120 ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE |
121 GT_CONTROL_AUTO_INC);
122 writel(ctrl, gt_base + GT_CONTROL);
126 static int gt_clockevent_set_periodic(struct clock_event_device *evt)
128 gt_compare_set(DIV_ROUND_CLOSEST(gt_clk_rate, HZ), 1);
132 static int gt_clockevent_set_next_event(unsigned long evt,
133 struct clock_event_device *unused)
135 gt_compare_set(evt, 0);
139 static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
141 struct clock_event_device *evt = dev_id;
143 if (!(readl_relaxed(gt_base + GT_INT_STATUS) &
144 GT_INT_STATUS_EVENT_FLAG))
148 * ERRATA 740657( Global Timer can send 2 interrupts for
149 * the same event in single-shot mode)
151 * Either disable single-shot mode.
153 * Modify the Interrupt Handler to avoid the
154 * offending sequence. This is achieved by clearing
155 * the Global Timer flag _after_ having incremented
156 * the Comparator register value to a higher value.
158 if (clockevent_state_oneshot(evt))
159 gt_compare_set(ULONG_MAX, 0);
161 writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
162 evt->event_handler(evt);
167 static int gt_clockevents_init(struct clock_event_device *clk)
169 int cpu = smp_processor_id();
171 clk->name = "arm_global_timer";
172 clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
173 CLOCK_EVT_FEAT_PERCPU;
174 clk->set_state_shutdown = gt_clockevent_shutdown;
175 clk->set_state_periodic = gt_clockevent_set_periodic;
176 clk->set_state_oneshot = gt_clockevent_shutdown;
177 clk->set_next_event = gt_clockevent_set_next_event;
178 clk->cpumask = cpumask_of(cpu);
181 clockevents_config_and_register(clk, gt_clk_rate,
183 enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
187 static void gt_clockevents_stop(struct clock_event_device *clk)
189 gt_clockevent_shutdown(clk);
190 disable_percpu_irq(clk->irq);
193 static cycle_t gt_clocksource_read(struct clocksource *cs)
195 return gt_counter_read();
198 static void gt_resume(struct clocksource *cs)
202 ctrl = readl(gt_base + GT_CONTROL);
203 if (!(ctrl & GT_CONTROL_TIMER_ENABLE))
204 /* re-enable timer on resume */
205 writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
208 static struct clocksource gt_clocksource = {
209 .name = "arm_global_timer",
211 .read = gt_clocksource_read,
212 .mask = CLOCKSOURCE_MASK(64),
213 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
217 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
218 static u64 notrace gt_sched_clock_read(void)
220 return _gt_counter_read();
224 static void __init gt_clocksource_init(void)
226 writel(0, gt_base + GT_CONTROL);
227 writel(0, gt_base + GT_COUNTER0);
228 writel(0, gt_base + GT_COUNTER1);
229 /* enables timer on all the cores */
230 writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
232 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
233 sched_clock_register(gt_sched_clock_read, 64, gt_clk_rate);
235 clocksource_register_hz(>_clocksource, gt_clk_rate);
238 static int gt_cpu_notify(struct notifier_block *self, unsigned long action,
241 switch (action & ~CPU_TASKS_FROZEN) {
243 gt_clockevents_init(this_cpu_ptr(gt_evt));
246 gt_clockevents_stop(this_cpu_ptr(gt_evt));
252 static struct notifier_block gt_cpu_nb = {
253 .notifier_call = gt_cpu_notify,
256 static void __init global_timer_of_register(struct device_node *np)
262 * In A9 r2p0 the comparators for each processor with the global timer
263 * fire when the timer value is greater than or equal to. In previous
264 * revisions the comparators fired when the timer value was equal to.
266 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9
267 && (read_cpuid_id() & 0xf0000f) < 0x200000) {
268 pr_warn("global-timer: non support for this cpu version.\n");
272 gt_ppi = irq_of_parse_and_map(np, 0);
274 pr_warn("global-timer: unable to parse irq\n");
278 gt_base = of_iomap(np, 0);
280 pr_warn("global-timer: invalid base address\n");
284 gt_clk = of_clk_get(np, 0);
285 if (!IS_ERR(gt_clk)) {
286 err = clk_prepare_enable(gt_clk);
290 pr_warn("global-timer: clk not found\n");
295 gt_clk_rate = clk_get_rate(gt_clk);
296 gt_evt = alloc_percpu(struct clock_event_device);
298 pr_warn("global-timer: can't allocate memory\n");
303 err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt,
306 pr_warn("global-timer: can't register interrupt %d (%d)\n",
311 err = register_cpu_notifier(>_cpu_nb);
313 pr_warn("global-timer: unable to register cpu notifier.\n");
317 /* Immediately configure the timer on the boot CPU */
318 gt_clocksource_init();
319 gt_clockevents_init(this_cpu_ptr(gt_evt));
324 free_percpu_irq(gt_ppi, gt_evt);
328 clk_disable_unprepare(gt_clk);
331 WARN(err, "ARM Global timer register failed (%d)\n", err);
334 /* Only tested on r2p2 and r3p0 */
335 CLOCKSOURCE_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",
336 global_timer_of_register);