drivers/clk/zynqmp/clk-zynqmp.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  *  Copyright (C) 2016-2018 Xilinx
   4  */
   5
   6 #ifndef __LINUX_CLK_ZYNQMP_H_
   7 #define __LINUX_CLK_ZYNQMP_H_
   8
   9 #include <linux/spinlock.h>
  10
  11 #include <linux/firmware/xlnx-zynqmp.h>
  12
  13 /* Clock APIs payload parameters */
  14 #define CLK_GET_NAME_RESP_LEN                           16
  15 #define CLK_GET_TOPOLOGY_RESP_WORDS                     3
  16 #define CLK_GET_PARENTS_RESP_WORDS                      3
  17 #define CLK_GET_ATTR_RESP_WORDS                         1
  18
  19 enum topology_type {
  20         TYPE_INVALID,
  21         TYPE_MUX,
  22         TYPE_PLL,
  23         TYPE_FIXEDFACTOR,
  24         TYPE_DIV1,
  25         TYPE_DIV2,
  26         TYPE_GATE,
  27 };
  28
  29 /**
  30  * struct clock_topology - Clock topology
  31  * @type:       Type of topology
  32  * @flag:       Topology flags
  33  * @type_flag:  Topology type specific flag
  34  */
  35 struct clock_topology {
  36         u32 type;
  37         u32 flag;
  38         u32 type_flag;
  39 };
  40
  41 struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
  42                                        const char * const *parents,
  43                                        u8 num_parents,
  44                                        const struct clock_topology *nodes);
  45
  46 struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
  47                                         const char * const *parents,
  48                                         u8 num_parents,
  49                                         const struct clock_topology *nodes);
  50
  51 struct clk_hw *zynqmp_clk_register_divider(const char *name,
  52                                            u32 clk_id,
  53                                            const char * const *parents,
  54                                            u8 num_parents,
  55                                            const struct clock_topology *nodes);
  56
  57 struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
  58                                        const char * const *parents,
  59                                        u8 num_parents,
  60                                        const struct clock_topology *nodes);
  61
  62 struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name,
  63                                         u32 clk_id,
  64                                         const char * const *parents,
  65                                         u8 num_parents,
  66                                         const struct clock_topology *nodes);
  67
  68 #endif