1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx 'Clocking Wizard' driver
5 * Copyright (C) 2013 - 2021 Xilinx
7 * Sören Brinkmann <soren.brinkmann@xilinx.com>
11 #include <linux/platform_device.h>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/slab.h>
17 #include <linux/module.h>
18 #include <linux/err.h>
19 #include <linux/iopoll.h>
21 #define WZRD_NUM_OUTPUTS 7
22 #define WZRD_ACLK_MAX_FREQ 250000000UL
24 #define WZRD_CLK_CFG_REG(n) (0x200 + 4 * (n))
26 #define WZRD_CLKOUT0_FRAC_EN BIT(18)
27 #define WZRD_CLKFBOUT_FRAC_EN BIT(26)
29 #define WZRD_CLKFBOUT_MULT_SHIFT 8
30 #define WZRD_CLKFBOUT_MULT_MASK (0xff << WZRD_CLKFBOUT_MULT_SHIFT)
31 #define WZRD_CLKFBOUT_FRAC_SHIFT 16
32 #define WZRD_CLKFBOUT_FRAC_MASK (0x3ff << WZRD_CLKFBOUT_FRAC_SHIFT)
33 #define WZRD_DIVCLK_DIVIDE_SHIFT 0
34 #define WZRD_DIVCLK_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT)
35 #define WZRD_CLKOUT_DIVIDE_SHIFT 0
36 #define WZRD_CLKOUT_DIVIDE_WIDTH 8
37 #define WZRD_CLKOUT_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT)
38 #define WZRD_CLKOUT_FRAC_SHIFT 8
39 #define WZRD_CLKOUT_FRAC_MASK 0x3ff
41 #define WZRD_DR_MAX_INT_DIV_VALUE 255
42 #define WZRD_DR_STATUS_REG_OFFSET 0x04
43 #define WZRD_DR_LOCK_BIT_MASK 0x00000001
44 #define WZRD_DR_INIT_REG_OFFSET 0x25C
45 #define WZRD_DR_DIV_TO_PHASE_OFFSET 4
46 #define WZRD_DR_BEGIN_DYNA_RECONF 0x03
47 #define WZRD_DR_BEGIN_DYNA_RECONF_5_2 0x07
48 #define WZRD_DR_BEGIN_DYNA_RECONF1_5_2 0x02
50 #define WZRD_USEC_POLL 10
51 #define WZRD_TIMEOUT_POLL 1000
52 /* Get the mask from width */
53 #define div_mask(width) ((1 << (width)) - 1)
55 /* Extract divider instance from clock hardware instance */
56 #define to_clk_wzrd_divider(_hw) container_of(_hw, struct clk_wzrd_divider, hw)
58 enum clk_wzrd_int_clks {
66 * struct clk_wzrd - Clock wizard private data structure
68 * @clk_data: Clock data
71 * @clk_in1: Handle to input clock 'clk_in1'
72 * @axi_clk: Handle to input clock 's_axi_aclk'
73 * @clks_internal: Internal clocks
74 * @clkout: Output clocks
75 * @speed_grade: Speed grade of the device
76 * @suspended: Flag indicating power state of the device
79 struct clk_onecell_data clk_data;
80 struct notifier_block nb;
84 struct clk *clks_internal[wzrd_clk_int_max];
85 struct clk *clkout[WZRD_NUM_OUTPUTS];
86 unsigned int speed_grade;
91 * struct clk_wzrd_divider - clock divider specific to clk_wzrd
93 * @hw: handle between common and hardware-specific interfaces
94 * @base: base address of register containing the divider
95 * @offset: offset address of register containing the divider
96 * @shift: shift to the divider bit field
97 * @width: width of the divider bit field
98 * @flags: clk_wzrd divider flags
99 * @table: array of value/divider pairs, last entry should have div = 0
100 * @lock: register lock
102 struct clk_wzrd_divider {
109 const struct clk_div_table *table;
110 spinlock_t *lock; /* divider lock */
113 #define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb)
115 /* maximum frequencies for input/output clocks per speed grade */
116 static const unsigned long clk_wzrd_max_freq[] = {
122 /* spin lock variable for clk_wzrd */
123 static DEFINE_SPINLOCK(clkwzrd_lock);
125 static unsigned long clk_wzrd_recalc_rate(struct clk_hw *hw,
126 unsigned long parent_rate)
128 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
129 void __iomem *div_addr = divider->base + divider->offset;
132 val = readl(div_addr) >> divider->shift;
133 val &= div_mask(divider->width);
135 return divider_recalc_rate(hw, parent_rate, val, divider->table,
136 divider->flags, divider->width);
139 static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate,
140 unsigned long parent_rate)
144 unsigned long flags = 0;
145 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
146 void __iomem *div_addr = divider->base + divider->offset;
149 spin_lock_irqsave(divider->lock, flags);
151 __acquire(divider->lock);
153 value = DIV_ROUND_CLOSEST(parent_rate, rate);
155 /* Cap the value to max */
156 min_t(u32, value, WZRD_DR_MAX_INT_DIV_VALUE);
158 /* Set divisor and clear phase offset */
159 writel(value, div_addr);
160 writel(0x00, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET);
162 /* Check status register */
163 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
164 value, value & WZRD_DR_LOCK_BIT_MASK,
165 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
169 /* Initiate reconfiguration */
170 writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2,
171 divider->base + WZRD_DR_INIT_REG_OFFSET);
172 writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2,
173 divider->base + WZRD_DR_INIT_REG_OFFSET);
175 /* Check status register */
176 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
177 value, value & WZRD_DR_LOCK_BIT_MASK,
178 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
181 spin_unlock_irqrestore(divider->lock, flags);
183 __release(divider->lock);
187 static long clk_wzrd_round_rate(struct clk_hw *hw, unsigned long rate,
188 unsigned long *prate)
193 * since we don't change parent rate we just round rate to closest
196 div = DIV_ROUND_CLOSEST(*prate, rate);
201 static const struct clk_ops clk_wzrd_clk_divider_ops = {
202 .round_rate = clk_wzrd_round_rate,
203 .set_rate = clk_wzrd_dynamic_reconfig,
204 .recalc_rate = clk_wzrd_recalc_rate,
207 static unsigned long clk_wzrd_recalc_ratef(struct clk_hw *hw,
208 unsigned long parent_rate)
212 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
213 void __iomem *div_addr = divider->base + divider->offset;
215 val = readl(div_addr);
216 div = val & div_mask(divider->width);
217 frac = (val >> WZRD_CLKOUT_FRAC_SHIFT) & WZRD_CLKOUT_FRAC_MASK;
219 return mult_frac(parent_rate, 1000, (div * 1000) + frac);
222 static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate,
223 unsigned long parent_rate)
227 unsigned long rate_div, f, clockout0_div;
228 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
229 void __iomem *div_addr = divider->base + divider->offset;
231 rate_div = DIV_ROUND_DOWN_ULL(parent_rate * 1000, rate);
232 clockout0_div = rate_div / 1000;
234 pre = DIV_ROUND_CLOSEST((parent_rate * 1000), rate);
235 f = (u32)(pre - (clockout0_div * 1000));
236 f = f & WZRD_CLKOUT_FRAC_MASK;
237 f = f << WZRD_CLKOUT_DIVIDE_WIDTH;
239 value = (f | (clockout0_div & WZRD_CLKOUT_DIVIDE_MASK));
241 /* Set divisor and clear phase offset */
242 writel(value, div_addr);
243 writel(0x0, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET);
245 /* Check status register */
246 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
247 value & WZRD_DR_LOCK_BIT_MASK,
248 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
252 /* Initiate reconfiguration */
253 writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2,
254 divider->base + WZRD_DR_INIT_REG_OFFSET);
255 writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2,
256 divider->base + WZRD_DR_INIT_REG_OFFSET);
258 /* Check status register */
259 return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
260 value & WZRD_DR_LOCK_BIT_MASK,
261 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
264 static long clk_wzrd_round_rate_f(struct clk_hw *hw, unsigned long rate,
265 unsigned long *prate)
270 static const struct clk_ops clk_wzrd_clk_divider_ops_f = {
271 .round_rate = clk_wzrd_round_rate_f,
272 .set_rate = clk_wzrd_dynamic_reconfig_f,
273 .recalc_rate = clk_wzrd_recalc_ratef,
276 static struct clk *clk_wzrd_register_divf(struct device *dev,
278 const char *parent_name,
280 void __iomem *base, u16 offset,
282 u8 clk_divider_flags,
283 const struct clk_div_table *table,
286 struct clk_wzrd_divider *div;
288 struct clk_init_data init;
291 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
293 return ERR_PTR(-ENOMEM);
297 init.ops = &clk_wzrd_clk_divider_ops_f;
300 init.parent_names = &parent_name;
301 init.num_parents = 1;
304 div->offset = offset;
307 div->flags = clk_divider_flags;
309 div->hw.init = &init;
313 ret = devm_clk_hw_register(dev, hw);
320 static struct clk *clk_wzrd_register_divider(struct device *dev,
322 const char *parent_name,
324 void __iomem *base, u16 offset,
326 u8 clk_divider_flags,
327 const struct clk_div_table *table,
330 struct clk_wzrd_divider *div;
332 struct clk_init_data init;
335 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
337 return ERR_PTR(-ENOMEM);
340 init.ops = &clk_wzrd_clk_divider_ops;
342 init.parent_names = &parent_name;
343 init.num_parents = 1;
346 div->offset = offset;
349 div->flags = clk_divider_flags;
351 div->hw.init = &init;
355 ret = devm_clk_hw_register(dev, hw);
362 static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long event,
366 struct clk_notifier_data *ndata = data;
367 struct clk_wzrd *clk_wzrd = to_clk_wzrd(nb);
369 if (clk_wzrd->suspended)
372 if (ndata->clk == clk_wzrd->clk_in1)
373 max = clk_wzrd_max_freq[clk_wzrd->speed_grade - 1];
374 else if (ndata->clk == clk_wzrd->axi_clk)
375 max = WZRD_ACLK_MAX_FREQ;
377 return NOTIFY_DONE; /* should never happen */
380 case PRE_RATE_CHANGE:
381 if (ndata->new_rate > max)
384 case POST_RATE_CHANGE:
385 case ABORT_RATE_CHANGE:
391 static int __maybe_unused clk_wzrd_suspend(struct device *dev)
393 struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev);
395 clk_disable_unprepare(clk_wzrd->axi_clk);
396 clk_wzrd->suspended = true;
401 static int __maybe_unused clk_wzrd_resume(struct device *dev)
404 struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev);
406 ret = clk_prepare_enable(clk_wzrd->axi_clk);
408 dev_err(dev, "unable to enable s_axi_aclk\n");
412 clk_wzrd->suspended = false;
417 static SIMPLE_DEV_PM_OPS(clk_wzrd_dev_pm_ops, clk_wzrd_suspend,
420 static int clk_wzrd_probe(struct platform_device *pdev)
423 u32 reg, reg_f, mult;
425 const char *clk_name;
426 void __iomem *ctrl_reg;
427 struct clk_wzrd *clk_wzrd;
428 struct device_node *np = pdev->dev.of_node;
430 unsigned long flags = 0;
432 clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL);
435 platform_set_drvdata(pdev, clk_wzrd);
437 clk_wzrd->base = devm_platform_ioremap_resource(pdev, 0);
438 if (IS_ERR(clk_wzrd->base))
439 return PTR_ERR(clk_wzrd->base);
441 ret = of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_grade);
443 if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) {
444 dev_warn(&pdev->dev, "invalid speed grade '%d'\n",
445 clk_wzrd->speed_grade);
446 clk_wzrd->speed_grade = 0;
450 clk_wzrd->clk_in1 = devm_clk_get(&pdev->dev, "clk_in1");
451 if (IS_ERR(clk_wzrd->clk_in1))
452 return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->clk_in1),
453 "clk_in1 not found\n");
455 clk_wzrd->axi_clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
456 if (IS_ERR(clk_wzrd->axi_clk))
457 return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->axi_clk),
458 "s_axi_aclk not found\n");
459 ret = clk_prepare_enable(clk_wzrd->axi_clk);
461 dev_err(&pdev->dev, "enabling s_axi_aclk failed\n");
464 rate = clk_get_rate(clk_wzrd->axi_clk);
465 if (rate > WZRD_ACLK_MAX_FREQ) {
466 dev_err(&pdev->dev, "s_axi_aclk frequency (%lu) too high\n",
469 goto err_disable_clk;
472 reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0));
473 reg_f = reg & WZRD_CLKFBOUT_FRAC_MASK;
474 reg_f = reg_f >> WZRD_CLKFBOUT_FRAC_SHIFT;
476 reg = reg & WZRD_CLKFBOUT_MULT_MASK;
477 reg = reg >> WZRD_CLKFBOUT_MULT_SHIFT;
478 mult = (reg * 1000) + reg_f;
479 clk_name = kasprintf(GFP_KERNEL, "%s_mul", dev_name(&pdev->dev));
482 goto err_disable_clk;
485 ret = of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs);
486 if (ret || nr_outputs > WZRD_NUM_OUTPUTS) {
488 goto err_disable_clk;
491 flags = CLK_SET_RATE_PARENT;
493 clk_wzrd->clks_internal[wzrd_clk_mul] = clk_register_fixed_factor
494 (&pdev->dev, clk_name,
495 __clk_get_name(clk_wzrd->clk_in1),
497 if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul])) {
498 dev_err(&pdev->dev, "unable to register fixed-factor clock\n");
499 ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul]);
500 goto err_disable_clk;
503 clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev));
509 ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(0);
511 clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_divider
512 (&pdev->dev, clk_name,
513 __clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]),
514 flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED |
515 CLK_DIVIDER_ALLOW_ZERO, &clkwzrd_lock);
516 if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) {
517 dev_err(&pdev->dev, "unable to register divider clock\n");
518 ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]);
522 /* register div per output */
523 for (i = nr_outputs - 1; i >= 0 ; i--) {
524 const char *clkout_name;
526 clkout_name = kasprintf(GFP_KERNEL, "%s_out%d", dev_name(&pdev->dev), i);
533 clk_wzrd->clkout[i] = clk_wzrd_register_divf
534 (&pdev->dev, clkout_name,
536 clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),
537 WZRD_CLKOUT_DIVIDE_SHIFT,
538 WZRD_CLKOUT_DIVIDE_WIDTH,
539 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
540 NULL, &clkwzrd_lock);
542 clk_wzrd->clkout[i] = clk_wzrd_register_divider
543 (&pdev->dev, clkout_name,
545 clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),
546 WZRD_CLKOUT_DIVIDE_SHIFT,
547 WZRD_CLKOUT_DIVIDE_WIDTH,
548 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
549 NULL, &clkwzrd_lock);
550 if (IS_ERR(clk_wzrd->clkout[i])) {
553 for (j = i + 1; j < nr_outputs; j++)
554 clk_unregister(clk_wzrd->clkout[j]);
556 "unable to register divider clock\n");
557 ret = PTR_ERR(clk_wzrd->clkout[i]);
558 goto err_rm_int_clks;
564 clk_wzrd->clk_data.clks = clk_wzrd->clkout;
565 clk_wzrd->clk_data.clk_num = ARRAY_SIZE(clk_wzrd->clkout);
566 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_wzrd->clk_data);
568 if (clk_wzrd->speed_grade) {
569 clk_wzrd->nb.notifier_call = clk_wzrd_clk_notifier;
571 ret = clk_notifier_register(clk_wzrd->clk_in1,
575 "unable to register clock notifier\n");
577 ret = clk_notifier_register(clk_wzrd->axi_clk, &clk_wzrd->nb);
580 "unable to register clock notifier\n");
586 clk_unregister(clk_wzrd->clks_internal[1]);
589 clk_unregister(clk_wzrd->clks_internal[0]);
591 clk_disable_unprepare(clk_wzrd->axi_clk);
596 static int clk_wzrd_remove(struct platform_device *pdev)
599 struct clk_wzrd *clk_wzrd = platform_get_drvdata(pdev);
601 of_clk_del_provider(pdev->dev.of_node);
603 for (i = 0; i < WZRD_NUM_OUTPUTS; i++)
604 clk_unregister(clk_wzrd->clkout[i]);
605 for (i = 0; i < wzrd_clk_int_max; i++)
606 clk_unregister(clk_wzrd->clks_internal[i]);
608 if (clk_wzrd->speed_grade) {
609 clk_notifier_unregister(clk_wzrd->axi_clk, &clk_wzrd->nb);
610 clk_notifier_unregister(clk_wzrd->clk_in1, &clk_wzrd->nb);
613 clk_disable_unprepare(clk_wzrd->axi_clk);
618 static const struct of_device_id clk_wzrd_ids[] = {
619 { .compatible = "xlnx,clocking-wizard" },
620 { .compatible = "xlnx,clocking-wizard-v5.2" },
621 { .compatible = "xlnx,clocking-wizard-v6.0" },
624 MODULE_DEVICE_TABLE(of, clk_wzrd_ids);
626 static struct platform_driver clk_wzrd_driver = {
628 .name = "clk-wizard",
629 .of_match_table = clk_wzrd_ids,
630 .pm = &clk_wzrd_dev_pm_ops,
632 .probe = clk_wzrd_probe,
633 .remove = clk_wzrd_remove,
635 module_platform_driver(clk_wzrd_driver);
637 MODULE_LICENSE("GPL");
638 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com");
639 MODULE_DESCRIPTION("Driver for the Xilinx Clocking Wizard IP core");