2 * Intel Atom platform clocks driver for BayTrail and CherryTrail SoCs
4 * Copyright (C) 2016, Intel Corporation
5 * Author: Irina Tirdea <irina.tirdea@intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
19 #include <linux/err.h>
21 #include <linux/platform_data/x86/clk-pmc-atom.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
25 #define PLT_CLK_NAME_BASE "pmc_plt_clk"
27 #define PMC_CLK_CTL_OFFSET 0x60
28 #define PMC_CLK_CTL_SIZE 4
30 #define PMC_CLK_CTL_GATED_ON_D3 0x0
31 #define PMC_CLK_CTL_FORCE_ON 0x1
32 #define PMC_CLK_CTL_FORCE_OFF 0x2
33 #define PMC_CLK_CTL_RESERVED 0x3
34 #define PMC_MASK_CLK_CTL GENMASK(1, 0)
35 #define PMC_MASK_CLK_FREQ BIT(2)
36 #define PMC_CLK_FREQ_XTAL (0 << 2) /* 25 MHz */
37 #define PMC_CLK_FREQ_PLL (1 << 2) /* 19.2 MHz */
39 struct clk_plt_fixed {
41 struct clk_lookup *lookup;
47 struct clk_lookup *lookup;
48 /* protect access to PMC registers */
52 #define to_clk_plt(_hw) container_of(_hw, struct clk_plt, hw)
55 struct clk_plt_fixed **parents;
57 struct clk_plt *clks[PMC_CLK_NUM];
58 struct clk_lookup *mclk_lookup;
59 struct clk_lookup *ether_clk_lookup;
62 /* Return an index in parent table */
63 static inline int plt_reg_to_parent(int reg)
65 switch (reg & PMC_MASK_CLK_FREQ) {
67 case PMC_CLK_FREQ_XTAL:
69 case PMC_CLK_FREQ_PLL:
74 /* Return clk index of parent */
75 static inline int plt_parent_to_reg(int index)
80 return PMC_CLK_FREQ_XTAL;
82 return PMC_CLK_FREQ_PLL;
86 /* Abstract status in simpler enabled/disabled value */
87 static inline int plt_reg_to_enabled(int reg)
89 switch (reg & PMC_MASK_CLK_CTL) {
90 case PMC_CLK_CTL_GATED_ON_D3:
91 case PMC_CLK_CTL_FORCE_ON:
92 return 1; /* enabled */
93 case PMC_CLK_CTL_FORCE_OFF:
94 case PMC_CLK_CTL_RESERVED:
96 return 0; /* disabled */
100 static void plt_clk_reg_update(struct clk_plt *clk, u32 mask, u32 val)
105 spin_lock_irqsave(&clk->lock, flags);
107 tmp = readl(clk->reg);
108 tmp = (tmp & ~mask) | (val & mask);
109 writel(tmp, clk->reg);
111 spin_unlock_irqrestore(&clk->lock, flags);
114 static int plt_clk_set_parent(struct clk_hw *hw, u8 index)
116 struct clk_plt *clk = to_clk_plt(hw);
118 plt_clk_reg_update(clk, PMC_MASK_CLK_FREQ, plt_parent_to_reg(index));
123 static u8 plt_clk_get_parent(struct clk_hw *hw)
125 struct clk_plt *clk = to_clk_plt(hw);
128 value = readl(clk->reg);
130 return plt_reg_to_parent(value);
133 static int plt_clk_enable(struct clk_hw *hw)
135 struct clk_plt *clk = to_clk_plt(hw);
137 plt_clk_reg_update(clk, PMC_MASK_CLK_CTL, PMC_CLK_CTL_FORCE_ON);
142 static void plt_clk_disable(struct clk_hw *hw)
144 struct clk_plt *clk = to_clk_plt(hw);
146 plt_clk_reg_update(clk, PMC_MASK_CLK_CTL, PMC_CLK_CTL_FORCE_OFF);
149 static int plt_clk_is_enabled(struct clk_hw *hw)
151 struct clk_plt *clk = to_clk_plt(hw);
154 value = readl(clk->reg);
156 return plt_reg_to_enabled(value);
159 static const struct clk_ops plt_clk_ops = {
160 .enable = plt_clk_enable,
161 .disable = plt_clk_disable,
162 .is_enabled = plt_clk_is_enabled,
163 .get_parent = plt_clk_get_parent,
164 .set_parent = plt_clk_set_parent,
165 .determine_rate = __clk_mux_determine_rate,
168 static struct clk_plt *plt_clk_register(struct platform_device *pdev, int id,
169 const struct pmc_clk_data *pmc_data,
170 const char **parent_names,
173 struct clk_plt *pclk;
174 struct clk_init_data init;
177 pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL);
179 return ERR_PTR(-ENOMEM);
181 init.name = kasprintf(GFP_KERNEL, "%s_%d", PLT_CLK_NAME_BASE, id);
182 init.ops = &plt_clk_ops;
184 init.parent_names = parent_names;
185 init.num_parents = num_parents;
187 pclk->hw.init = &init;
188 pclk->reg = pmc_data->base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE;
189 spin_lock_init(&pclk->lock);
192 * On some systems, the pmc_plt_clocks already enabled by the
193 * firmware are being marked as critical to avoid them being
194 * gated by the clock framework.
196 if (pmc_data->critical && plt_clk_is_enabled(&pclk->hw))
197 init.flags |= CLK_IS_CRITICAL;
199 ret = devm_clk_hw_register(&pdev->dev, &pclk->hw);
205 pclk->lookup = clkdev_hw_create(&pclk->hw, init.name, NULL);
207 pclk = ERR_PTR(-ENOMEM);
216 static void plt_clk_unregister(struct clk_plt *pclk)
218 clkdev_drop(pclk->lookup);
221 static struct clk_plt_fixed *plt_clk_register_fixed_rate(struct platform_device *pdev,
223 const char *parent_name,
224 unsigned long fixed_rate)
226 struct clk_plt_fixed *pclk;
228 pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL);
230 return ERR_PTR(-ENOMEM);
232 pclk->clk = clk_hw_register_fixed_rate(&pdev->dev, name, parent_name,
234 if (IS_ERR(pclk->clk))
235 return ERR_CAST(pclk->clk);
237 pclk->lookup = clkdev_hw_create(pclk->clk, name, NULL);
239 clk_hw_unregister_fixed_rate(pclk->clk);
240 return ERR_PTR(-ENOMEM);
246 static void plt_clk_unregister_fixed_rate(struct clk_plt_fixed *pclk)
248 clkdev_drop(pclk->lookup);
249 clk_hw_unregister_fixed_rate(pclk->clk);
252 static void plt_clk_unregister_fixed_rate_loop(struct clk_plt_data *data,
256 plt_clk_unregister_fixed_rate(data->parents[i]);
259 static void plt_clk_free_parent_names_loop(const char **parent_names,
263 kfree_const(parent_names[i]);
267 static void plt_clk_unregister_loop(struct clk_plt_data *data,
271 plt_clk_unregister(data->clks[i]);
274 static const char **plt_clk_register_parents(struct platform_device *pdev,
275 struct clk_plt_data *data,
276 const struct pmc_clk *clks)
278 const char **parent_names;
284 while (clks[nparents].name)
287 data->parents = devm_kcalloc(&pdev->dev, nparents,
288 sizeof(*data->parents), GFP_KERNEL);
290 return ERR_PTR(-ENOMEM);
292 parent_names = kcalloc(nparents, sizeof(*parent_names),
295 return ERR_PTR(-ENOMEM);
297 for (i = 0; i < nparents; i++) {
299 plt_clk_register_fixed_rate(pdev, clks[i].name,
302 if (IS_ERR(data->parents[i])) {
303 err = PTR_ERR(data->parents[i]);
306 parent_names[i] = kstrdup_const(clks[i].name, GFP_KERNEL);
309 data->nparents = nparents;
313 plt_clk_unregister_fixed_rate_loop(data, i);
314 plt_clk_free_parent_names_loop(parent_names, i);
318 static void plt_clk_unregister_parents(struct clk_plt_data *data)
320 plt_clk_unregister_fixed_rate_loop(data, data->nparents);
323 static int plt_clk_probe(struct platform_device *pdev)
325 const struct pmc_clk_data *pmc_data;
326 const char **parent_names;
327 struct clk_plt_data *data;
331 pmc_data = dev_get_platdata(&pdev->dev);
332 if (!pmc_data || !pmc_data->clks)
335 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
339 parent_names = plt_clk_register_parents(pdev, data, pmc_data->clks);
340 if (IS_ERR(parent_names))
341 return PTR_ERR(parent_names);
343 for (i = 0; i < PMC_CLK_NUM; i++) {
344 data->clks[i] = plt_clk_register(pdev, i, pmc_data,
345 parent_names, data->nparents);
346 if (IS_ERR(data->clks[i])) {
347 err = PTR_ERR(data->clks[i]);
348 goto err_unreg_clk_plt;
351 data->mclk_lookup = clkdev_hw_create(&data->clks[3]->hw, "mclk", NULL);
352 if (!data->mclk_lookup) {
354 goto err_unreg_clk_plt;
357 data->ether_clk_lookup = clkdev_hw_create(&data->clks[4]->hw,
359 if (!data->ether_clk_lookup) {
364 plt_clk_free_parent_names_loop(parent_names, data->nparents);
366 platform_set_drvdata(pdev, data);
370 clkdev_drop(data->mclk_lookup);
372 plt_clk_unregister_loop(data, i);
373 plt_clk_unregister_parents(data);
374 plt_clk_free_parent_names_loop(parent_names, data->nparents);
378 static int plt_clk_remove(struct platform_device *pdev)
380 struct clk_plt_data *data;
382 data = platform_get_drvdata(pdev);
384 clkdev_drop(data->ether_clk_lookup);
385 clkdev_drop(data->mclk_lookup);
386 plt_clk_unregister_loop(data, PMC_CLK_NUM);
387 plt_clk_unregister_parents(data);
391 static struct platform_driver plt_clk_driver = {
393 .name = "clk-pmc-atom",
395 .probe = plt_clk_probe,
396 .remove = plt_clk_remove,
398 builtin_platform_driver(plt_clk_driver);