1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2021 TOSHIBA CORPORATION
4 * Copyright (c) 2021 Toshiba Electronic Devices & Storage Corporation
6 * Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
9 #ifndef _VISCONTI_PLL_H_
10 #define _VISCONTI_PLL_H_
12 #include <linux/clk-provider.h>
13 #include <linux/regmap.h>
14 #include <linux/spinlock.h>
16 struct visconti_pll_provider {
17 void __iomem *reg_base;
18 struct regmap *regmap;
19 struct clk_hw_onecell_data clk_data;
20 struct device_node *node;
23 #define VISCONTI_PLL_RATE(_rate, _dacen, _dsmen, \
24 _refdiv, _intin, _fracin, _postdiv1, _postdiv2) \
32 .postdiv1 = _postdiv1, \
33 .postdiv2 = _postdiv2 \
36 struct visconti_pll_rate_table {
43 unsigned int postdiv1;
44 unsigned int postdiv2;
47 struct visconti_pll_info {
51 unsigned long base_reg;
52 const struct visconti_pll_rate_table *rate_table;
55 struct visconti_pll_provider * __init visconti_init_pll(struct device_node *np,
57 unsigned long nr_plls);
58 void visconti_register_plls(struct visconti_pll_provider *ctx,
59 const struct visconti_pll_info *list,
60 unsigned int nr_plls, spinlock_t *lock);
62 #endif /* _VISCONTI_PLL_H_ */