2 * Sysctrl clock implementation for ux500 platform.
4 * Copyright (C) 2013 ST-Ericsson SA
5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
7 * License terms: GNU General Public License (GPL) version 2
10 #include <linux/clk-provider.h>
11 #include <linux/mfd/abx500/ab8500-sysctrl.h>
12 #include <linux/device.h>
13 #include <linux/slab.h>
14 #include <linux/delay.h>
16 #include <linux/err.h>
19 #define SYSCTRL_MAX_NUM_PARENTS 4
21 #define to_clk_sysctrl(_hw) container_of(_hw, struct clk_sysctrl, hw)
27 u16 reg_sel[SYSCTRL_MAX_NUM_PARENTS];
28 u8 reg_mask[SYSCTRL_MAX_NUM_PARENTS];
29 u8 reg_bits[SYSCTRL_MAX_NUM_PARENTS];
31 unsigned long enable_delay_us;
34 /* Sysctrl clock operations. */
36 static int clk_sysctrl_prepare(struct clk_hw *hw)
39 struct clk_sysctrl *clk = to_clk_sysctrl(hw);
41 ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0],
44 if (!ret && clk->enable_delay_us)
45 usleep_range(clk->enable_delay_us, clk->enable_delay_us +
46 (clk->enable_delay_us >> 2));
51 static void clk_sysctrl_unprepare(struct clk_hw *hw)
53 struct clk_sysctrl *clk = to_clk_sysctrl(hw);
54 if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0]))
55 dev_err(clk->dev, "clk_sysctrl: %s fail to clear %s.\n",
56 __func__, clk_hw_get_name(hw));
59 static unsigned long clk_sysctrl_recalc_rate(struct clk_hw *hw,
60 unsigned long parent_rate)
62 struct clk_sysctrl *clk = to_clk_sysctrl(hw);
66 static int clk_sysctrl_set_parent(struct clk_hw *hw, u8 index)
68 struct clk_sysctrl *clk = to_clk_sysctrl(hw);
69 u8 old_index = clk->parent_index;
72 if (clk->reg_sel[old_index]) {
73 ret = ab8500_sysctrl_clear(clk->reg_sel[old_index],
74 clk->reg_mask[old_index]);
79 if (clk->reg_sel[index]) {
80 ret = ab8500_sysctrl_write(clk->reg_sel[index],
82 clk->reg_bits[index]);
84 if (clk->reg_sel[old_index])
85 ab8500_sysctrl_write(clk->reg_sel[old_index],
86 clk->reg_mask[old_index],
87 clk->reg_bits[old_index]);
91 clk->parent_index = index;
96 static u8 clk_sysctrl_get_parent(struct clk_hw *hw)
98 struct clk_sysctrl *clk = to_clk_sysctrl(hw);
99 return clk->parent_index;
102 static const struct clk_ops clk_sysctrl_gate_ops = {
103 .prepare = clk_sysctrl_prepare,
104 .unprepare = clk_sysctrl_unprepare,
107 static const struct clk_ops clk_sysctrl_gate_fixed_rate_ops = {
108 .prepare = clk_sysctrl_prepare,
109 .unprepare = clk_sysctrl_unprepare,
110 .recalc_rate = clk_sysctrl_recalc_rate,
113 static const struct clk_ops clk_sysctrl_set_parent_ops = {
114 .set_parent = clk_sysctrl_set_parent,
115 .get_parent = clk_sysctrl_get_parent,
118 static struct clk *clk_reg_sysctrl(struct device *dev,
120 const char **parent_names,
126 unsigned long enable_delay_us,
128 const struct clk_ops *clk_sysctrl_ops)
130 struct clk_sysctrl *clk;
131 struct clk_init_data clk_sysctrl_init;
136 return ERR_PTR(-EINVAL);
138 if (!name || (num_parents > SYSCTRL_MAX_NUM_PARENTS)) {
139 dev_err(dev, "clk_sysctrl: invalid arguments passed\n");
140 return ERR_PTR(-EINVAL);
143 clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
145 return ERR_PTR(-ENOMEM);
147 /* set main clock registers */
148 clk->reg_sel[0] = reg_sel[0];
149 clk->reg_bits[0] = reg_bits[0];
150 clk->reg_mask[0] = reg_mask[0];
152 /* handle clocks with more than one parent */
153 for (i = 1; i < num_parents; i++) {
154 clk->reg_sel[i] = reg_sel[i];
155 clk->reg_bits[i] = reg_bits[i];
156 clk->reg_mask[i] = reg_mask[i];
159 clk->parent_index = 0;
161 clk->enable_delay_us = enable_delay_us;
164 clk_sysctrl_init.name = name;
165 clk_sysctrl_init.ops = clk_sysctrl_ops;
166 clk_sysctrl_init.flags = flags;
167 clk_sysctrl_init.parent_names = parent_names;
168 clk_sysctrl_init.num_parents = num_parents;
169 clk->hw.init = &clk_sysctrl_init;
171 clk_reg = devm_clk_register(clk->dev, &clk->hw);
173 dev_err(dev, "clk_sysctrl: clk_register failed\n");
178 struct clk *clk_reg_sysctrl_gate(struct device *dev,
180 const char *parent_name,
184 unsigned long enable_delay_us,
187 const char **parent_names = (parent_name ? &parent_name : NULL);
188 u8 num_parents = (parent_name ? 1 : 0);
190 return clk_reg_sysctrl(dev, name, parent_names, num_parents,
191 ®_sel, ®_mask, ®_bits, 0, enable_delay_us,
192 flags, &clk_sysctrl_gate_ops);
195 struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev,
197 const char *parent_name,
202 unsigned long enable_delay_us,
205 const char **parent_names = (parent_name ? &parent_name : NULL);
206 u8 num_parents = (parent_name ? 1 : 0);
208 return clk_reg_sysctrl(dev, name, parent_names, num_parents,
209 ®_sel, ®_mask, ®_bits,
210 rate, enable_delay_us, flags,
211 &clk_sysctrl_gate_fixed_rate_ops);
214 struct clk *clk_reg_sysctrl_set_parent(struct device *dev,
216 const char **parent_names,
223 return clk_reg_sysctrl(dev, name, parent_names, num_parents,
224 reg_sel, reg_mask, reg_bits, 0, 0, flags,
225 &clk_sysctrl_set_parent_ops);