drivers/clk/ti/dpll.c

   1 /*
   2  * OMAP DPLL clock support
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * Tero Kristo <t-kristo@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/clk-provider.h>
  20 #include <linux/slab.h>
  21 #include <linux/err.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/clk/ti.h>
  25 #include "clock.h"
  26
  27 #undef pr_fmt
  28 #define pr_fmt(fmt) "%s: " fmt, __func__
  29
  30 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
  31         defined(CONFIG_SOC_DRA7XX)
  32 static const struct clk_ops dpll_m4xen_ck_ops = {
  33         .enable         = &omap3_noncore_dpll_enable,
  34         .disable        = &omap3_noncore_dpll_disable,
  35         .recalc_rate    = &omap4_dpll_regm4xen_recalc,
  36         .round_rate     = &omap4_dpll_regm4xen_round_rate,
  37         .set_rate       = &omap3_noncore_dpll_set_rate,
  38         .set_parent     = &omap3_noncore_dpll_set_parent,
  39         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
  40         .determine_rate = &omap4_dpll_regm4xen_determine_rate,
  41         .get_parent     = &omap2_init_dpll_parent,
  42         .save_context   = &omap3_core_dpll_save_context,
  43         .restore_context = &omap3_core_dpll_restore_context,
  44 };
  45 #else
  46 static const struct clk_ops dpll_m4xen_ck_ops = {};
  47 #endif
  48
  49 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
  50         defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \
  51         defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
  52 static const struct clk_ops dpll_core_ck_ops = {
  53         .recalc_rate    = &omap3_dpll_recalc,
  54         .get_parent     = &omap2_init_dpll_parent,
  55 };
  56
  57 static const struct clk_ops dpll_ck_ops = {
  58         .enable         = &omap3_noncore_dpll_enable,
  59         .disable        = &omap3_noncore_dpll_disable,
  60         .recalc_rate    = &omap3_dpll_recalc,
  61         .round_rate     = &omap2_dpll_round_rate,
  62         .set_rate       = &omap3_noncore_dpll_set_rate,
  63         .set_parent     = &omap3_noncore_dpll_set_parent,
  64         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
  65         .determine_rate = &omap3_noncore_dpll_determine_rate,
  66         .get_parent     = &omap2_init_dpll_parent,
  67         .save_context   = &omap3_noncore_dpll_save_context,
  68         .restore_context = &omap3_noncore_dpll_restore_context,
  69 };
  70
  71 static const struct clk_ops dpll_no_gate_ck_ops = {
  72         .recalc_rate    = &omap3_dpll_recalc,
  73         .get_parent     = &omap2_init_dpll_parent,
  74         .round_rate     = &omap2_dpll_round_rate,
  75         .set_rate       = &omap3_noncore_dpll_set_rate,
  76         .set_parent     = &omap3_noncore_dpll_set_parent,
  77         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
  78         .determine_rate = &omap3_noncore_dpll_determine_rate,
  79         .save_context   = &omap3_noncore_dpll_save_context,
  80         .restore_context = &omap3_noncore_dpll_restore_context
  81 };
  82 #else
  83 static const struct clk_ops dpll_core_ck_ops = {};
  84 static const struct clk_ops dpll_ck_ops = {};
  85 static const struct clk_ops dpll_no_gate_ck_ops = {};
  86 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
  87 #endif
  88
  89 #ifdef CONFIG_ARCH_OMAP2
  90 static const struct clk_ops omap2_dpll_core_ck_ops = {
  91         .get_parent     = &omap2_init_dpll_parent,
  92         .recalc_rate    = &omap2_dpllcore_recalc,
  93         .round_rate     = &omap2_dpll_round_rate,
  94         .set_rate       = &omap2_reprogram_dpllcore,
  95 };
  96 #else
  97 static const struct clk_ops omap2_dpll_core_ck_ops = {};
  98 #endif
  99
 100 #ifdef CONFIG_ARCH_OMAP3
 101 static const struct clk_ops omap3_dpll_core_ck_ops = {
 102         .get_parent     = &omap2_init_dpll_parent,
 103         .recalc_rate    = &omap3_dpll_recalc,
 104         .round_rate     = &omap2_dpll_round_rate,
 105 };
 106 #else
 107 static const struct clk_ops omap3_dpll_core_ck_ops = {};
 108 #endif
 109
 110 #ifdef CONFIG_ARCH_OMAP3
 111 static const struct clk_ops omap3_dpll_ck_ops = {
 112         .enable         = &omap3_noncore_dpll_enable,
 113         .disable        = &omap3_noncore_dpll_disable,
 114         .get_parent     = &omap2_init_dpll_parent,
 115         .recalc_rate    = &omap3_dpll_recalc,
 116         .set_rate       = &omap3_noncore_dpll_set_rate,
 117         .set_parent     = &omap3_noncore_dpll_set_parent,
 118         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
 119         .determine_rate = &omap3_noncore_dpll_determine_rate,
 120         .round_rate     = &omap2_dpll_round_rate,
 121 };
 122
 123 static const struct clk_ops omap3_dpll5_ck_ops = {
 124         .enable         = &omap3_noncore_dpll_enable,
 125         .disable        = &omap3_noncore_dpll_disable,
 126         .get_parent     = &omap2_init_dpll_parent,
 127         .recalc_rate    = &omap3_dpll_recalc,
 128         .set_rate       = &omap3_dpll5_set_rate,
 129         .set_parent     = &omap3_noncore_dpll_set_parent,
 130         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
 131         .determine_rate = &omap3_noncore_dpll_determine_rate,
 132         .round_rate     = &omap2_dpll_round_rate,
 133 };
 134
 135 static const struct clk_ops omap3_dpll_per_ck_ops = {
 136         .enable         = &omap3_noncore_dpll_enable,
 137         .disable        = &omap3_noncore_dpll_disable,
 138         .get_parent     = &omap2_init_dpll_parent,
 139         .recalc_rate    = &omap3_dpll_recalc,
 140         .set_rate       = &omap3_dpll4_set_rate,
 141         .set_parent     = &omap3_noncore_dpll_set_parent,
 142         .set_rate_and_parent    = &omap3_dpll4_set_rate_and_parent,
 143         .determine_rate = &omap3_noncore_dpll_determine_rate,
 144         .round_rate     = &omap2_dpll_round_rate,
 145 };
 146 #endif
 147
 148 static const struct clk_ops dpll_x2_ck_ops = {
 149         .recalc_rate    = &omap3_clkoutx2_recalc,
 150 };
 151
 152 /**
 153  * _register_dpll - low level registration of a DPLL clock
 154  * @hw: hardware clock definition for the clock
 155  * @node: device node for the clock
 156  *
 157  * Finalizes DPLL registration process. In case a failure (clk-ref or
 158  * clk-bypass is missing), the clock is added to retry list and
 159  * the initialization is retried on later stage.
 160  */
 161 static void __init _register_dpll(void *user,
 162                                   struct device_node *node)
 163 {
 164         struct clk_hw *hw = user;
 165         struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
 166         struct dpll_data *dd = clk_hw->dpll_data;
 167         struct clk *clk;
 168
 169         clk = of_clk_get(node, 0);
 170         if (IS_ERR(clk)) {
 171                 pr_debug("clk-ref missing for %pOFn, retry later\n",
 172                          node);
 173                 if (!ti_clk_retry_init(node, hw, _register_dpll))
 174                         return;
 175
 176                 goto cleanup;
 177         }
 178
 179         dd->clk_ref = __clk_get_hw(clk);
 180
 181         clk = of_clk_get(node, 1);
 182
 183         if (IS_ERR(clk)) {
 184                 pr_debug("clk-bypass missing for %pOFn, retry later\n",
 185                          node);
 186                 if (!ti_clk_retry_init(node, hw, _register_dpll))
 187                         return;
 188
 189                 goto cleanup;
 190         }
 191
 192         dd->clk_bypass = __clk_get_hw(clk);
 193
 194         /* register the clock */
 195         clk = ti_clk_register(NULL, &clk_hw->hw, node->name);
 196
 197         if (!IS_ERR(clk)) {
 198                 omap2_init_clk_hw_omap_clocks(&clk_hw->hw);
 199                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 200                 kfree(clk_hw->hw.init->parent_names);
 201                 kfree(clk_hw->hw.init);
 202                 return;
 203         }
 204
 205 cleanup:
 206         kfree(clk_hw->dpll_data);
 207         kfree(clk_hw->hw.init->parent_names);
 208         kfree(clk_hw->hw.init);
 209         kfree(clk_hw);
 210 }
 211
 212 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
 213         defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
 214         defined(CONFIG_SOC_AM43XX)
 215 /**
 216  * _register_dpll_x2 - Registers a DPLLx2 clock
 217  * @node: device node for this clock
 218  * @ops: clk_ops for this clock
 219  * @hw_ops: clk_hw_ops for this clock
 220  *
 221  * Initializes a DPLL x 2 clock from device tree data.
 222  */
 223 static void _register_dpll_x2(struct device_node *node,
 224                               const struct clk_ops *ops,
 225                               const struct clk_hw_omap_ops *hw_ops)
 226 {
 227         struct clk *clk;
 228         struct clk_init_data init = { NULL };
 229         struct clk_hw_omap *clk_hw;
 230         const char *name = node->name;
 231         const char *parent_name;
 232
 233         parent_name = of_clk_get_parent_name(node, 0);
 234         if (!parent_name) {
 235                 pr_err("%pOFn must have parent\n", node);
 236                 return;
 237         }
 238
 239         clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
 240         if (!clk_hw)
 241                 return;
 242
 243         clk_hw->ops = hw_ops;
 244         clk_hw->hw.init = &init;
 245
 246         init.name = name;
 247         init.ops = ops;
 248         init.parent_names = &parent_name;
 249         init.num_parents = 1;
 250
 251 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
 252         defined(CONFIG_SOC_DRA7XX)
 253         if (hw_ops == &clkhwops_omap4_dpllmx) {
 254                 int ret;
 255
 256                 /* Check if register defined, if not, drop hw-ops */
 257                 ret = of_property_count_elems_of_size(node, "reg", 1);
 258                 if (ret <= 0) {
 259                         clk_hw->ops = NULL;
 260                 } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) {
 261                         kfree(clk_hw);
 262                         return;
 263                 }
 264         }
 265 #endif
 266
 267         /* register the clock */
 268         clk = ti_clk_register(NULL, &clk_hw->hw, name);
 269
 270         if (IS_ERR(clk)) {
 271                 kfree(clk_hw);
 272         } else {
 273                 omap2_init_clk_hw_omap_clocks(&clk_hw->hw);
 274                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 275         }
 276 }
 277 #endif
 278
 279 /**
 280  * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
 281  * @node: device node containing the DPLL info
 282  * @ops: ops for the DPLL
 283  * @ddt: DPLL data template to use
 284  *
 285  * Initializes a DPLL clock from device tree data.
 286  */
 287 static void __init of_ti_dpll_setup(struct device_node *node,
 288                                     const struct clk_ops *ops,
 289                                     const struct dpll_data *ddt)
 290 {
 291         struct clk_hw_omap *clk_hw = NULL;
 292         struct clk_init_data *init = NULL;
 293         const char **parent_names = NULL;
 294         struct dpll_data *dd = NULL;
 295         u8 dpll_mode = 0;
 296
 297         dd = kzalloc(sizeof(*dd), GFP_KERNEL);
 298         clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
 299         init = kzalloc(sizeof(*init), GFP_KERNEL);
 300         if (!dd || !clk_hw || !init)
 301                 goto cleanup;
 302
 303         memcpy(dd, ddt, sizeof(*dd));
 304
 305         clk_hw->dpll_data = dd;
 306         clk_hw->ops = &clkhwops_omap3_dpll;
 307         clk_hw->hw.init = init;
 308
 309         init->name = node->name;
 310         init->ops = ops;
 311
 312         init->num_parents = of_clk_get_parent_count(node);
 313         if (!init->num_parents) {
 314                 pr_err("%pOFn must have parent(s)\n", node);
 315                 goto cleanup;
 316         }
 317
 318         parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);
 319         if (!parent_names)
 320                 goto cleanup;
 321
 322         of_clk_parent_fill(node, parent_names, init->num_parents);
 323
 324         init->parent_names = parent_names;
 325
 326         if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))
 327                 goto cleanup;
 328
 329         /*
 330          * Special case for OMAP2 DPLL, register order is different due to
 331          * missing idlest_reg, also clkhwops is different. Detected from
 332          * missing idlest_mask.
 333          */
 334         if (!dd->idlest_mask) {
 335                 if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg))
 336                         goto cleanup;
 337 #ifdef CONFIG_ARCH_OMAP2
 338                 clk_hw->ops = &clkhwops_omap2xxx_dpll;
 339                 omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
 340 #endif
 341         } else {
 342                 if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg))
 343                         goto cleanup;
 344
 345                 if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg))
 346                         goto cleanup;
 347         }
 348
 349         if (dd->autoidle_mask) {
 350                 if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg))
 351                         goto cleanup;
 352         }
 353
 354         if (of_property_read_bool(node, "ti,low-power-stop"))
 355                 dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
 356
 357         if (of_property_read_bool(node, "ti,low-power-bypass"))
 358                 dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
 359
 360         if (of_property_read_bool(node, "ti,lock"))
 361                 dpll_mode |= 1 << DPLL_LOCKED;
 362
 363         if (dpll_mode)
 364                 dd->modes = dpll_mode;
 365
 366         _register_dpll(&clk_hw->hw, node);
 367         return;
 368
 369 cleanup:
 370         kfree(dd);
 371         kfree(parent_names);
 372         kfree(init);
 373         kfree(clk_hw);
 374 }
 375
 376 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
 377         defined(CONFIG_SOC_DRA7XX)
 378 static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
 379 {
 380         _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
 381 }
 382 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
 383                of_ti_omap4_dpll_x2_setup);
 384 #endif
 385
 386 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 387 static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
 388 {
 389         _register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
 390 }
 391 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
 392                of_ti_am3_dpll_x2_setup);
 393 #endif
 394
 395 #ifdef CONFIG_ARCH_OMAP3
 396 static void __init of_ti_omap3_dpll_setup(struct device_node *node)
 397 {
 398         const struct dpll_data dd = {
 399                 .idlest_mask = 0x1,
 400                 .enable_mask = 0x7,
 401                 .autoidle_mask = 0x7,
 402                 .mult_mask = 0x7ff << 8,
 403                 .div1_mask = 0x7f,
 404                 .max_multiplier = 2047,
 405                 .max_divider = 128,
 406                 .min_divider = 1,
 407                 .freqsel_mask = 0xf0,
 408                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 409         };
 410
 411         if ((of_machine_is_compatible("ti,omap3630") ||
 412              of_machine_is_compatible("ti,omap36xx")) &&
 413             !strcmp(node->name, "dpll5_ck"))
 414                 of_ti_dpll_setup(node, &omap3_dpll5_ck_ops, &dd);
 415         else
 416                 of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
 417 }
 418 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
 419                of_ti_omap3_dpll_setup);
 420
 421 static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
 422 {
 423         const struct dpll_data dd = {
 424                 .idlest_mask = 0x1,
 425                 .enable_mask = 0x7,
 426                 .autoidle_mask = 0x7,
 427                 .mult_mask = 0x7ff << 16,
 428                 .div1_mask = 0x7f << 8,
 429                 .max_multiplier = 2047,
 430                 .max_divider = 128,
 431                 .min_divider = 1,
 432                 .freqsel_mask = 0xf0,
 433         };
 434
 435         of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
 436 }
 437 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
 438                of_ti_omap3_core_dpll_setup);
 439
 440 static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
 441 {
 442         const struct dpll_data dd = {
 443                 .idlest_mask = 0x1 << 1,
 444                 .enable_mask = 0x7 << 16,
 445                 .autoidle_mask = 0x7 << 3,
 446                 .mult_mask = 0x7ff << 8,
 447                 .div1_mask = 0x7f,
 448                 .max_multiplier = 2047,
 449                 .max_divider = 128,
 450                 .min_divider = 1,
 451                 .freqsel_mask = 0xf00000,
 452                 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 453         };
 454
 455         of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
 456 }
 457 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
 458                of_ti_omap3_per_dpll_setup);
 459
 460 static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
 461 {
 462         const struct dpll_data dd = {
 463                 .idlest_mask = 0x1 << 1,
 464                 .enable_mask = 0x7 << 16,
 465                 .autoidle_mask = 0x7 << 3,
 466                 .mult_mask = 0xfff << 8,
 467                 .div1_mask = 0x7f,
 468                 .max_multiplier = 4095,
 469                 .max_divider = 128,
 470                 .min_divider = 1,
 471                 .sddiv_mask = 0xff << 24,
 472                 .dco_mask = 0xe << 20,
 473                 .flags = DPLL_J_TYPE,
 474                 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 475         };
 476
 477         of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
 478 }
 479 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
 480                of_ti_omap3_per_jtype_dpll_setup);
 481 #endif
 482
 483 static void __init of_ti_omap4_dpll_setup(struct device_node *node)
 484 {
 485         const struct dpll_data dd = {
 486                 .idlest_mask = 0x1,
 487                 .enable_mask = 0x7,
 488                 .autoidle_mask = 0x7,
 489                 .mult_mask = 0x7ff << 8,
 490                 .div1_mask = 0x7f,
 491                 .max_multiplier = 2047,
 492                 .max_divider = 128,
 493                 .min_divider = 1,
 494                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 495         };
 496
 497         of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
 498 }
 499 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
 500                of_ti_omap4_dpll_setup);
 501
 502 static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node)
 503 {
 504         const struct dpll_data dd = {
 505                 .idlest_mask = 0x1,
 506                 .enable_mask = 0x7,
 507                 .autoidle_mask = 0x7,
 508                 .mult_mask = 0x7ff << 8,
 509                 .div1_mask = 0x7f,
 510                 .max_multiplier = 2047,
 511                 .max_divider = 128,
 512                 .dcc_mask = BIT(22),
 513                 .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */
 514                 .min_divider = 1,
 515                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 516         };
 517
 518         of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
 519 }
 520 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
 521                of_ti_omap5_mpu_dpll_setup);
 522
 523 static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
 524 {
 525         const struct dpll_data dd = {
 526                 .idlest_mask = 0x1,
 527                 .enable_mask = 0x7,
 528                 .autoidle_mask = 0x7,
 529                 .mult_mask = 0x7ff << 8,
 530                 .div1_mask = 0x7f,
 531                 .max_multiplier = 2047,
 532                 .max_divider = 128,
 533                 .min_divider = 1,
 534                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 535         };
 536
 537         of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
 538 }
 539 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
 540                of_ti_omap4_core_dpll_setup);
 541
 542 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
 543         defined(CONFIG_SOC_DRA7XX)
 544 static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
 545 {
 546         const struct dpll_data dd = {
 547                 .idlest_mask = 0x1,
 548                 .enable_mask = 0x7,
 549                 .autoidle_mask = 0x7,
 550                 .mult_mask = 0x7ff << 8,
 551                 .div1_mask = 0x7f,
 552                 .max_multiplier = 2047,
 553                 .max_divider = 128,
 554                 .min_divider = 1,
 555                 .m4xen_mask = 0x800,
 556                 .lpmode_mask = 1 << 10,
 557                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 558         };
 559
 560         of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
 561 }
 562 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
 563                of_ti_omap4_m4xen_dpll_setup);
 564
 565 static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
 566 {
 567         const struct dpll_data dd = {
 568                 .idlest_mask = 0x1,
 569                 .enable_mask = 0x7,
 570                 .autoidle_mask = 0x7,
 571                 .mult_mask = 0xfff << 8,
 572                 .div1_mask = 0xff,
 573                 .max_multiplier = 4095,
 574                 .max_divider = 256,
 575                 .min_divider = 1,
 576                 .sddiv_mask = 0xff << 24,
 577                 .flags = DPLL_J_TYPE,
 578                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 579         };
 580
 581         of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
 582 }
 583 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
 584                of_ti_omap4_jtype_dpll_setup);
 585 #endif
 586
 587 static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
 588 {
 589         const struct dpll_data dd = {
 590                 .idlest_mask = 0x1,
 591                 .enable_mask = 0x7,
 592                 .mult_mask = 0x7ff << 8,
 593                 .div1_mask = 0x7f,
 594                 .max_multiplier = 2047,
 595                 .max_divider = 128,
 596                 .min_divider = 1,
 597                 .max_rate = 1000000000,
 598                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 599         };
 600
 601         of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
 602 }
 603 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
 604                of_ti_am3_no_gate_dpll_setup);
 605
 606 static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
 607 {
 608         const struct dpll_data dd = {
 609                 .idlest_mask = 0x1,
 610                 .enable_mask = 0x7,
 611                 .mult_mask = 0x7ff << 8,
 612                 .div1_mask = 0x7f,
 613                 .max_multiplier = 4095,
 614                 .max_divider = 256,
 615                 .min_divider = 2,
 616                 .flags = DPLL_J_TYPE,
 617                 .max_rate = 2000000000,
 618                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 619         };
 620
 621         of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
 622 }
 623 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
 624                of_ti_am3_jtype_dpll_setup);
 625
 626 static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
 627 {
 628         const struct dpll_data dd = {
 629                 .idlest_mask = 0x1,
 630                 .enable_mask = 0x7,
 631                 .mult_mask = 0x7ff << 8,
 632                 .div1_mask = 0x7f,
 633                 .max_multiplier = 2047,
 634                 .max_divider = 128,
 635                 .min_divider = 1,
 636                 .max_rate = 2000000000,
 637                 .flags = DPLL_J_TYPE,
 638                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 639         };
 640
 641         of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
 642 }
 643 CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
 644                "ti,am3-dpll-no-gate-j-type-clock",
 645                of_ti_am3_no_gate_jtype_dpll_setup);
 646
 647 static void __init of_ti_am3_dpll_setup(struct device_node *node)
 648 {
 649         const struct dpll_data dd = {
 650                 .idlest_mask = 0x1,
 651                 .enable_mask = 0x7,
 652                 .mult_mask = 0x7ff << 8,
 653                 .div1_mask = 0x7f,
 654                 .max_multiplier = 2047,
 655                 .max_divider = 128,
 656                 .min_divider = 1,
 657                 .max_rate = 1000000000,
 658                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 659         };
 660
 661         of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
 662 }
 663 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
 664
 665 static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
 666 {
 667         const struct dpll_data dd = {
 668                 .idlest_mask = 0x1,
 669                 .enable_mask = 0x7,
 670                 .mult_mask = 0x7ff << 8,
 671                 .div1_mask = 0x7f,
 672                 .max_multiplier = 2047,
 673                 .max_divider = 128,
 674                 .min_divider = 1,
 675                 .max_rate = 1000000000,
 676                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 677         };
 678
 679         of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
 680 }
 681 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
 682                of_ti_am3_core_dpll_setup);
 683
 684 static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
 685 {
 686         const struct dpll_data dd = {
 687                 .enable_mask = 0x3,
 688                 .mult_mask = 0x3ff << 12,
 689                 .div1_mask = 0xf << 8,
 690                 .max_divider = 16,
 691                 .min_divider = 1,
 692         };
 693
 694         of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
 695 }
 696 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
 697                of_ti_omap2_core_dpll_setup);