2 * OMAP DPLL clock support
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
23 #include <linux/of_address.h>
24 #include <linux/clk/ti.h>
28 #define pr_fmt(fmt) "%s: " fmt, __func__
30 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
31 defined(CONFIG_SOC_DRA7XX)
32 static const struct clk_ops dpll_m4xen_ck_ops = {
33 .enable = &omap3_noncore_dpll_enable,
34 .disable = &omap3_noncore_dpll_disable,
35 .recalc_rate = &omap4_dpll_regm4xen_recalc,
36 .round_rate = &omap4_dpll_regm4xen_round_rate,
37 .set_rate = &omap3_noncore_dpll_set_rate,
38 .set_parent = &omap3_noncore_dpll_set_parent,
39 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
40 .determine_rate = &omap4_dpll_regm4xen_determine_rate,
41 .get_parent = &omap2_init_dpll_parent,
42 .save_context = &omap3_core_dpll_save_context,
43 .restore_context = &omap3_core_dpll_restore_context,
46 static const struct clk_ops dpll_m4xen_ck_ops = {};
49 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
50 defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \
51 defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
52 static const struct clk_ops dpll_core_ck_ops = {
53 .recalc_rate = &omap3_dpll_recalc,
54 .get_parent = &omap2_init_dpll_parent,
57 static const struct clk_ops dpll_ck_ops = {
58 .enable = &omap3_noncore_dpll_enable,
59 .disable = &omap3_noncore_dpll_disable,
60 .recalc_rate = &omap3_dpll_recalc,
61 .round_rate = &omap2_dpll_round_rate,
62 .set_rate = &omap3_noncore_dpll_set_rate,
63 .set_parent = &omap3_noncore_dpll_set_parent,
64 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
65 .determine_rate = &omap3_noncore_dpll_determine_rate,
66 .get_parent = &omap2_init_dpll_parent,
67 .save_context = &omap3_noncore_dpll_save_context,
68 .restore_context = &omap3_noncore_dpll_restore_context,
71 static const struct clk_ops dpll_no_gate_ck_ops = {
72 .recalc_rate = &omap3_dpll_recalc,
73 .get_parent = &omap2_init_dpll_parent,
74 .round_rate = &omap2_dpll_round_rate,
75 .set_rate = &omap3_noncore_dpll_set_rate,
76 .set_parent = &omap3_noncore_dpll_set_parent,
77 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
78 .determine_rate = &omap3_noncore_dpll_determine_rate,
79 .save_context = &omap3_noncore_dpll_save_context,
80 .restore_context = &omap3_noncore_dpll_restore_context
83 static const struct clk_ops dpll_core_ck_ops = {};
84 static const struct clk_ops dpll_ck_ops = {};
85 static const struct clk_ops dpll_no_gate_ck_ops = {};
86 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
89 #ifdef CONFIG_ARCH_OMAP2
90 static const struct clk_ops omap2_dpll_core_ck_ops = {
91 .get_parent = &omap2_init_dpll_parent,
92 .recalc_rate = &omap2_dpllcore_recalc,
93 .round_rate = &omap2_dpll_round_rate,
94 .set_rate = &omap2_reprogram_dpllcore,
97 static const struct clk_ops omap2_dpll_core_ck_ops = {};
100 #ifdef CONFIG_ARCH_OMAP3
101 static const struct clk_ops omap3_dpll_core_ck_ops = {
102 .get_parent = &omap2_init_dpll_parent,
103 .recalc_rate = &omap3_dpll_recalc,
104 .round_rate = &omap2_dpll_round_rate,
107 static const struct clk_ops omap3_dpll_core_ck_ops = {};
110 #ifdef CONFIG_ARCH_OMAP3
111 static const struct clk_ops omap3_dpll_ck_ops = {
112 .enable = &omap3_noncore_dpll_enable,
113 .disable = &omap3_noncore_dpll_disable,
114 .get_parent = &omap2_init_dpll_parent,
115 .recalc_rate = &omap3_dpll_recalc,
116 .set_rate = &omap3_noncore_dpll_set_rate,
117 .set_parent = &omap3_noncore_dpll_set_parent,
118 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
119 .determine_rate = &omap3_noncore_dpll_determine_rate,
120 .round_rate = &omap2_dpll_round_rate,
123 static const struct clk_ops omap3_dpll5_ck_ops = {
124 .enable = &omap3_noncore_dpll_enable,
125 .disable = &omap3_noncore_dpll_disable,
126 .get_parent = &omap2_init_dpll_parent,
127 .recalc_rate = &omap3_dpll_recalc,
128 .set_rate = &omap3_dpll5_set_rate,
129 .set_parent = &omap3_noncore_dpll_set_parent,
130 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
131 .determine_rate = &omap3_noncore_dpll_determine_rate,
132 .round_rate = &omap2_dpll_round_rate,
135 static const struct clk_ops omap3_dpll_per_ck_ops = {
136 .enable = &omap3_noncore_dpll_enable,
137 .disable = &omap3_noncore_dpll_disable,
138 .get_parent = &omap2_init_dpll_parent,
139 .recalc_rate = &omap3_dpll_recalc,
140 .set_rate = &omap3_dpll4_set_rate,
141 .set_parent = &omap3_noncore_dpll_set_parent,
142 .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent,
143 .determine_rate = &omap3_noncore_dpll_determine_rate,
144 .round_rate = &omap2_dpll_round_rate,
148 static const struct clk_ops dpll_x2_ck_ops = {
149 .recalc_rate = &omap3_clkoutx2_recalc,
153 * _register_dpll - low level registration of a DPLL clock
154 * @hw: hardware clock definition for the clock
155 * @node: device node for the clock
157 * Finalizes DPLL registration process. In case a failure (clk-ref or
158 * clk-bypass is missing), the clock is added to retry list and
159 * the initialization is retried on later stage.
161 static void __init _register_dpll(void *user,
162 struct device_node *node)
164 struct clk_hw *hw = user;
165 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
166 struct dpll_data *dd = clk_hw->dpll_data;
169 clk = of_clk_get(node, 0);
171 pr_debug("clk-ref missing for %pOFn, retry later\n",
173 if (!ti_clk_retry_init(node, hw, _register_dpll))
179 dd->clk_ref = __clk_get_hw(clk);
181 clk = of_clk_get(node, 1);
184 pr_debug("clk-bypass missing for %pOFn, retry later\n",
186 if (!ti_clk_retry_init(node, hw, _register_dpll))
192 dd->clk_bypass = __clk_get_hw(clk);
194 /* register the clock */
195 clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name);
198 of_clk_add_provider(node, of_clk_src_simple_get, clk);
199 kfree(clk_hw->hw.init->parent_names);
200 kfree(clk_hw->hw.init);
205 kfree(clk_hw->dpll_data);
206 kfree(clk_hw->hw.init->parent_names);
207 kfree(clk_hw->hw.init);
211 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
212 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
213 defined(CONFIG_SOC_AM43XX)
215 * _register_dpll_x2 - Registers a DPLLx2 clock
216 * @node: device node for this clock
217 * @ops: clk_ops for this clock
218 * @hw_ops: clk_hw_ops for this clock
220 * Initializes a DPLL x 2 clock from device tree data.
222 static void _register_dpll_x2(struct device_node *node,
223 const struct clk_ops *ops,
224 const struct clk_hw_omap_ops *hw_ops)
227 struct clk_init_data init = { NULL };
228 struct clk_hw_omap *clk_hw;
229 const char *name = node->name;
230 const char *parent_name;
232 parent_name = of_clk_get_parent_name(node, 0);
234 pr_err("%pOFn must have parent\n", node);
238 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
242 clk_hw->ops = hw_ops;
243 clk_hw->hw.init = &init;
247 init.parent_names = &parent_name;
248 init.num_parents = 1;
250 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
251 defined(CONFIG_SOC_DRA7XX)
252 if (hw_ops == &clkhwops_omap4_dpllmx) {
255 /* Check if register defined, if not, drop hw-ops */
256 ret = of_property_count_elems_of_size(node, "reg", 1);
259 } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) {
266 /* register the clock */
267 clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
272 of_clk_add_provider(node, of_clk_src_simple_get, clk);
277 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
278 * @node: device node containing the DPLL info
279 * @ops: ops for the DPLL
280 * @ddt: DPLL data template to use
282 * Initializes a DPLL clock from device tree data.
284 static void __init of_ti_dpll_setup(struct device_node *node,
285 const struct clk_ops *ops,
286 const struct dpll_data *ddt)
288 struct clk_hw_omap *clk_hw = NULL;
289 struct clk_init_data *init = NULL;
290 const char **parent_names = NULL;
291 struct dpll_data *dd = NULL;
294 dd = kzalloc(sizeof(*dd), GFP_KERNEL);
295 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
296 init = kzalloc(sizeof(*init), GFP_KERNEL);
297 if (!dd || !clk_hw || !init)
300 memcpy(dd, ddt, sizeof(*dd));
302 clk_hw->dpll_data = dd;
303 clk_hw->ops = &clkhwops_omap3_dpll;
304 clk_hw->hw.init = init;
306 init->name = node->name;
309 init->num_parents = of_clk_get_parent_count(node);
310 if (!init->num_parents) {
311 pr_err("%pOFn must have parent(s)\n", node);
315 parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);
319 of_clk_parent_fill(node, parent_names, init->num_parents);
321 init->parent_names = parent_names;
323 if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))
327 * Special case for OMAP2 DPLL, register order is different due to
328 * missing idlest_reg, also clkhwops is different. Detected from
329 * missing idlest_mask.
331 if (!dd->idlest_mask) {
332 if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg))
334 #ifdef CONFIG_ARCH_OMAP2
335 clk_hw->ops = &clkhwops_omap2xxx_dpll;
336 omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
339 if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg))
342 if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg))
346 if (dd->autoidle_mask) {
347 if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg))
351 if (of_property_read_bool(node, "ti,low-power-stop"))
352 dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
354 if (of_property_read_bool(node, "ti,low-power-bypass"))
355 dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
357 if (of_property_read_bool(node, "ti,lock"))
358 dpll_mode |= 1 << DPLL_LOCKED;
361 dd->modes = dpll_mode;
363 _register_dpll(&clk_hw->hw, node);
373 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
374 defined(CONFIG_SOC_DRA7XX)
375 static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
377 _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
379 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
380 of_ti_omap4_dpll_x2_setup);
383 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
384 static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
386 _register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
388 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
389 of_ti_am3_dpll_x2_setup);
392 #ifdef CONFIG_ARCH_OMAP3
393 static void __init of_ti_omap3_dpll_setup(struct device_node *node)
395 const struct dpll_data dd = {
398 .autoidle_mask = 0x7,
399 .mult_mask = 0x7ff << 8,
401 .max_multiplier = 2047,
404 .freqsel_mask = 0xf0,
405 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
408 if ((of_machine_is_compatible("ti,omap3630") ||
409 of_machine_is_compatible("ti,omap36xx")) &&
410 of_node_name_eq(node, "dpll5_ck"))
411 of_ti_dpll_setup(node, &omap3_dpll5_ck_ops, &dd);
413 of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
415 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
416 of_ti_omap3_dpll_setup);
418 static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
420 const struct dpll_data dd = {
423 .autoidle_mask = 0x7,
424 .mult_mask = 0x7ff << 16,
425 .div1_mask = 0x7f << 8,
426 .max_multiplier = 2047,
429 .freqsel_mask = 0xf0,
432 of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
434 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
435 of_ti_omap3_core_dpll_setup);
437 static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
439 const struct dpll_data dd = {
440 .idlest_mask = 0x1 << 1,
441 .enable_mask = 0x7 << 16,
442 .autoidle_mask = 0x7 << 3,
443 .mult_mask = 0x7ff << 8,
445 .max_multiplier = 2047,
448 .freqsel_mask = 0xf00000,
449 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
452 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
454 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
455 of_ti_omap3_per_dpll_setup);
457 static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
459 const struct dpll_data dd = {
460 .idlest_mask = 0x1 << 1,
461 .enable_mask = 0x7 << 16,
462 .autoidle_mask = 0x7 << 3,
463 .mult_mask = 0xfff << 8,
465 .max_multiplier = 4095,
468 .sddiv_mask = 0xff << 24,
469 .dco_mask = 0xe << 20,
470 .flags = DPLL_J_TYPE,
471 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
474 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
476 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
477 of_ti_omap3_per_jtype_dpll_setup);
480 static void __init of_ti_omap4_dpll_setup(struct device_node *node)
482 const struct dpll_data dd = {
485 .autoidle_mask = 0x7,
486 .mult_mask = 0x7ff << 8,
488 .max_multiplier = 2047,
491 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
494 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
496 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
497 of_ti_omap4_dpll_setup);
499 static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node)
501 const struct dpll_data dd = {
504 .autoidle_mask = 0x7,
505 .mult_mask = 0x7ff << 8,
507 .max_multiplier = 2047,
510 .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */
512 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
515 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
517 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
518 of_ti_omap5_mpu_dpll_setup);
520 static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
522 const struct dpll_data dd = {
525 .autoidle_mask = 0x7,
526 .mult_mask = 0x7ff << 8,
528 .max_multiplier = 2047,
531 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
534 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
536 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
537 of_ti_omap4_core_dpll_setup);
539 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
540 defined(CONFIG_SOC_DRA7XX)
541 static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
543 const struct dpll_data dd = {
546 .autoidle_mask = 0x7,
547 .mult_mask = 0x7ff << 8,
549 .max_multiplier = 2047,
553 .lpmode_mask = 1 << 10,
554 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
557 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
559 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
560 of_ti_omap4_m4xen_dpll_setup);
562 static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
564 const struct dpll_data dd = {
567 .autoidle_mask = 0x7,
568 .mult_mask = 0xfff << 8,
570 .max_multiplier = 4095,
573 .sddiv_mask = 0xff << 24,
574 .flags = DPLL_J_TYPE,
575 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
578 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
580 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
581 of_ti_omap4_jtype_dpll_setup);
584 static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
586 const struct dpll_data dd = {
589 .mult_mask = 0x7ff << 8,
591 .max_multiplier = 2047,
594 .max_rate = 1000000000,
595 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
598 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
600 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
601 of_ti_am3_no_gate_dpll_setup);
603 static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
605 const struct dpll_data dd = {
608 .mult_mask = 0x7ff << 8,
610 .max_multiplier = 4095,
613 .flags = DPLL_J_TYPE,
614 .max_rate = 2000000000,
615 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
618 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
620 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
621 of_ti_am3_jtype_dpll_setup);
623 static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
625 const struct dpll_data dd = {
628 .mult_mask = 0x7ff << 8,
630 .max_multiplier = 2047,
633 .max_rate = 2000000000,
634 .flags = DPLL_J_TYPE,
635 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
638 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
640 CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
641 "ti,am3-dpll-no-gate-j-type-clock",
642 of_ti_am3_no_gate_jtype_dpll_setup);
644 static void __init of_ti_am3_dpll_setup(struct device_node *node)
646 const struct dpll_data dd = {
649 .mult_mask = 0x7ff << 8,
651 .max_multiplier = 2047,
654 .max_rate = 1000000000,
655 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
658 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
660 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
662 static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
664 const struct dpll_data dd = {
667 .mult_mask = 0x7ff << 8,
669 .max_multiplier = 2047,
672 .max_rate = 1000000000,
673 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
676 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
678 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
679 of_ti_am3_core_dpll_setup);
681 static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
683 const struct dpll_data dd = {
685 .mult_mask = 0x3ff << 12,
686 .div1_mask = 0xf << 8,
691 of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
693 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
694 of_ti_omap2_core_dpll_setup);