1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk-provider.h>
9 #include <linux/of_address.h>
10 #include <linux/delay.h>
11 #include <linux/export.h>
12 #include <linux/clk/tegra.h>
18 #define OSC_CTRL_OSC_FREQ_SHIFT 28
19 #define OSC_CTRL_PLL_REF_DIV_SHIFT 26
20 #define OSC_CTRL_MASK (0x3f2 | \
21 (0xf << OSC_CTRL_OSC_FREQ_SHIFT))
23 static u32 osc_ctrl_ctx;
25 int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
26 unsigned long *input_freqs, unsigned int num,
27 unsigned int clk_m_div, unsigned long *osc_freq,
28 unsigned long *pll_ref_freq)
30 struct clk *clk, *osc;
35 val = readl_relaxed(clk_base + OSC_CTRL);
36 osc_ctrl_ctx = val & OSC_CTRL_MASK;
37 osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
40 *osc_freq = input_freqs[osc_idx];
49 osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
51 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
55 clk = clk_register_fixed_factor(NULL, "clk_m", "osc",
60 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
61 pll_ref_div = 1 << val;
62 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, clks);
66 clk = clk_register_fixed_factor(NULL, "pll_ref", "osc",
71 *pll_ref_freq = *osc_freq / pll_ref_div;
76 void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
82 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks);
84 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
89 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);
91 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
92 CLK_SET_RATE_PARENT, 1, 2);
97 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);
99 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
100 CLK_SET_RATE_PARENT, 1, 4);
105 void tegra_clk_osc_resume(void __iomem *clk_base)
109 val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK;
111 writel_relaxed(val, clk_base + OSC_CTRL);
112 fence_udelay(2, clk_base);