2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/slab.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/clk-provider.h>
22 #include <linux/clk.h>
26 #define PLL_BASE_BYPASS BIT(31)
27 #define PLL_BASE_ENABLE BIT(30)
28 #define PLL_BASE_REF_ENABLE BIT(29)
29 #define PLL_BASE_OVERRIDE BIT(28)
31 #define PLL_BASE_DIVP_SHIFT 20
32 #define PLL_BASE_DIVP_WIDTH 3
33 #define PLL_BASE_DIVN_SHIFT 8
34 #define PLL_BASE_DIVN_WIDTH 10
35 #define PLL_BASE_DIVM_SHIFT 0
36 #define PLL_BASE_DIVM_WIDTH 5
37 #define PLLU_POST_DIVP_MASK 0x1
39 #define PLL_MISC_DCCON_SHIFT 20
40 #define PLL_MISC_CPCON_SHIFT 8
41 #define PLL_MISC_CPCON_WIDTH 4
42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
43 #define PLL_MISC_LFCON_SHIFT 4
44 #define PLL_MISC_LFCON_WIDTH 4
45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
46 #define PLL_MISC_VCOCON_SHIFT 0
47 #define PLL_MISC_VCOCON_WIDTH 4
48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
50 #define OUT_OF_TABLE_CPCON 8
52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
56 #define PLL_POST_LOCK_DELAY 50
58 #define PLLDU_LFCON_SET_DIVN 600
60 #define PLLE_BASE_DIVCML_SHIFT 24
61 #define PLLE_BASE_DIVCML_MASK 0xf
62 #define PLLE_BASE_DIVP_SHIFT 16
63 #define PLLE_BASE_DIVP_WIDTH 6
64 #define PLLE_BASE_DIVN_SHIFT 8
65 #define PLLE_BASE_DIVN_WIDTH 8
66 #define PLLE_BASE_DIVM_SHIFT 0
67 #define PLLE_BASE_DIVM_WIDTH 8
69 #define PLLE_MISC_SETUP_BASE_SHIFT 16
70 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
71 #define PLLE_MISC_LOCK_ENABLE BIT(9)
72 #define PLLE_MISC_READY BIT(15)
73 #define PLLE_MISC_SETUP_EX_SHIFT 2
74 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
75 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
76 PLLE_MISC_SETUP_EX_MASK)
77 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
79 #define PLLE_SS_CTRL 0x68
80 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
81 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
82 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
83 #define PLLE_SS_CNTL_CENTER BIT(14)
84 #define PLLE_SS_CNTL_INVERT BIT(15)
85 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
87 #define PLLE_SS_MAX_MASK 0x1ff
88 #define PLLE_SS_MAX_VAL 0x25
89 #define PLLE_SS_INC_MASK (0xff << 16)
90 #define PLLE_SS_INC_VAL (0x1 << 16)
91 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
92 #define PLLE_SS_INCINTRV_VAL (0x20 << 24)
93 #define PLLE_SS_COEFFICIENTS_MASK \
94 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
95 #define PLLE_SS_COEFFICIENTS_VAL \
96 (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)
98 #define PLLE_AUX_PLLP_SEL BIT(2)
99 #define PLLE_AUX_USE_LOCKDET BIT(3)
100 #define PLLE_AUX_ENABLE_SWCTL BIT(4)
101 #define PLLE_AUX_SS_SWCTL BIT(6)
102 #define PLLE_AUX_SEQ_ENABLE BIT(24)
103 #define PLLE_AUX_SEQ_START_STATE BIT(25)
104 #define PLLE_AUX_PLLRE_SEL BIT(28)
106 #define XUSBIO_PLL_CFG0 0x51c
107 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
108 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
109 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
110 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
111 #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25)
113 #define SATA_PLL_CFG0 0x490
114 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
115 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
116 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
117 #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25)
119 #define PLLE_MISC_PLLE_PTS BIT(8)
120 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
121 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
122 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
123 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
124 #define PLLE_MISC_VREG_CTRL_SHIFT 2
125 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
127 #define PLLCX_MISC_STROBE BIT(31)
128 #define PLLCX_MISC_RESET BIT(30)
129 #define PLLCX_MISC_SDM_DIV_SHIFT 28
130 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
131 #define PLLCX_MISC_FILT_DIV_SHIFT 26
132 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
133 #define PLLCX_MISC_ALPHA_SHIFT 18
134 #define PLLCX_MISC_DIV_LOW_RANGE \
135 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
136 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
137 #define PLLCX_MISC_DIV_HIGH_RANGE \
138 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
139 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
140 #define PLLCX_MISC_COEF_LOW_RANGE \
141 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
142 #define PLLCX_MISC_KA_SHIFT 2
143 #define PLLCX_MISC_KB_SHIFT 9
144 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
145 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
146 PLLCX_MISC_DIV_LOW_RANGE | \
148 #define PLLCX_MISC1_DEFAULT 0x000d2308
149 #define PLLCX_MISC2_DEFAULT 0x30211200
150 #define PLLCX_MISC3_DEFAULT 0x200
152 #define PMC_SATA_PWRGT 0x1ac
153 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
154 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
156 #define PLLSS_MISC_KCP 0
157 #define PLLSS_MISC_KVCO 0
158 #define PLLSS_MISC_SETUP 0
159 #define PLLSS_EN_SDM 0
160 #define PLLSS_EN_SSC 0
161 #define PLLSS_EN_DITHER2 0
162 #define PLLSS_EN_DITHER 1
163 #define PLLSS_SDM_RESET 0
164 #define PLLSS_CLAMP 0
165 #define PLLSS_SDM_SSC_MAX 0
166 #define PLLSS_SDM_SSC_MIN 0
167 #define PLLSS_SDM_SSC_STEP 0
168 #define PLLSS_SDM_DIN 0
169 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
170 (PLLSS_MISC_KVCO << 24) | \
172 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
173 (PLLSS_EN_SSC << 30) | \
174 (PLLSS_EN_DITHER2 << 29) | \
175 (PLLSS_EN_DITHER << 28) | \
176 (PLLSS_SDM_RESET) << 27 | \
178 #define PLLSS_CTRL1_DEFAULT \
179 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
180 #define PLLSS_CTRL2_DEFAULT \
181 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
182 #define PLLSS_LOCK_OVERRIDE BIT(24)
183 #define PLLSS_REF_SRC_SEL_SHIFT 25
184 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT)
186 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
187 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
188 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
189 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
191 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
192 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
193 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
194 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
196 #define mask(w) ((1 << (w)) - 1)
197 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
198 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
199 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
200 mask(p->params->div_nmp->divp_width))
202 #define divm_shift(p) (p)->params->div_nmp->divm_shift
203 #define divn_shift(p) (p)->params->div_nmp->divn_shift
204 #define divp_shift(p) (p)->params->div_nmp->divp_shift
206 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
207 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
208 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
210 #define divm_max(p) (divm_mask(p))
211 #define divn_max(p) (divn_mask(p))
212 #define divp_max(p) (1 << (divp_mask(p)))
214 static struct div_nmp default_nmp = {
215 .divn_shift = PLL_BASE_DIVN_SHIFT,
216 .divn_width = PLL_BASE_DIVN_WIDTH,
217 .divm_shift = PLL_BASE_DIVM_SHIFT,
218 .divm_width = PLL_BASE_DIVM_WIDTH,
219 .divp_shift = PLL_BASE_DIVP_SHIFT,
220 .divp_width = PLL_BASE_DIVP_WIDTH,
223 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
227 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
230 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
233 val = pll_readl_misc(pll);
234 val |= BIT(pll->params->lock_enable_bit_idx);
235 pll_writel_misc(val, pll);
238 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
242 void __iomem *lock_addr;
244 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
245 udelay(pll->params->lock_delay);
249 lock_addr = pll->clk_base;
250 if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
251 lock_addr += pll->params->misc_reg;
253 lock_addr += pll->params->base_reg;
255 lock_mask = pll->params->lock_mask;
257 for (i = 0; i < pll->params->lock_delay; i++) {
258 val = readl_relaxed(lock_addr);
259 if ((val & lock_mask) == lock_mask) {
260 udelay(PLL_POST_LOCK_DELAY);
263 udelay(2); /* timeout = 2 * lock time */
266 pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
267 __clk_get_name(pll->hw.clk));
272 static int clk_pll_is_enabled(struct clk_hw *hw)
274 struct tegra_clk_pll *pll = to_clk_pll(hw);
277 if (pll->params->flags & TEGRA_PLLM) {
278 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
279 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
280 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
283 val = pll_readl_base(pll);
285 return val & PLL_BASE_ENABLE ? 1 : 0;
288 static void _clk_pll_enable(struct clk_hw *hw)
290 struct tegra_clk_pll *pll = to_clk_pll(hw);
293 clk_pll_enable_lock(pll);
295 val = pll_readl_base(pll);
296 if (pll->params->flags & TEGRA_PLL_BYPASS)
297 val &= ~PLL_BASE_BYPASS;
298 val |= PLL_BASE_ENABLE;
299 pll_writel_base(val, pll);
301 if (pll->params->flags & TEGRA_PLLM) {
302 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
303 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
304 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
308 static void _clk_pll_disable(struct clk_hw *hw)
310 struct tegra_clk_pll *pll = to_clk_pll(hw);
313 val = pll_readl_base(pll);
314 if (pll->params->flags & TEGRA_PLL_BYPASS)
315 val &= ~PLL_BASE_BYPASS;
316 val &= ~PLL_BASE_ENABLE;
317 pll_writel_base(val, pll);
319 if (pll->params->flags & TEGRA_PLLM) {
320 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
321 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
322 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
326 static int clk_pll_enable(struct clk_hw *hw)
328 struct tegra_clk_pll *pll = to_clk_pll(hw);
329 unsigned long flags = 0;
333 spin_lock_irqsave(pll->lock, flags);
337 ret = clk_pll_wait_for_lock(pll);
340 spin_unlock_irqrestore(pll->lock, flags);
345 static void clk_pll_disable(struct clk_hw *hw)
347 struct tegra_clk_pll *pll = to_clk_pll(hw);
348 unsigned long flags = 0;
351 spin_lock_irqsave(pll->lock, flags);
353 _clk_pll_disable(hw);
356 spin_unlock_irqrestore(pll->lock, flags);
359 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
361 struct tegra_clk_pll *pll = to_clk_pll(hw);
362 struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
365 while (p_tohw->pdiv) {
366 if (p_div <= p_tohw->pdiv)
367 return p_tohw->hw_val;
375 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
377 struct tegra_clk_pll *pll = to_clk_pll(hw);
378 struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
381 while (p_tohw->pdiv) {
382 if (p_div_hw == p_tohw->hw_val)
389 return 1 << p_div_hw;
392 static int _get_table_rate(struct clk_hw *hw,
393 struct tegra_clk_pll_freq_table *cfg,
394 unsigned long rate, unsigned long parent_rate)
396 struct tegra_clk_pll *pll = to_clk_pll(hw);
397 struct tegra_clk_pll_freq_table *sel;
399 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
400 if (sel->input_rate == parent_rate &&
401 sel->output_rate == rate)
404 if (sel->input_rate == 0)
407 cfg->input_rate = sel->input_rate;
408 cfg->output_rate = sel->output_rate;
412 cfg->cpcon = sel->cpcon;
417 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
418 unsigned long rate, unsigned long parent_rate)
420 struct tegra_clk_pll *pll = to_clk_pll(hw);
425 switch (parent_rate) {
428 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
431 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
435 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
440 * PLL_P_OUT1 rate is not listed in PLLA table
442 cfreq = parent_rate/(parent_rate/1000000);
445 pr_err("%s Unexpected reference rate %lu\n",
446 __func__, parent_rate);
450 /* Raise VCO to guarantee 0.5% accuracy */
451 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
452 cfg->output_rate <<= 1)
455 cfg->m = parent_rate / cfreq;
456 cfg->n = cfg->output_rate / cfreq;
457 cfg->cpcon = OUT_OF_TABLE_CPCON;
459 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
460 (1 << p_div) > divp_max(pll)
461 || cfg->output_rate > pll->params->vco_max) {
465 cfg->output_rate >>= p_div;
467 if (pll->params->pdiv_tohw) {
468 ret = _p_div_to_hw(hw, 1 << p_div);
479 static void _update_pll_mnp(struct tegra_clk_pll *pll,
480 struct tegra_clk_pll_freq_table *cfg)
483 struct tegra_clk_pll_params *params = pll->params;
484 struct div_nmp *div_nmp = params->div_nmp;
486 if ((params->flags & TEGRA_PLLM) &&
487 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
488 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
489 val = pll_override_readl(params->pmc_divp_reg, pll);
490 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
491 val |= cfg->p << div_nmp->override_divp_shift;
492 pll_override_writel(val, params->pmc_divp_reg, pll);
494 val = pll_override_readl(params->pmc_divnm_reg, pll);
495 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |
496 ~(divn_mask(pll) << div_nmp->override_divn_shift);
497 val |= (cfg->m << div_nmp->override_divm_shift) |
498 (cfg->n << div_nmp->override_divn_shift);
499 pll_override_writel(val, params->pmc_divnm_reg, pll);
501 val = pll_readl_base(pll);
503 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
504 divp_mask_shifted(pll));
506 val |= (cfg->m << divm_shift(pll)) |
507 (cfg->n << divn_shift(pll)) |
508 (cfg->p << divp_shift(pll));
510 pll_writel_base(val, pll);
514 static void _get_pll_mnp(struct tegra_clk_pll *pll,
515 struct tegra_clk_pll_freq_table *cfg)
518 struct tegra_clk_pll_params *params = pll->params;
519 struct div_nmp *div_nmp = params->div_nmp;
521 if ((params->flags & TEGRA_PLLM) &&
522 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
523 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
524 val = pll_override_readl(params->pmc_divp_reg, pll);
525 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
527 val = pll_override_readl(params->pmc_divnm_reg, pll);
528 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
529 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
531 val = pll_readl_base(pll);
533 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
534 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
535 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
539 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
540 struct tegra_clk_pll_freq_table *cfg,
545 val = pll_readl_misc(pll);
547 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
548 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
550 if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
551 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
552 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
553 val |= 1 << PLL_MISC_LFCON_SHIFT;
554 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
555 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
556 if (rate >= (pll->params->vco_max >> 1))
557 val |= 1 << PLL_MISC_DCCON_SHIFT;
560 pll_writel_misc(val, pll);
563 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
566 struct tegra_clk_pll *pll = to_clk_pll(hw);
569 state = clk_pll_is_enabled(hw);
572 _clk_pll_disable(hw);
574 _update_pll_mnp(pll, cfg);
576 if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
577 _update_pll_cpcon(pll, cfg, rate);
581 ret = clk_pll_wait_for_lock(pll);
587 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
588 unsigned long parent_rate)
590 struct tegra_clk_pll *pll = to_clk_pll(hw);
591 struct tegra_clk_pll_freq_table cfg, old_cfg;
592 unsigned long flags = 0;
595 if (pll->params->flags & TEGRA_PLL_FIXED) {
596 if (rate != pll->params->fixed_rate) {
597 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
598 __func__, __clk_get_name(hw->clk),
599 pll->params->fixed_rate, rate);
605 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
606 _calc_rate(hw, &cfg, rate, parent_rate)) {
607 pr_err("%s: Failed to set %s rate %lu\n", __func__,
608 __clk_get_name(hw->clk), rate);
613 spin_lock_irqsave(pll->lock, flags);
615 _get_pll_mnp(pll, &old_cfg);
617 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
618 ret = _program_pll(hw, &cfg, rate);
621 spin_unlock_irqrestore(pll->lock, flags);
626 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
627 unsigned long *prate)
629 struct tegra_clk_pll *pll = to_clk_pll(hw);
630 struct tegra_clk_pll_freq_table cfg;
632 if (pll->params->flags & TEGRA_PLL_FIXED)
633 return pll->params->fixed_rate;
635 /* PLLM is used for memory; we do not change rate */
636 if (pll->params->flags & TEGRA_PLLM)
637 return __clk_get_rate(hw->clk);
639 if (_get_table_rate(hw, &cfg, rate, *prate) &&
640 _calc_rate(hw, &cfg, rate, *prate))
643 return cfg.output_rate;
646 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
647 unsigned long parent_rate)
649 struct tegra_clk_pll *pll = to_clk_pll(hw);
650 struct tegra_clk_pll_freq_table cfg;
652 u64 rate = parent_rate;
655 val = pll_readl_base(pll);
657 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
660 if ((pll->params->flags & TEGRA_PLL_FIXED) &&
661 !(val & PLL_BASE_OVERRIDE)) {
662 struct tegra_clk_pll_freq_table sel;
663 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
665 pr_err("Clock %s has unknown fixed frequency\n",
666 __clk_get_name(hw->clk));
669 return pll->params->fixed_rate;
672 _get_pll_mnp(pll, &cfg);
674 pdiv = _hw_to_p_div(hw, cfg.p);
688 static int clk_plle_training(struct tegra_clk_pll *pll)
691 unsigned long timeout;
697 * PLLE is already disabled, and setup cleared;
698 * create falling edge on PLLE IDDQ input.
700 val = readl(pll->pmc + PMC_SATA_PWRGT);
701 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
702 writel(val, pll->pmc + PMC_SATA_PWRGT);
704 val = readl(pll->pmc + PMC_SATA_PWRGT);
705 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
706 writel(val, pll->pmc + PMC_SATA_PWRGT);
708 val = readl(pll->pmc + PMC_SATA_PWRGT);
709 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
710 writel(val, pll->pmc + PMC_SATA_PWRGT);
712 val = pll_readl_misc(pll);
714 timeout = jiffies + msecs_to_jiffies(100);
716 val = pll_readl_misc(pll);
717 if (val & PLLE_MISC_READY)
719 if (time_after(jiffies, timeout)) {
720 pr_err("%s: timeout waiting for PLLE\n", __func__);
729 static int clk_plle_enable(struct clk_hw *hw)
731 struct tegra_clk_pll *pll = to_clk_pll(hw);
732 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
733 struct tegra_clk_pll_freq_table sel;
737 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
742 val = pll_readl_misc(pll);
743 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
744 pll_writel_misc(val, pll);
746 val = pll_readl_misc(pll);
747 if (!(val & PLLE_MISC_READY)) {
748 err = clk_plle_training(pll);
753 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
754 /* configure dividers */
755 val = pll_readl_base(pll);
756 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
757 divm_mask_shifted(pll));
758 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
759 val |= sel.m << divm_shift(pll);
760 val |= sel.n << divn_shift(pll);
761 val |= sel.p << divp_shift(pll);
762 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
763 pll_writel_base(val, pll);
766 val = pll_readl_misc(pll);
767 val |= PLLE_MISC_SETUP_VALUE;
768 val |= PLLE_MISC_LOCK_ENABLE;
769 pll_writel_misc(val, pll);
771 val = readl(pll->clk_base + PLLE_SS_CTRL);
772 val &= ~PLLE_SS_COEFFICIENTS_MASK;
773 val |= PLLE_SS_DISABLE;
774 writel(val, pll->clk_base + PLLE_SS_CTRL);
776 val = pll_readl_base(pll);
777 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
778 pll_writel_base(val, pll);
780 clk_pll_wait_for_lock(pll);
785 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
786 unsigned long parent_rate)
788 struct tegra_clk_pll *pll = to_clk_pll(hw);
789 u32 val = pll_readl_base(pll);
790 u32 divn = 0, divm = 0, divp = 0;
791 u64 rate = parent_rate;
793 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
794 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
795 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
803 const struct clk_ops tegra_clk_pll_ops = {
804 .is_enabled = clk_pll_is_enabled,
805 .enable = clk_pll_enable,
806 .disable = clk_pll_disable,
807 .recalc_rate = clk_pll_recalc_rate,
808 .round_rate = clk_pll_round_rate,
809 .set_rate = clk_pll_set_rate,
812 const struct clk_ops tegra_clk_plle_ops = {
813 .recalc_rate = clk_plle_recalc_rate,
814 .is_enabled = clk_pll_is_enabled,
815 .disable = clk_pll_disable,
816 .enable = clk_plle_enable,
819 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
820 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
821 defined(CONFIG_ARCH_TEGRA_132_SOC)
823 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
824 unsigned long parent_rate)
826 if (parent_rate > pll_params->cf_max)
832 static unsigned long _clip_vco_min(unsigned long vco_min,
833 unsigned long parent_rate)
835 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
838 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
839 void __iomem *clk_base,
840 unsigned long parent_rate)
845 switch (parent_rate) {
861 pr_err("%s: Unexpected reference rate %lu\n",
862 __func__, parent_rate);
867 val = step_a << pll_params->stepa_shift;
868 val |= step_b << pll_params->stepb_shift;
869 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
874 static int clk_pll_iddq_enable(struct clk_hw *hw)
876 struct tegra_clk_pll *pll = to_clk_pll(hw);
877 unsigned long flags = 0;
883 spin_lock_irqsave(pll->lock, flags);
885 val = pll_readl(pll->params->iddq_reg, pll);
886 val &= ~BIT(pll->params->iddq_bit_idx);
887 pll_writel(val, pll->params->iddq_reg, pll);
892 ret = clk_pll_wait_for_lock(pll);
895 spin_unlock_irqrestore(pll->lock, flags);
900 static void clk_pll_iddq_disable(struct clk_hw *hw)
902 struct tegra_clk_pll *pll = to_clk_pll(hw);
903 unsigned long flags = 0;
907 spin_lock_irqsave(pll->lock, flags);
909 _clk_pll_disable(hw);
911 val = pll_readl(pll->params->iddq_reg, pll);
912 val |= BIT(pll->params->iddq_bit_idx);
913 pll_writel(val, pll->params->iddq_reg, pll);
917 spin_unlock_irqrestore(pll->lock, flags);
920 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
921 struct tegra_clk_pll_freq_table *cfg,
922 unsigned long rate, unsigned long parent_rate)
924 struct tegra_clk_pll *pll = to_clk_pll(hw);
931 p = DIV_ROUND_UP(pll->params->vco_min, rate);
932 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
933 cfg->output_rate = rate * p;
934 cfg->n = cfg->output_rate * cfg->m / parent_rate;
936 p_div = _p_div_to_hw(hw, p);
942 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
948 static int _pll_ramp_calc_pll(struct clk_hw *hw,
949 struct tegra_clk_pll_freq_table *cfg,
950 unsigned long rate, unsigned long parent_rate)
952 struct tegra_clk_pll *pll = to_clk_pll(hw);
955 err = _get_table_rate(hw, cfg, rate, parent_rate);
957 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
959 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
964 p_div = _p_div_to_hw(hw, cfg->p);
971 if (cfg->p > pll->params->max_p)
978 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
979 unsigned long parent_rate)
981 struct tegra_clk_pll *pll = to_clk_pll(hw);
982 struct tegra_clk_pll_freq_table cfg, old_cfg;
983 unsigned long flags = 0;
986 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
991 spin_lock_irqsave(pll->lock, flags);
993 _get_pll_mnp(pll, &old_cfg);
995 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
996 ret = _program_pll(hw, &cfg, rate);
999 spin_unlock_irqrestore(pll->lock, flags);
1004 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1005 unsigned long *prate)
1007 struct tegra_clk_pll_freq_table cfg;
1009 u64 output_rate = *prate;
1011 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1015 p_div = _hw_to_p_div(hw, cfg.p);
1019 output_rate *= cfg.n;
1020 do_div(output_rate, cfg.m * p_div);
1025 static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate,
1026 unsigned long parent_rate)
1028 struct tegra_clk_pll_freq_table cfg;
1029 struct tegra_clk_pll *pll = to_clk_pll(hw);
1030 unsigned long flags = 0;
1034 spin_lock_irqsave(pll->lock, flags);
1036 state = clk_pll_is_enabled(hw);
1038 if (rate != clk_get_rate(hw->clk)) {
1039 pr_err("%s: Cannot change active PLLM\n", __func__);
1046 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1050 _update_pll_mnp(pll, &cfg);
1054 spin_unlock_irqrestore(pll->lock, flags);
1059 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1063 val = pll_readl_misc(pll);
1064 val |= PLLCX_MISC_STROBE;
1065 pll_writel_misc(val, pll);
1068 val &= ~PLLCX_MISC_STROBE;
1069 pll_writel_misc(val, pll);
1072 static int clk_pllc_enable(struct clk_hw *hw)
1074 struct tegra_clk_pll *pll = to_clk_pll(hw);
1077 unsigned long flags = 0;
1080 spin_lock_irqsave(pll->lock, flags);
1082 _clk_pll_enable(hw);
1085 val = pll_readl_misc(pll);
1086 val &= ~PLLCX_MISC_RESET;
1087 pll_writel_misc(val, pll);
1092 ret = clk_pll_wait_for_lock(pll);
1095 spin_unlock_irqrestore(pll->lock, flags);
1100 static void _clk_pllc_disable(struct clk_hw *hw)
1102 struct tegra_clk_pll *pll = to_clk_pll(hw);
1105 _clk_pll_disable(hw);
1107 val = pll_readl_misc(pll);
1108 val |= PLLCX_MISC_RESET;
1109 pll_writel_misc(val, pll);
1113 static void clk_pllc_disable(struct clk_hw *hw)
1115 struct tegra_clk_pll *pll = to_clk_pll(hw);
1116 unsigned long flags = 0;
1119 spin_lock_irqsave(pll->lock, flags);
1121 _clk_pllc_disable(hw);
1124 spin_unlock_irqrestore(pll->lock, flags);
1127 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1128 unsigned long input_rate, u32 n)
1130 u32 val, n_threshold;
1132 switch (input_rate) {
1147 pr_err("%s: Unexpected reference rate %lu\n",
1148 __func__, input_rate);
1152 val = pll_readl_misc(pll);
1153 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1154 val |= n <= n_threshold ?
1155 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1156 pll_writel_misc(val, pll);
1161 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1162 unsigned long parent_rate)
1164 struct tegra_clk_pll_freq_table cfg, old_cfg;
1165 struct tegra_clk_pll *pll = to_clk_pll(hw);
1166 unsigned long flags = 0;
1170 spin_lock_irqsave(pll->lock, flags);
1172 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1176 _get_pll_mnp(pll, &old_cfg);
1178 if (cfg.m != old_cfg.m) {
1183 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1186 state = clk_pll_is_enabled(hw);
1188 _clk_pllc_disable(hw);
1190 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1194 _update_pll_mnp(pll, &cfg);
1197 ret = clk_pllc_enable(hw);
1201 spin_unlock_irqrestore(pll->lock, flags);
1206 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1207 struct tegra_clk_pll_freq_table *cfg,
1208 unsigned long rate, unsigned long parent_rate)
1211 u64 output_rate = parent_rate;
1213 m = _pll_fixed_mdiv(pll->params, parent_rate);
1214 n = rate * m / parent_rate;
1217 do_div(output_rate, m);
1226 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1227 unsigned long parent_rate)
1229 struct tegra_clk_pll_freq_table cfg, old_cfg;
1230 struct tegra_clk_pll *pll = to_clk_pll(hw);
1231 unsigned long flags = 0;
1235 spin_lock_irqsave(pll->lock, flags);
1237 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1238 _get_pll_mnp(pll, &old_cfg);
1241 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1242 state = clk_pll_is_enabled(hw);
1244 _clk_pll_disable(hw);
1246 _update_pll_mnp(pll, &cfg);
1249 _clk_pll_enable(hw);
1250 ret = clk_pll_wait_for_lock(pll);
1255 spin_unlock_irqrestore(pll->lock, flags);
1260 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1261 unsigned long parent_rate)
1263 struct tegra_clk_pll_freq_table cfg;
1264 struct tegra_clk_pll *pll = to_clk_pll(hw);
1265 u64 rate = parent_rate;
1267 _get_pll_mnp(pll, &cfg);
1270 do_div(rate, cfg.m);
1275 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1276 unsigned long *prate)
1278 struct tegra_clk_pll *pll = to_clk_pll(hw);
1280 return _pllre_calc_rate(pll, NULL, rate, *prate);
1283 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1285 struct tegra_clk_pll *pll = to_clk_pll(hw);
1286 struct tegra_clk_pll_freq_table sel;
1289 unsigned long flags = 0;
1290 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
1292 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1296 spin_lock_irqsave(pll->lock, flags);
1298 val = pll_readl_base(pll);
1299 val &= ~BIT(29); /* Disable lock override */
1300 pll_writel_base(val, pll);
1302 val = pll_readl(pll->params->aux_reg, pll);
1303 val |= PLLE_AUX_ENABLE_SWCTL;
1304 val &= ~PLLE_AUX_SEQ_ENABLE;
1305 pll_writel(val, pll->params->aux_reg, pll);
1308 val = pll_readl_misc(pll);
1309 val |= PLLE_MISC_LOCK_ENABLE;
1310 val |= PLLE_MISC_IDDQ_SW_CTRL;
1311 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1312 val |= PLLE_MISC_PLLE_PTS;
1313 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
1314 pll_writel_misc(val, pll);
1317 val = pll_readl(PLLE_SS_CTRL, pll);
1318 val |= PLLE_SS_DISABLE;
1319 pll_writel(val, PLLE_SS_CTRL, pll);
1321 val = pll_readl_base(pll);
1322 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1323 divm_mask_shifted(pll));
1324 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1325 val |= sel.m << divm_shift(pll);
1326 val |= sel.n << divn_shift(pll);
1327 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1328 pll_writel_base(val, pll);
1331 _clk_pll_enable(hw);
1332 ret = clk_pll_wait_for_lock(pll);
1337 val = pll_readl(PLLE_SS_CTRL, pll);
1338 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1339 val &= ~PLLE_SS_COEFFICIENTS_MASK;
1340 val |= PLLE_SS_COEFFICIENTS_VAL;
1341 pll_writel(val, PLLE_SS_CTRL, pll);
1342 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1343 pll_writel(val, PLLE_SS_CTRL, pll);
1345 val &= ~PLLE_SS_CNTL_INTERP_RESET;
1346 pll_writel(val, PLLE_SS_CTRL, pll);
1349 /* Enable hw control of xusb brick pll */
1350 val = pll_readl_misc(pll);
1351 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1352 pll_writel_misc(val, pll);
1354 val = pll_readl(pll->params->aux_reg, pll);
1355 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1356 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1357 pll_writel(val, pll->params->aux_reg, pll);
1359 val |= PLLE_AUX_SEQ_ENABLE;
1360 pll_writel(val, pll->params->aux_reg, pll);
1362 val = pll_readl(XUSBIO_PLL_CFG0, pll);
1363 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1364 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1365 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1366 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1367 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1369 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1370 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1372 /* Enable hw control of SATA pll */
1373 val = pll_readl(SATA_PLL_CFG0, pll);
1374 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1375 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1376 val |= SATA_PLL_CFG0_SEQ_START_STATE;
1377 pll_writel(val, SATA_PLL_CFG0, pll);
1381 val = pll_readl(SATA_PLL_CFG0, pll);
1382 val |= SATA_PLL_CFG0_SEQ_ENABLE;
1383 pll_writel(val, SATA_PLL_CFG0, pll);
1387 spin_unlock_irqrestore(pll->lock, flags);
1392 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1394 struct tegra_clk_pll *pll = to_clk_pll(hw);
1395 unsigned long flags = 0;
1399 spin_lock_irqsave(pll->lock, flags);
1401 _clk_pll_disable(hw);
1403 val = pll_readl_misc(pll);
1404 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1405 pll_writel_misc(val, pll);
1409 spin_unlock_irqrestore(pll->lock, flags);
1413 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1414 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1417 struct tegra_clk_pll *pll;
1419 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1421 return ERR_PTR(-ENOMEM);
1423 pll->clk_base = clk_base;
1426 pll->params = pll_params;
1429 if (!pll_params->div_nmp)
1430 pll_params->div_nmp = &default_nmp;
1435 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1436 const char *name, const char *parent_name, unsigned long flags,
1437 const struct clk_ops *ops)
1439 struct clk_init_data init;
1444 init.parent_names = (parent_name ? &parent_name : NULL);
1445 init.num_parents = (parent_name ? 1 : 0);
1447 /* Data in .init is copied by clk_register(), so stack variable OK */
1448 pll->hw.init = &init;
1450 return clk_register(NULL, &pll->hw);
1453 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1454 void __iomem *clk_base, void __iomem *pmc,
1455 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1458 struct tegra_clk_pll *pll;
1461 pll_params->flags |= TEGRA_PLL_BYPASS;
1462 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1463 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1465 return ERR_CAST(pll);
1467 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1468 &tegra_clk_pll_ops);
1475 static struct div_nmp pll_e_nmp = {
1476 .divn_shift = PLLE_BASE_DIVN_SHIFT,
1477 .divn_width = PLLE_BASE_DIVN_WIDTH,
1478 .divm_shift = PLLE_BASE_DIVM_SHIFT,
1479 .divm_width = PLLE_BASE_DIVM_WIDTH,
1480 .divp_shift = PLLE_BASE_DIVP_SHIFT,
1481 .divp_width = PLLE_BASE_DIVP_WIDTH,
1484 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1485 void __iomem *clk_base, void __iomem *pmc,
1486 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1489 struct tegra_clk_pll *pll;
1492 pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
1493 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1495 if (!pll_params->div_nmp)
1496 pll_params->div_nmp = &pll_e_nmp;
1498 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1500 return ERR_CAST(pll);
1502 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1503 &tegra_clk_plle_ops);
1510 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1511 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1512 defined(CONFIG_ARCH_TEGRA_132_SOC)
1513 static const struct clk_ops tegra_clk_pllxc_ops = {
1514 .is_enabled = clk_pll_is_enabled,
1515 .enable = clk_pll_iddq_enable,
1516 .disable = clk_pll_iddq_disable,
1517 .recalc_rate = clk_pll_recalc_rate,
1518 .round_rate = clk_pll_ramp_round_rate,
1519 .set_rate = clk_pllxc_set_rate,
1522 static const struct clk_ops tegra_clk_pllm_ops = {
1523 .is_enabled = clk_pll_is_enabled,
1524 .enable = clk_pll_iddq_enable,
1525 .disable = clk_pll_iddq_disable,
1526 .recalc_rate = clk_pll_recalc_rate,
1527 .round_rate = clk_pll_ramp_round_rate,
1528 .set_rate = clk_pllm_set_rate,
1531 static const struct clk_ops tegra_clk_pllc_ops = {
1532 .is_enabled = clk_pll_is_enabled,
1533 .enable = clk_pllc_enable,
1534 .disable = clk_pllc_disable,
1535 .recalc_rate = clk_pll_recalc_rate,
1536 .round_rate = clk_pll_ramp_round_rate,
1537 .set_rate = clk_pllc_set_rate,
1540 static const struct clk_ops tegra_clk_pllre_ops = {
1541 .is_enabled = clk_pll_is_enabled,
1542 .enable = clk_pll_iddq_enable,
1543 .disable = clk_pll_iddq_disable,
1544 .recalc_rate = clk_pllre_recalc_rate,
1545 .round_rate = clk_pllre_round_rate,
1546 .set_rate = clk_pllre_set_rate,
1549 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1550 .is_enabled = clk_pll_is_enabled,
1551 .enable = clk_plle_tegra114_enable,
1552 .disable = clk_plle_tegra114_disable,
1553 .recalc_rate = clk_pll_recalc_rate,
1557 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1558 void __iomem *clk_base, void __iomem *pmc,
1559 unsigned long flags,
1560 struct tegra_clk_pll_params *pll_params,
1563 struct tegra_clk_pll *pll;
1564 struct clk *clk, *parent;
1565 unsigned long parent_rate;
1569 parent = __clk_lookup(parent_name);
1571 WARN(1, "parent clk %s of %s must be registered first\n",
1573 return ERR_PTR(-EINVAL);
1576 if (!pll_params->pdiv_tohw)
1577 return ERR_PTR(-EINVAL);
1579 parent_rate = __clk_get_rate(parent);
1581 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1583 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
1585 return ERR_PTR(err);
1587 val = readl_relaxed(clk_base + pll_params->base_reg);
1588 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1590 if (val & PLL_BASE_ENABLE)
1591 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1593 val_iddq |= BIT(pll_params->iddq_bit_idx);
1594 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
1597 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1598 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1600 return ERR_CAST(pll);
1602 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1603 &tegra_clk_pllxc_ops);
1610 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1611 void __iomem *clk_base, void __iomem *pmc,
1612 unsigned long flags,
1613 struct tegra_clk_pll_params *pll_params,
1614 spinlock_t *lock, unsigned long parent_rate)
1617 struct tegra_clk_pll *pll;
1620 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC;
1622 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1624 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1626 return ERR_CAST(pll);
1628 /* program minimum rate by default */
1630 val = pll_readl_base(pll);
1631 if (val & PLL_BASE_ENABLE)
1632 WARN_ON(val & pll_params->iddq_bit_idx);
1636 m = _pll_fixed_mdiv(pll_params, parent_rate);
1637 val = m << divm_shift(pll);
1638 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
1639 pll_writel_base(val, pll);
1642 /* disable lock override */
1644 val = pll_readl_misc(pll);
1646 pll_writel_misc(val, pll);
1648 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1649 &tegra_clk_pllre_ops);
1656 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1657 void __iomem *clk_base, void __iomem *pmc,
1658 unsigned long flags,
1659 struct tegra_clk_pll_params *pll_params,
1662 struct tegra_clk_pll *pll;
1663 struct clk *clk, *parent;
1664 unsigned long parent_rate;
1666 if (!pll_params->pdiv_tohw)
1667 return ERR_PTR(-EINVAL);
1669 parent = __clk_lookup(parent_name);
1671 WARN(1, "parent clk %s of %s must be registered first\n",
1673 return ERR_PTR(-EINVAL);
1676 parent_rate = __clk_get_rate(parent);
1678 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1680 pll_params->flags |= TEGRA_PLL_BYPASS;
1681 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1682 pll_params->flags |= TEGRA_PLLM;
1683 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1685 return ERR_CAST(pll);
1687 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1688 &tegra_clk_pllm_ops);
1695 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1696 void __iomem *clk_base, void __iomem *pmc,
1697 unsigned long flags,
1698 struct tegra_clk_pll_params *pll_params,
1701 struct clk *parent, *clk;
1702 struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
1703 struct tegra_clk_pll *pll;
1704 struct tegra_clk_pll_freq_table cfg;
1705 unsigned long parent_rate;
1708 return ERR_PTR(-EINVAL);
1710 parent = __clk_lookup(parent_name);
1712 WARN(1, "parent clk %s of %s must be registered first\n",
1714 return ERR_PTR(-EINVAL);
1717 parent_rate = __clk_get_rate(parent);
1719 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1721 pll_params->flags |= TEGRA_PLL_BYPASS;
1722 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1724 return ERR_CAST(pll);
1727 * Most of PLLC register fields are shadowed, and can not be read
1728 * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
1729 * Initialize PLL to default state: disabled, reset; shadow registers
1730 * loaded with default parameters; dividers are preset for half of
1731 * minimum VCO rate (the latter assured that shadowed divider settings
1732 * are within supported range).
1735 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1736 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1738 while (p_tohw->pdiv) {
1739 if (p_tohw->pdiv == 2) {
1740 cfg.p = p_tohw->hw_val;
1746 if (!p_tohw->pdiv) {
1748 return ERR_PTR(-EINVAL);
1751 pll_writel_base(0, pll);
1752 _update_pll_mnp(pll, &cfg);
1754 pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
1755 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
1756 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
1757 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
1759 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1761 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1762 &tegra_clk_pllc_ops);
1769 struct clk *tegra_clk_register_plle_tegra114(const char *name,
1770 const char *parent_name,
1771 void __iomem *clk_base, unsigned long flags,
1772 struct tegra_clk_pll_params *pll_params,
1775 struct tegra_clk_pll *pll;
1779 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1780 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1782 return ERR_CAST(pll);
1784 /* ensure parent is set to pll_re_vco */
1786 val = pll_readl_base(pll);
1787 val_aux = pll_readl(pll_params->aux_reg, pll);
1789 if (val & PLL_BASE_ENABLE) {
1790 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
1791 (val_aux & PLLE_AUX_PLLP_SEL))
1792 WARN(1, "pll_e enabled with unsupported parent %s\n",
1793 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
1796 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
1797 pll_writel(val_aux, pll_params->aux_reg, pll);
1800 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1801 &tegra_clk_plle_tegra114_ops);
1809 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
1810 static const struct clk_ops tegra_clk_pllss_ops = {
1811 .is_enabled = clk_pll_is_enabled,
1812 .enable = clk_pll_iddq_enable,
1813 .disable = clk_pll_iddq_disable,
1814 .recalc_rate = clk_pll_recalc_rate,
1815 .round_rate = clk_pll_ramp_round_rate,
1816 .set_rate = clk_pllxc_set_rate,
1819 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
1820 void __iomem *clk_base, unsigned long flags,
1821 struct tegra_clk_pll_params *pll_params,
1824 struct tegra_clk_pll *pll;
1825 struct clk *clk, *parent;
1826 struct tegra_clk_pll_freq_table cfg;
1827 unsigned long parent_rate;
1831 if (!pll_params->div_nmp)
1832 return ERR_PTR(-EINVAL);
1834 parent = __clk_lookup(parent_name);
1836 WARN(1, "parent clk %s of %s must be registered first\n",
1838 return ERR_PTR(-EINVAL);
1841 pll_params->flags = TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_USE_LOCK;
1842 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1844 return ERR_CAST(pll);
1846 val = pll_readl_base(pll);
1847 val &= ~PLLSS_REF_SRC_SEL_MASK;
1848 pll_writel_base(val, pll);
1850 parent_rate = __clk_get_rate(parent);
1852 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1854 /* initialize PLL to minimum rate */
1856 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1857 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1859 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
1863 return ERR_PTR(-EINVAL);
1866 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
1868 _update_pll_mnp(pll, &cfg);
1870 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
1871 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
1872 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
1873 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
1875 val = pll_readl_base(pll);
1876 if (val & PLL_BASE_ENABLE) {
1877 if (val & BIT(pll_params->iddq_bit_idx)) {
1878 WARN(1, "%s is on but IDDQ set\n", name);
1880 return ERR_PTR(-EINVAL);
1883 val |= BIT(pll_params->iddq_bit_idx);
1885 val &= ~PLLSS_LOCK_OVERRIDE;
1886 pll_writel_base(val, pll);
1888 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1889 &tegra_clk_pllss_ops);