2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/slab.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/clk-provider.h>
26 #define PLL_BASE_BYPASS BIT(31)
27 #define PLL_BASE_ENABLE BIT(30)
28 #define PLL_BASE_REF_ENABLE BIT(29)
29 #define PLL_BASE_OVERRIDE BIT(28)
31 #define PLL_BASE_DIVP_SHIFT 20
32 #define PLL_BASE_DIVP_WIDTH 3
33 #define PLL_BASE_DIVN_SHIFT 8
34 #define PLL_BASE_DIVN_WIDTH 10
35 #define PLL_BASE_DIVM_SHIFT 0
36 #define PLL_BASE_DIVM_WIDTH 5
37 #define PLLU_POST_DIVP_MASK 0x1
39 #define PLL_MISC_DCCON_SHIFT 20
40 #define PLL_MISC_CPCON_SHIFT 8
41 #define PLL_MISC_CPCON_WIDTH 4
42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
43 #define PLL_MISC_LFCON_SHIFT 4
44 #define PLL_MISC_LFCON_WIDTH 4
45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
46 #define PLL_MISC_VCOCON_SHIFT 0
47 #define PLL_MISC_VCOCON_WIDTH 4
48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
50 #define OUT_OF_TABLE_CPCON 8
52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
56 #define PLL_POST_LOCK_DELAY 50
58 #define PLLDU_LFCON_SET_DIVN 600
60 #define PLLE_BASE_DIVCML_SHIFT 24
61 #define PLLE_BASE_DIVCML_MASK 0xf
62 #define PLLE_BASE_DIVP_SHIFT 16
63 #define PLLE_BASE_DIVP_WIDTH 6
64 #define PLLE_BASE_DIVN_SHIFT 8
65 #define PLLE_BASE_DIVN_WIDTH 8
66 #define PLLE_BASE_DIVM_SHIFT 0
67 #define PLLE_BASE_DIVM_WIDTH 8
68 #define PLLE_BASE_ENABLE BIT(31)
70 #define PLLE_MISC_SETUP_BASE_SHIFT 16
71 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
72 #define PLLE_MISC_LOCK_ENABLE BIT(9)
73 #define PLLE_MISC_READY BIT(15)
74 #define PLLE_MISC_SETUP_EX_SHIFT 2
75 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
76 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
77 PLLE_MISC_SETUP_EX_MASK)
78 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
80 #define PLLE_SS_CTRL 0x68
81 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
82 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
83 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
84 #define PLLE_SS_CNTL_CENTER BIT(14)
85 #define PLLE_SS_CNTL_INVERT BIT(15)
86 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
88 #define PLLE_SS_MAX_MASK 0x1ff
89 #define PLLE_SS_MAX_VAL 0x25
90 #define PLLE_SS_INC_MASK (0xff << 16)
91 #define PLLE_SS_INC_VAL (0x1 << 16)
92 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
93 #define PLLE_SS_INCINTRV_VAL (0x20 << 24)
94 #define PLLE_SS_COEFFICIENTS_MASK \
95 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
96 #define PLLE_SS_COEFFICIENTS_VAL \
97 (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)
99 #define PLLE_AUX_PLLP_SEL BIT(2)
100 #define PLLE_AUX_USE_LOCKDET BIT(3)
101 #define PLLE_AUX_ENABLE_SWCTL BIT(4)
102 #define PLLE_AUX_SS_SWCTL BIT(6)
103 #define PLLE_AUX_SEQ_ENABLE BIT(24)
104 #define PLLE_AUX_SEQ_START_STATE BIT(25)
105 #define PLLE_AUX_PLLRE_SEL BIT(28)
106 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
108 #define XUSBIO_PLL_CFG0 0x51c
109 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
110 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
111 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
112 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
113 #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25)
115 #define SATA_PLL_CFG0 0x490
116 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
117 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
118 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
119 #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25)
121 #define PLLE_MISC_PLLE_PTS BIT(8)
122 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
123 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
124 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
125 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
126 #define PLLE_MISC_VREG_CTRL_SHIFT 2
127 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
129 #define PLLCX_MISC_STROBE BIT(31)
130 #define PLLCX_MISC_RESET BIT(30)
131 #define PLLCX_MISC_SDM_DIV_SHIFT 28
132 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
133 #define PLLCX_MISC_FILT_DIV_SHIFT 26
134 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
135 #define PLLCX_MISC_ALPHA_SHIFT 18
136 #define PLLCX_MISC_DIV_LOW_RANGE \
137 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
138 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
139 #define PLLCX_MISC_DIV_HIGH_RANGE \
140 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
141 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
142 #define PLLCX_MISC_COEF_LOW_RANGE \
143 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
144 #define PLLCX_MISC_KA_SHIFT 2
145 #define PLLCX_MISC_KB_SHIFT 9
146 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
147 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
148 PLLCX_MISC_DIV_LOW_RANGE | \
150 #define PLLCX_MISC1_DEFAULT 0x000d2308
151 #define PLLCX_MISC2_DEFAULT 0x30211200
152 #define PLLCX_MISC3_DEFAULT 0x200
154 #define PMC_SATA_PWRGT 0x1ac
155 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
156 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
158 #define PLLSS_MISC_KCP 0
159 #define PLLSS_MISC_KVCO 0
160 #define PLLSS_MISC_SETUP 0
161 #define PLLSS_EN_SDM 0
162 #define PLLSS_EN_SSC 0
163 #define PLLSS_EN_DITHER2 0
164 #define PLLSS_EN_DITHER 1
165 #define PLLSS_SDM_RESET 0
166 #define PLLSS_CLAMP 0
167 #define PLLSS_SDM_SSC_MAX 0
168 #define PLLSS_SDM_SSC_MIN 0
169 #define PLLSS_SDM_SSC_STEP 0
170 #define PLLSS_SDM_DIN 0
171 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
172 (PLLSS_MISC_KVCO << 24) | \
174 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
175 (PLLSS_EN_SSC << 30) | \
176 (PLLSS_EN_DITHER2 << 29) | \
177 (PLLSS_EN_DITHER << 28) | \
178 (PLLSS_SDM_RESET) << 27 | \
180 #define PLLSS_CTRL1_DEFAULT \
181 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
182 #define PLLSS_CTRL2_DEFAULT \
183 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
184 #define PLLSS_LOCK_OVERRIDE BIT(24)
185 #define PLLSS_REF_SRC_SEL_SHIFT 25
186 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT)
188 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
189 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
190 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
191 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
192 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
193 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
195 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
196 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
197 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
198 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
199 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
200 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
202 #define mask(w) ((1 << (w)) - 1)
203 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
204 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
205 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
206 mask(p->params->div_nmp->divp_width))
207 #define sdm_din_mask(p) p->params->sdm_din_mask
208 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
210 #define divm_shift(p) (p)->params->div_nmp->divm_shift
211 #define divn_shift(p) (p)->params->div_nmp->divn_shift
212 #define divp_shift(p) (p)->params->div_nmp->divp_shift
214 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
215 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
216 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
218 #define divm_max(p) (divm_mask(p))
219 #define divn_max(p) (divn_mask(p))
220 #define divp_max(p) (1 << (divp_mask(p)))
222 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
223 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
225 static struct div_nmp default_nmp = {
226 .divn_shift = PLL_BASE_DIVN_SHIFT,
227 .divn_width = PLL_BASE_DIVN_WIDTH,
228 .divm_shift = PLL_BASE_DIVM_SHIFT,
229 .divm_width = PLL_BASE_DIVM_WIDTH,
230 .divp_shift = PLL_BASE_DIVP_SHIFT,
231 .divp_width = PLL_BASE_DIVP_WIDTH,
234 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
238 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
241 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
244 val = pll_readl_misc(pll);
245 val |= BIT(pll->params->lock_enable_bit_idx);
246 pll_writel_misc(val, pll);
249 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
253 void __iomem *lock_addr;
255 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
256 udelay(pll->params->lock_delay);
260 lock_addr = pll->clk_base;
261 if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
262 lock_addr += pll->params->misc_reg;
264 lock_addr += pll->params->base_reg;
266 lock_mask = pll->params->lock_mask;
268 for (i = 0; i < pll->params->lock_delay; i++) {
269 val = readl_relaxed(lock_addr);
270 if ((val & lock_mask) == lock_mask) {
271 udelay(PLL_POST_LOCK_DELAY);
274 udelay(2); /* timeout = 2 * lock time */
277 pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
278 clk_hw_get_name(&pll->hw));
283 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
285 return clk_pll_wait_for_lock(pll);
288 static int clk_pll_is_enabled(struct clk_hw *hw)
290 struct tegra_clk_pll *pll = to_clk_pll(hw);
293 if (pll->params->flags & TEGRA_PLLM) {
294 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
295 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
296 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
299 val = pll_readl_base(pll);
301 return val & PLL_BASE_ENABLE ? 1 : 0;
304 static void _clk_pll_enable(struct clk_hw *hw)
306 struct tegra_clk_pll *pll = to_clk_pll(hw);
309 if (pll->params->iddq_reg) {
310 val = pll_readl(pll->params->iddq_reg, pll);
311 val &= ~BIT(pll->params->iddq_bit_idx);
312 pll_writel(val, pll->params->iddq_reg, pll);
316 if (pll->params->reset_reg) {
317 val = pll_readl(pll->params->reset_reg, pll);
318 val &= ~BIT(pll->params->reset_bit_idx);
319 pll_writel(val, pll->params->reset_reg, pll);
322 clk_pll_enable_lock(pll);
324 val = pll_readl_base(pll);
325 if (pll->params->flags & TEGRA_PLL_BYPASS)
326 val &= ~PLL_BASE_BYPASS;
327 val |= PLL_BASE_ENABLE;
328 pll_writel_base(val, pll);
330 if (pll->params->flags & TEGRA_PLLM) {
331 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
332 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
333 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
337 static void _clk_pll_disable(struct clk_hw *hw)
339 struct tegra_clk_pll *pll = to_clk_pll(hw);
342 val = pll_readl_base(pll);
343 if (pll->params->flags & TEGRA_PLL_BYPASS)
344 val &= ~PLL_BASE_BYPASS;
345 val &= ~PLL_BASE_ENABLE;
346 pll_writel_base(val, pll);
348 if (pll->params->flags & TEGRA_PLLM) {
349 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
350 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
351 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
354 if (pll->params->reset_reg) {
355 val = pll_readl(pll->params->reset_reg, pll);
356 val |= BIT(pll->params->reset_bit_idx);
357 pll_writel(val, pll->params->reset_reg, pll);
360 if (pll->params->iddq_reg) {
361 val = pll_readl(pll->params->iddq_reg, pll);
362 val |= BIT(pll->params->iddq_bit_idx);
363 pll_writel(val, pll->params->iddq_reg, pll);
368 static int clk_pll_enable(struct clk_hw *hw)
370 struct tegra_clk_pll *pll = to_clk_pll(hw);
371 unsigned long flags = 0;
375 spin_lock_irqsave(pll->lock, flags);
379 ret = clk_pll_wait_for_lock(pll);
382 spin_unlock_irqrestore(pll->lock, flags);
387 static void clk_pll_disable(struct clk_hw *hw)
389 struct tegra_clk_pll *pll = to_clk_pll(hw);
390 unsigned long flags = 0;
393 spin_lock_irqsave(pll->lock, flags);
395 _clk_pll_disable(hw);
398 spin_unlock_irqrestore(pll->lock, flags);
401 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
403 struct tegra_clk_pll *pll = to_clk_pll(hw);
404 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
407 while (p_tohw->pdiv) {
408 if (p_div <= p_tohw->pdiv)
409 return p_tohw->hw_val;
417 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
419 return _p_div_to_hw(&pll->hw, p_div);
422 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
424 struct tegra_clk_pll *pll = to_clk_pll(hw);
425 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
428 while (p_tohw->pdiv) {
429 if (p_div_hw == p_tohw->hw_val)
436 return 1 << p_div_hw;
439 static int _get_table_rate(struct clk_hw *hw,
440 struct tegra_clk_pll_freq_table *cfg,
441 unsigned long rate, unsigned long parent_rate)
443 struct tegra_clk_pll *pll = to_clk_pll(hw);
444 struct tegra_clk_pll_freq_table *sel;
447 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
448 if (sel->input_rate == parent_rate &&
449 sel->output_rate == rate)
452 if (sel->input_rate == 0)
455 if (pll->params->pdiv_tohw) {
456 p = _p_div_to_hw(hw, sel->p);
463 cfg->input_rate = sel->input_rate;
464 cfg->output_rate = sel->output_rate;
468 cfg->cpcon = sel->cpcon;
469 cfg->sdm_data = sel->sdm_data;
474 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
475 unsigned long rate, unsigned long parent_rate)
477 struct tegra_clk_pll *pll = to_clk_pll(hw);
482 switch (parent_rate) {
485 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
488 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
492 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
497 * PLL_P_OUT1 rate is not listed in PLLA table
499 cfreq = parent_rate / (parent_rate / 1000000);
502 pr_err("%s Unexpected reference rate %lu\n",
503 __func__, parent_rate);
507 /* Raise VCO to guarantee 0.5% accuracy */
508 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
509 cfg->output_rate <<= 1)
512 cfg->m = parent_rate / cfreq;
513 cfg->n = cfg->output_rate / cfreq;
514 cfg->cpcon = OUT_OF_TABLE_CPCON;
516 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
517 (1 << p_div) > divp_max(pll)
518 || cfg->output_rate > pll->params->vco_max) {
522 cfg->output_rate >>= p_div;
524 if (pll->params->pdiv_tohw) {
525 ret = _p_div_to_hw(hw, 1 << p_div);
537 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
538 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
539 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
540 * to indicate that SDM is disabled.
542 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
544 static void clk_pll_set_sdm_data(struct clk_hw *hw,
545 struct tegra_clk_pll_freq_table *cfg)
547 struct tegra_clk_pll *pll = to_clk_pll(hw);
551 if (!pll->params->sdm_din_reg)
555 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
556 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
557 pll_writel_sdm_din(val, pll);
560 val = pll_readl_sdm_ctrl(pll);
561 enabled = (val & sdm_en_mask(pll));
563 if (cfg->sdm_data == 0 && enabled)
564 val &= ~pll->params->sdm_ctrl_en_mask;
566 if (cfg->sdm_data != 0 && !enabled)
567 val |= pll->params->sdm_ctrl_en_mask;
569 pll_writel_sdm_ctrl(val, pll);
572 static void _update_pll_mnp(struct tegra_clk_pll *pll,
573 struct tegra_clk_pll_freq_table *cfg)
576 struct tegra_clk_pll_params *params = pll->params;
577 struct div_nmp *div_nmp = params->div_nmp;
579 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
580 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
581 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
582 val = pll_override_readl(params->pmc_divp_reg, pll);
583 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
584 val |= cfg->p << div_nmp->override_divp_shift;
585 pll_override_writel(val, params->pmc_divp_reg, pll);
587 val = pll_override_readl(params->pmc_divnm_reg, pll);
588 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |
589 ~(divn_mask(pll) << div_nmp->override_divn_shift);
590 val |= (cfg->m << div_nmp->override_divm_shift) |
591 (cfg->n << div_nmp->override_divn_shift);
592 pll_override_writel(val, params->pmc_divnm_reg, pll);
594 val = pll_readl_base(pll);
596 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
597 divp_mask_shifted(pll));
599 val |= (cfg->m << divm_shift(pll)) |
600 (cfg->n << divn_shift(pll)) |
601 (cfg->p << divp_shift(pll));
603 pll_writel_base(val, pll);
605 clk_pll_set_sdm_data(&pll->hw, cfg);
609 static void _get_pll_mnp(struct tegra_clk_pll *pll,
610 struct tegra_clk_pll_freq_table *cfg)
613 struct tegra_clk_pll_params *params = pll->params;
614 struct div_nmp *div_nmp = params->div_nmp;
616 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
617 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
618 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
619 val = pll_override_readl(params->pmc_divp_reg, pll);
620 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
622 val = pll_override_readl(params->pmc_divnm_reg, pll);
623 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
624 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
626 val = pll_readl_base(pll);
628 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
629 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
630 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
632 if (pll->params->sdm_din_reg) {
633 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
634 val = pll_readl_sdm_din(pll);
635 val &= sdm_din_mask(pll);
636 cfg->sdm_data = sdin_din_to_data(val);
642 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
643 struct tegra_clk_pll_freq_table *cfg,
648 val = pll_readl_misc(pll);
650 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
651 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
653 if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
654 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
655 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
656 val |= 1 << PLL_MISC_LFCON_SHIFT;
657 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
658 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
659 if (rate >= (pll->params->vco_max >> 1))
660 val |= 1 << PLL_MISC_DCCON_SHIFT;
663 pll_writel_misc(val, pll);
666 static void pll_clk_start_ss(struct tegra_clk_pll *pll)
668 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
669 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
671 val |= pll->params->ssc_ctrl_en_mask;
672 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
676 static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
678 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
679 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
681 val &= ~pll->params->ssc_ctrl_en_mask;
682 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
686 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
689 struct tegra_clk_pll *pll = to_clk_pll(hw);
690 struct tegra_clk_pll_freq_table old_cfg;
693 state = clk_pll_is_enabled(hw);
695 _get_pll_mnp(pll, &old_cfg);
697 if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
698 (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
699 ret = pll->params->dyn_ramp(pll, cfg);
705 pll_clk_stop_ss(pll);
706 _clk_pll_disable(hw);
709 if (!pll->params->defaults_set && pll->params->set_defaults)
710 pll->params->set_defaults(pll);
712 _update_pll_mnp(pll, cfg);
714 if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
715 _update_pll_cpcon(pll, cfg, rate);
719 ret = clk_pll_wait_for_lock(pll);
720 pll_clk_start_ss(pll);
726 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
727 unsigned long parent_rate)
729 struct tegra_clk_pll *pll = to_clk_pll(hw);
730 struct tegra_clk_pll_freq_table cfg, old_cfg;
731 unsigned long flags = 0;
734 if (pll->params->flags & TEGRA_PLL_FIXED) {
735 if (rate != pll->params->fixed_rate) {
736 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
737 __func__, clk_hw_get_name(hw),
738 pll->params->fixed_rate, rate);
744 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
745 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
746 pr_err("%s: Failed to set %s rate %lu\n", __func__,
747 clk_hw_get_name(hw), rate);
752 spin_lock_irqsave(pll->lock, flags);
754 _get_pll_mnp(pll, &old_cfg);
755 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
758 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
759 old_cfg.sdm_data != cfg.sdm_data)
760 ret = _program_pll(hw, &cfg, rate);
763 spin_unlock_irqrestore(pll->lock, flags);
768 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
769 unsigned long *prate)
771 struct tegra_clk_pll *pll = to_clk_pll(hw);
772 struct tegra_clk_pll_freq_table cfg;
774 if (pll->params->flags & TEGRA_PLL_FIXED) {
775 /* PLLM/MB are used for memory; we do not change rate */
776 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
777 return clk_hw_get_rate(hw);
778 return pll->params->fixed_rate;
781 if (_get_table_rate(hw, &cfg, rate, *prate) &&
782 pll->params->calc_rate(hw, &cfg, rate, *prate))
785 return cfg.output_rate;
788 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
789 unsigned long parent_rate)
791 struct tegra_clk_pll *pll = to_clk_pll(hw);
792 struct tegra_clk_pll_freq_table cfg;
794 u64 rate = parent_rate;
797 val = pll_readl_base(pll);
799 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
802 if ((pll->params->flags & TEGRA_PLL_FIXED) &&
803 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
804 !(val & PLL_BASE_OVERRIDE)) {
805 struct tegra_clk_pll_freq_table sel;
806 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
808 pr_err("Clock %s has unknown fixed frequency\n",
809 clk_hw_get_name(hw));
812 return pll->params->fixed_rate;
815 _get_pll_mnp(pll, &cfg);
817 if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
820 pdiv = _hw_to_p_div(hw, cfg.p);
822 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
823 clk_hw_get_name(hw), cfg.p);
828 if (pll->params->set_gain)
829 pll->params->set_gain(&cfg);
839 static int clk_plle_training(struct tegra_clk_pll *pll)
842 unsigned long timeout;
848 * PLLE is already disabled, and setup cleared;
849 * create falling edge on PLLE IDDQ input.
851 val = readl(pll->pmc + PMC_SATA_PWRGT);
852 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
853 writel(val, pll->pmc + PMC_SATA_PWRGT);
855 val = readl(pll->pmc + PMC_SATA_PWRGT);
856 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
857 writel(val, pll->pmc + PMC_SATA_PWRGT);
859 val = readl(pll->pmc + PMC_SATA_PWRGT);
860 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
861 writel(val, pll->pmc + PMC_SATA_PWRGT);
863 val = pll_readl_misc(pll);
865 timeout = jiffies + msecs_to_jiffies(100);
867 val = pll_readl_misc(pll);
868 if (val & PLLE_MISC_READY)
870 if (time_after(jiffies, timeout)) {
871 pr_err("%s: timeout waiting for PLLE\n", __func__);
880 static int clk_plle_enable(struct clk_hw *hw)
882 struct tegra_clk_pll *pll = to_clk_pll(hw);
883 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
884 struct tegra_clk_pll_freq_table sel;
888 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
893 val = pll_readl_misc(pll);
894 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
895 pll_writel_misc(val, pll);
897 val = pll_readl_misc(pll);
898 if (!(val & PLLE_MISC_READY)) {
899 err = clk_plle_training(pll);
904 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
905 /* configure dividers */
906 val = pll_readl_base(pll);
907 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
908 divm_mask_shifted(pll));
909 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
910 val |= sel.m << divm_shift(pll);
911 val |= sel.n << divn_shift(pll);
912 val |= sel.p << divp_shift(pll);
913 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
914 pll_writel_base(val, pll);
917 val = pll_readl_misc(pll);
918 val |= PLLE_MISC_SETUP_VALUE;
919 val |= PLLE_MISC_LOCK_ENABLE;
920 pll_writel_misc(val, pll);
922 val = readl(pll->clk_base + PLLE_SS_CTRL);
923 val &= ~PLLE_SS_COEFFICIENTS_MASK;
924 val |= PLLE_SS_DISABLE;
925 writel(val, pll->clk_base + PLLE_SS_CTRL);
927 val = pll_readl_base(pll);
928 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
929 pll_writel_base(val, pll);
931 clk_pll_wait_for_lock(pll);
936 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
937 unsigned long parent_rate)
939 struct tegra_clk_pll *pll = to_clk_pll(hw);
940 u32 val = pll_readl_base(pll);
941 u32 divn = 0, divm = 0, divp = 0;
942 u64 rate = parent_rate;
944 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
945 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
946 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
954 const struct clk_ops tegra_clk_pll_ops = {
955 .is_enabled = clk_pll_is_enabled,
956 .enable = clk_pll_enable,
957 .disable = clk_pll_disable,
958 .recalc_rate = clk_pll_recalc_rate,
959 .round_rate = clk_pll_round_rate,
960 .set_rate = clk_pll_set_rate,
963 const struct clk_ops tegra_clk_plle_ops = {
964 .recalc_rate = clk_plle_recalc_rate,
965 .is_enabled = clk_pll_is_enabled,
966 .disable = clk_pll_disable,
967 .enable = clk_plle_enable,
970 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
971 unsigned long parent_rate)
973 u16 mdiv = parent_rate / pll_params->cf_min;
975 if (pll_params->flags & TEGRA_MDIV_NEW)
976 return (!pll_params->mdiv_default ? mdiv :
977 min(mdiv, pll_params->mdiv_default));
979 if (pll_params->mdiv_default)
980 return pll_params->mdiv_default;
982 if (parent_rate > pll_params->cf_max)
988 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
989 struct tegra_clk_pll_freq_table *cfg,
990 unsigned long rate, unsigned long parent_rate)
992 struct tegra_clk_pll *pll = to_clk_pll(hw);
999 p = DIV_ROUND_UP(pll->params->vco_min, rate);
1000 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1001 cfg->output_rate = rate * p;
1002 cfg->n = cfg->output_rate * cfg->m / parent_rate;
1003 cfg->input_rate = parent_rate;
1005 p_div = _p_div_to_hw(hw, p);
1011 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1017 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1018 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1019 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1020 defined(CONFIG_ARCH_TEGRA_210_SOC)
1022 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1024 struct tegra_clk_pll *pll = to_clk_pll(hw);
1026 return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1029 static unsigned long _clip_vco_min(unsigned long vco_min,
1030 unsigned long parent_rate)
1032 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
1035 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1036 void __iomem *clk_base,
1037 unsigned long parent_rate)
1042 switch (parent_rate) {
1058 pr_err("%s: Unexpected reference rate %lu\n",
1059 __func__, parent_rate);
1064 val = step_a << pll_params->stepa_shift;
1065 val |= step_b << pll_params->stepb_shift;
1066 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1071 static int _pll_ramp_calc_pll(struct clk_hw *hw,
1072 struct tegra_clk_pll_freq_table *cfg,
1073 unsigned long rate, unsigned long parent_rate)
1075 struct tegra_clk_pll *pll = to_clk_pll(hw);
1078 err = _get_table_rate(hw, cfg, rate, parent_rate);
1080 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
1082 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1089 if (cfg->p > pll->params->max_p)
1096 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1097 unsigned long parent_rate)
1099 struct tegra_clk_pll *pll = to_clk_pll(hw);
1100 struct tegra_clk_pll_freq_table cfg, old_cfg;
1101 unsigned long flags = 0;
1104 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1109 spin_lock_irqsave(pll->lock, flags);
1111 _get_pll_mnp(pll, &old_cfg);
1112 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1115 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
1116 ret = _program_pll(hw, &cfg, rate);
1119 spin_unlock_irqrestore(pll->lock, flags);
1124 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1125 unsigned long *prate)
1127 struct tegra_clk_pll *pll = to_clk_pll(hw);
1128 struct tegra_clk_pll_freq_table cfg;
1130 u64 output_rate = *prate;
1132 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1136 p_div = _hw_to_p_div(hw, cfg.p);
1140 if (pll->params->set_gain)
1141 pll->params->set_gain(&cfg);
1143 output_rate *= cfg.n;
1144 do_div(output_rate, cfg.m * p_div);
1149 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1153 val = pll_readl_misc(pll);
1154 val |= PLLCX_MISC_STROBE;
1155 pll_writel_misc(val, pll);
1158 val &= ~PLLCX_MISC_STROBE;
1159 pll_writel_misc(val, pll);
1162 static int clk_pllc_enable(struct clk_hw *hw)
1164 struct tegra_clk_pll *pll = to_clk_pll(hw);
1167 unsigned long flags = 0;
1170 spin_lock_irqsave(pll->lock, flags);
1172 _clk_pll_enable(hw);
1175 val = pll_readl_misc(pll);
1176 val &= ~PLLCX_MISC_RESET;
1177 pll_writel_misc(val, pll);
1182 ret = clk_pll_wait_for_lock(pll);
1185 spin_unlock_irqrestore(pll->lock, flags);
1190 static void _clk_pllc_disable(struct clk_hw *hw)
1192 struct tegra_clk_pll *pll = to_clk_pll(hw);
1195 _clk_pll_disable(hw);
1197 val = pll_readl_misc(pll);
1198 val |= PLLCX_MISC_RESET;
1199 pll_writel_misc(val, pll);
1203 static void clk_pllc_disable(struct clk_hw *hw)
1205 struct tegra_clk_pll *pll = to_clk_pll(hw);
1206 unsigned long flags = 0;
1209 spin_lock_irqsave(pll->lock, flags);
1211 _clk_pllc_disable(hw);
1214 spin_unlock_irqrestore(pll->lock, flags);
1217 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1218 unsigned long input_rate, u32 n)
1220 u32 val, n_threshold;
1222 switch (input_rate) {
1237 pr_err("%s: Unexpected reference rate %lu\n",
1238 __func__, input_rate);
1242 val = pll_readl_misc(pll);
1243 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1244 val |= n <= n_threshold ?
1245 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1246 pll_writel_misc(val, pll);
1251 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1252 unsigned long parent_rate)
1254 struct tegra_clk_pll_freq_table cfg, old_cfg;
1255 struct tegra_clk_pll *pll = to_clk_pll(hw);
1256 unsigned long flags = 0;
1260 spin_lock_irqsave(pll->lock, flags);
1262 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1266 _get_pll_mnp(pll, &old_cfg);
1268 if (cfg.m != old_cfg.m) {
1273 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1276 state = clk_pll_is_enabled(hw);
1278 _clk_pllc_disable(hw);
1280 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1284 _update_pll_mnp(pll, &cfg);
1287 ret = clk_pllc_enable(hw);
1291 spin_unlock_irqrestore(pll->lock, flags);
1296 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1297 struct tegra_clk_pll_freq_table *cfg,
1298 unsigned long rate, unsigned long parent_rate)
1301 u64 output_rate = parent_rate;
1303 m = _pll_fixed_mdiv(pll->params, parent_rate);
1304 n = rate * m / parent_rate;
1307 do_div(output_rate, m);
1317 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1318 unsigned long parent_rate)
1320 struct tegra_clk_pll_freq_table cfg, old_cfg;
1321 struct tegra_clk_pll *pll = to_clk_pll(hw);
1322 unsigned long flags = 0;
1326 spin_lock_irqsave(pll->lock, flags);
1328 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1329 _get_pll_mnp(pll, &old_cfg);
1332 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1333 state = clk_pll_is_enabled(hw);
1335 _clk_pll_disable(hw);
1337 _update_pll_mnp(pll, &cfg);
1340 _clk_pll_enable(hw);
1341 ret = clk_pll_wait_for_lock(pll);
1346 spin_unlock_irqrestore(pll->lock, flags);
1351 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1352 unsigned long parent_rate)
1354 struct tegra_clk_pll_freq_table cfg;
1355 struct tegra_clk_pll *pll = to_clk_pll(hw);
1356 u64 rate = parent_rate;
1358 _get_pll_mnp(pll, &cfg);
1361 do_div(rate, cfg.m);
1366 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1367 unsigned long *prate)
1369 struct tegra_clk_pll *pll = to_clk_pll(hw);
1371 return _pllre_calc_rate(pll, NULL, rate, *prate);
1374 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1376 struct tegra_clk_pll *pll = to_clk_pll(hw);
1377 struct tegra_clk_pll_freq_table sel;
1380 unsigned long flags = 0;
1381 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
1383 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1387 spin_lock_irqsave(pll->lock, flags);
1389 val = pll_readl_base(pll);
1390 val &= ~BIT(29); /* Disable lock override */
1391 pll_writel_base(val, pll);
1393 val = pll_readl(pll->params->aux_reg, pll);
1394 val |= PLLE_AUX_ENABLE_SWCTL;
1395 val &= ~PLLE_AUX_SEQ_ENABLE;
1396 pll_writel(val, pll->params->aux_reg, pll);
1399 val = pll_readl_misc(pll);
1400 val |= PLLE_MISC_LOCK_ENABLE;
1401 val |= PLLE_MISC_IDDQ_SW_CTRL;
1402 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1403 val |= PLLE_MISC_PLLE_PTS;
1404 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
1405 pll_writel_misc(val, pll);
1408 val = pll_readl(PLLE_SS_CTRL, pll);
1409 val |= PLLE_SS_DISABLE;
1410 pll_writel(val, PLLE_SS_CTRL, pll);
1412 val = pll_readl_base(pll);
1413 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1414 divm_mask_shifted(pll));
1415 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1416 val |= sel.m << divm_shift(pll);
1417 val |= sel.n << divn_shift(pll);
1418 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1419 pll_writel_base(val, pll);
1422 _clk_pll_enable(hw);
1423 ret = clk_pll_wait_for_lock(pll);
1428 val = pll_readl(PLLE_SS_CTRL, pll);
1429 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1430 val &= ~PLLE_SS_COEFFICIENTS_MASK;
1431 val |= PLLE_SS_COEFFICIENTS_VAL;
1432 pll_writel(val, PLLE_SS_CTRL, pll);
1433 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1434 pll_writel(val, PLLE_SS_CTRL, pll);
1436 val &= ~PLLE_SS_CNTL_INTERP_RESET;
1437 pll_writel(val, PLLE_SS_CTRL, pll);
1440 /* Enable hw control of xusb brick pll */
1441 val = pll_readl_misc(pll);
1442 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1443 pll_writel_misc(val, pll);
1445 val = pll_readl(pll->params->aux_reg, pll);
1446 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1447 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1448 pll_writel(val, pll->params->aux_reg, pll);
1450 val |= PLLE_AUX_SEQ_ENABLE;
1451 pll_writel(val, pll->params->aux_reg, pll);
1453 val = pll_readl(XUSBIO_PLL_CFG0, pll);
1454 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1455 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1456 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1457 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1458 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1460 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1461 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1463 /* Enable hw control of SATA pll */
1464 val = pll_readl(SATA_PLL_CFG0, pll);
1465 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1466 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1467 val |= SATA_PLL_CFG0_SEQ_START_STATE;
1468 pll_writel(val, SATA_PLL_CFG0, pll);
1472 val = pll_readl(SATA_PLL_CFG0, pll);
1473 val |= SATA_PLL_CFG0_SEQ_ENABLE;
1474 pll_writel(val, SATA_PLL_CFG0, pll);
1478 spin_unlock_irqrestore(pll->lock, flags);
1483 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1485 struct tegra_clk_pll *pll = to_clk_pll(hw);
1486 unsigned long flags = 0;
1490 spin_lock_irqsave(pll->lock, flags);
1492 _clk_pll_disable(hw);
1494 val = pll_readl_misc(pll);
1495 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1496 pll_writel_misc(val, pll);
1500 spin_unlock_irqrestore(pll->lock, flags);
1504 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1505 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1508 struct tegra_clk_pll *pll;
1510 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1512 return ERR_PTR(-ENOMEM);
1514 pll->clk_base = clk_base;
1517 pll->params = pll_params;
1520 if (!pll_params->div_nmp)
1521 pll_params->div_nmp = &default_nmp;
1526 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1527 const char *name, const char *parent_name, unsigned long flags,
1528 const struct clk_ops *ops)
1530 struct clk_init_data init;
1535 init.parent_names = (parent_name ? &parent_name : NULL);
1536 init.num_parents = (parent_name ? 1 : 0);
1538 /* Default to _calc_rate if unspecified */
1539 if (!pll->params->calc_rate) {
1540 if (pll->params->flags & TEGRA_PLLM)
1541 pll->params->calc_rate = _calc_dynamic_ramp_rate;
1543 pll->params->calc_rate = _calc_rate;
1546 if (pll->params->set_defaults)
1547 pll->params->set_defaults(pll);
1549 /* Data in .init is copied by clk_register(), so stack variable OK */
1550 pll->hw.init = &init;
1552 return clk_register(NULL, &pll->hw);
1555 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1556 void __iomem *clk_base, void __iomem *pmc,
1557 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1560 struct tegra_clk_pll *pll;
1563 pll_params->flags |= TEGRA_PLL_BYPASS;
1565 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1567 return ERR_CAST(pll);
1569 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1570 &tegra_clk_pll_ops);
1577 static struct div_nmp pll_e_nmp = {
1578 .divn_shift = PLLE_BASE_DIVN_SHIFT,
1579 .divn_width = PLLE_BASE_DIVN_WIDTH,
1580 .divm_shift = PLLE_BASE_DIVM_SHIFT,
1581 .divm_width = PLLE_BASE_DIVM_WIDTH,
1582 .divp_shift = PLLE_BASE_DIVP_SHIFT,
1583 .divp_width = PLLE_BASE_DIVP_WIDTH,
1586 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1587 void __iomem *clk_base, void __iomem *pmc,
1588 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1591 struct tegra_clk_pll *pll;
1594 pll_params->flags |= TEGRA_PLL_BYPASS;
1596 if (!pll_params->div_nmp)
1597 pll_params->div_nmp = &pll_e_nmp;
1599 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1601 return ERR_CAST(pll);
1603 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1604 &tegra_clk_plle_ops);
1611 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1612 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1613 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1614 defined(CONFIG_ARCH_TEGRA_210_SOC)
1615 static const struct clk_ops tegra_clk_pllxc_ops = {
1616 .is_enabled = clk_pll_is_enabled,
1617 .enable = clk_pll_enable,
1618 .disable = clk_pll_disable,
1619 .recalc_rate = clk_pll_recalc_rate,
1620 .round_rate = clk_pll_ramp_round_rate,
1621 .set_rate = clk_pllxc_set_rate,
1624 static const struct clk_ops tegra_clk_pllc_ops = {
1625 .is_enabled = clk_pll_is_enabled,
1626 .enable = clk_pllc_enable,
1627 .disable = clk_pllc_disable,
1628 .recalc_rate = clk_pll_recalc_rate,
1629 .round_rate = clk_pll_ramp_round_rate,
1630 .set_rate = clk_pllc_set_rate,
1633 static const struct clk_ops tegra_clk_pllre_ops = {
1634 .is_enabled = clk_pll_is_enabled,
1635 .enable = clk_pll_enable,
1636 .disable = clk_pll_disable,
1637 .recalc_rate = clk_pllre_recalc_rate,
1638 .round_rate = clk_pllre_round_rate,
1639 .set_rate = clk_pllre_set_rate,
1642 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1643 .is_enabled = clk_pll_is_enabled,
1644 .enable = clk_plle_tegra114_enable,
1645 .disable = clk_plle_tegra114_disable,
1646 .recalc_rate = clk_pll_recalc_rate,
1650 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1651 void __iomem *clk_base, void __iomem *pmc,
1652 unsigned long flags,
1653 struct tegra_clk_pll_params *pll_params,
1656 struct tegra_clk_pll *pll;
1657 struct clk *clk, *parent;
1658 unsigned long parent_rate;
1661 parent = __clk_lookup(parent_name);
1663 WARN(1, "parent clk %s of %s must be registered first\n",
1665 return ERR_PTR(-EINVAL);
1668 if (!pll_params->pdiv_tohw)
1669 return ERR_PTR(-EINVAL);
1671 parent_rate = clk_get_rate(parent);
1673 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1675 if (pll_params->adjust_vco)
1676 pll_params->vco_min = pll_params->adjust_vco(pll_params,
1680 * If the pll has a set_defaults callback, it will take care of
1681 * configuring dynamic ramping and setting IDDQ in that path.
1683 if (!pll_params->set_defaults) {
1686 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
1688 return ERR_PTR(err);
1690 val = readl_relaxed(clk_base + pll_params->base_reg);
1691 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1693 if (val & PLL_BASE_ENABLE)
1694 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1696 val_iddq |= BIT(pll_params->iddq_bit_idx);
1697 writel_relaxed(val_iddq,
1698 clk_base + pll_params->iddq_reg);
1702 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1704 return ERR_CAST(pll);
1706 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1707 &tegra_clk_pllxc_ops);
1714 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1715 void __iomem *clk_base, void __iomem *pmc,
1716 unsigned long flags,
1717 struct tegra_clk_pll_params *pll_params,
1718 spinlock_t *lock, unsigned long parent_rate)
1721 struct tegra_clk_pll *pll;
1724 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1726 if (pll_params->adjust_vco)
1727 pll_params->vco_min = pll_params->adjust_vco(pll_params,
1730 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1732 return ERR_CAST(pll);
1734 /* program minimum rate by default */
1736 val = pll_readl_base(pll);
1737 if (val & PLL_BASE_ENABLE)
1738 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
1739 BIT(pll_params->iddq_bit_idx));
1743 m = _pll_fixed_mdiv(pll_params, parent_rate);
1744 val = m << divm_shift(pll);
1745 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
1746 pll_writel_base(val, pll);
1749 /* disable lock override */
1751 val = pll_readl_misc(pll);
1753 pll_writel_misc(val, pll);
1755 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1756 &tegra_clk_pllre_ops);
1763 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1764 void __iomem *clk_base, void __iomem *pmc,
1765 unsigned long flags,
1766 struct tegra_clk_pll_params *pll_params,
1769 struct tegra_clk_pll *pll;
1770 struct clk *clk, *parent;
1771 unsigned long parent_rate;
1773 if (!pll_params->pdiv_tohw)
1774 return ERR_PTR(-EINVAL);
1776 parent = __clk_lookup(parent_name);
1778 WARN(1, "parent clk %s of %s must be registered first\n",
1780 return ERR_PTR(-EINVAL);
1783 parent_rate = clk_get_rate(parent);
1785 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1787 if (pll_params->adjust_vco)
1788 pll_params->vco_min = pll_params->adjust_vco(pll_params,
1791 pll_params->flags |= TEGRA_PLL_BYPASS;
1792 pll_params->flags |= TEGRA_PLLM;
1793 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1795 return ERR_CAST(pll);
1797 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1798 &tegra_clk_pll_ops);
1805 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1806 void __iomem *clk_base, void __iomem *pmc,
1807 unsigned long flags,
1808 struct tegra_clk_pll_params *pll_params,
1811 struct clk *parent, *clk;
1812 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
1813 struct tegra_clk_pll *pll;
1814 struct tegra_clk_pll_freq_table cfg;
1815 unsigned long parent_rate;
1818 return ERR_PTR(-EINVAL);
1820 parent = __clk_lookup(parent_name);
1822 WARN(1, "parent clk %s of %s must be registered first\n",
1824 return ERR_PTR(-EINVAL);
1827 parent_rate = clk_get_rate(parent);
1829 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1831 pll_params->flags |= TEGRA_PLL_BYPASS;
1832 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1834 return ERR_CAST(pll);
1837 * Most of PLLC register fields are shadowed, and can not be read
1838 * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
1839 * Initialize PLL to default state: disabled, reset; shadow registers
1840 * loaded with default parameters; dividers are preset for half of
1841 * minimum VCO rate (the latter assured that shadowed divider settings
1842 * are within supported range).
1845 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1846 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1848 while (p_tohw->pdiv) {
1849 if (p_tohw->pdiv == 2) {
1850 cfg.p = p_tohw->hw_val;
1856 if (!p_tohw->pdiv) {
1858 return ERR_PTR(-EINVAL);
1861 pll_writel_base(0, pll);
1862 _update_pll_mnp(pll, &cfg);
1864 pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
1865 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
1866 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
1867 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
1869 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1871 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1872 &tegra_clk_pllc_ops);
1879 struct clk *tegra_clk_register_plle_tegra114(const char *name,
1880 const char *parent_name,
1881 void __iomem *clk_base, unsigned long flags,
1882 struct tegra_clk_pll_params *pll_params,
1885 struct tegra_clk_pll *pll;
1889 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1891 return ERR_CAST(pll);
1893 /* ensure parent is set to pll_re_vco */
1895 val = pll_readl_base(pll);
1896 val_aux = pll_readl(pll_params->aux_reg, pll);
1898 if (val & PLL_BASE_ENABLE) {
1899 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
1900 (val_aux & PLLE_AUX_PLLP_SEL))
1901 WARN(1, "pll_e enabled with unsupported parent %s\n",
1902 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
1905 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
1906 pll_writel(val_aux, pll_params->aux_reg, pll);
1909 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1910 &tegra_clk_plle_tegra114_ops);
1918 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
1919 static const struct clk_ops tegra_clk_pllss_ops = {
1920 .is_enabled = clk_pll_is_enabled,
1921 .enable = clk_pll_enable,
1922 .disable = clk_pll_disable,
1923 .recalc_rate = clk_pll_recalc_rate,
1924 .round_rate = clk_pll_ramp_round_rate,
1925 .set_rate = clk_pllxc_set_rate,
1928 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
1929 void __iomem *clk_base, unsigned long flags,
1930 struct tegra_clk_pll_params *pll_params,
1933 struct tegra_clk_pll *pll;
1934 struct clk *clk, *parent;
1935 struct tegra_clk_pll_freq_table cfg;
1936 unsigned long parent_rate;
1940 if (!pll_params->div_nmp)
1941 return ERR_PTR(-EINVAL);
1943 parent = __clk_lookup(parent_name);
1945 WARN(1, "parent clk %s of %s must be registered first\n",
1947 return ERR_PTR(-EINVAL);
1950 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1952 return ERR_CAST(pll);
1954 val = pll_readl_base(pll);
1955 val &= ~PLLSS_REF_SRC_SEL_MASK;
1956 pll_writel_base(val, pll);
1958 parent_rate = clk_get_rate(parent);
1960 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1962 /* initialize PLL to minimum rate */
1964 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1965 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1967 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
1971 return ERR_PTR(-EINVAL);
1974 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
1976 _update_pll_mnp(pll, &cfg);
1978 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
1979 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
1980 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
1981 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
1983 val = pll_readl_base(pll);
1984 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1985 if (val & PLL_BASE_ENABLE) {
1986 if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
1987 WARN(1, "%s is on but IDDQ set\n", name);
1989 return ERR_PTR(-EINVAL);
1992 val_iddq |= BIT(pll_params->iddq_bit_idx);
1993 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
1996 val &= ~PLLSS_LOCK_OVERRIDE;
1997 pll_writel_base(val, pll);
1999 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2000 &tegra_clk_pllss_ops);
2009 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
2010 static int clk_plle_tegra210_enable(struct clk_hw *hw)
2012 struct tegra_clk_pll *pll = to_clk_pll(hw);
2013 struct tegra_clk_pll_freq_table sel;
2016 unsigned long flags = 0;
2017 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
2019 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2023 spin_lock_irqsave(pll->lock, flags);
2025 val = pll_readl_base(pll);
2026 val &= ~BIT(30); /* Disable lock override */
2027 pll_writel_base(val, pll);
2029 val = pll_readl(pll->params->aux_reg, pll);
2030 val |= PLLE_AUX_ENABLE_SWCTL;
2031 val &= ~PLLE_AUX_SEQ_ENABLE;
2032 pll_writel(val, pll->params->aux_reg, pll);
2035 val = pll_readl_misc(pll);
2036 val |= PLLE_MISC_LOCK_ENABLE;
2037 val |= PLLE_MISC_IDDQ_SW_CTRL;
2038 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2039 val |= PLLE_MISC_PLLE_PTS;
2040 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
2041 pll_writel_misc(val, pll);
2044 val = pll_readl(PLLE_SS_CTRL, pll);
2045 val |= PLLE_SS_DISABLE;
2046 pll_writel(val, PLLE_SS_CTRL, pll);
2048 val = pll_readl_base(pll);
2049 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2050 divm_mask_shifted(pll));
2051 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2052 val |= sel.m << divm_shift(pll);
2053 val |= sel.n << divn_shift(pll);
2054 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2055 pll_writel_base(val, pll);
2058 val = pll_readl_base(pll);
2059 val |= PLLE_BASE_ENABLE;
2060 pll_writel_base(val, pll);
2062 ret = clk_pll_wait_for_lock(pll);
2067 val = pll_readl(PLLE_SS_CTRL, pll);
2068 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2069 val &= ~PLLE_SS_COEFFICIENTS_MASK;
2070 val |= PLLE_SS_COEFFICIENTS_VAL;
2071 pll_writel(val, PLLE_SS_CTRL, pll);
2072 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2073 pll_writel(val, PLLE_SS_CTRL, pll);
2075 val &= ~PLLE_SS_CNTL_INTERP_RESET;
2076 pll_writel(val, PLLE_SS_CTRL, pll);
2079 val = pll_readl_misc(pll);
2080 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
2081 pll_writel_misc(val, pll);
2083 val = pll_readl(pll->params->aux_reg, pll);
2084 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
2085 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
2086 pll_writel(val, pll->params->aux_reg, pll);
2088 val |= PLLE_AUX_SEQ_ENABLE;
2089 pll_writel(val, pll->params->aux_reg, pll);
2093 spin_unlock_irqrestore(pll->lock, flags);
2098 static void clk_plle_tegra210_disable(struct clk_hw *hw)
2100 struct tegra_clk_pll *pll = to_clk_pll(hw);
2101 unsigned long flags = 0;
2105 spin_lock_irqsave(pll->lock, flags);
2107 val = pll_readl_base(pll);
2108 val &= ~PLLE_BASE_ENABLE;
2109 pll_writel_base(val, pll);
2111 val = pll_readl_misc(pll);
2112 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2113 pll_writel_misc(val, pll);
2117 spin_unlock_irqrestore(pll->lock, flags);
2120 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2122 struct tegra_clk_pll *pll = to_clk_pll(hw);
2125 val = pll_readl_base(pll);
2127 return val & PLLE_BASE_ENABLE ? 1 : 0;
2130 static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2131 .is_enabled = clk_plle_tegra210_is_enabled,
2132 .enable = clk_plle_tegra210_enable,
2133 .disable = clk_plle_tegra210_disable,
2134 .recalc_rate = clk_pll_recalc_rate,
2137 struct clk *tegra_clk_register_plle_tegra210(const char *name,
2138 const char *parent_name,
2139 void __iomem *clk_base, unsigned long flags,
2140 struct tegra_clk_pll_params *pll_params,
2143 struct tegra_clk_pll *pll;
2147 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2149 return ERR_CAST(pll);
2151 /* ensure parent is set to pll_re_vco */
2153 val = pll_readl_base(pll);
2154 val_aux = pll_readl(pll_params->aux_reg, pll);
2156 if (val & PLLE_BASE_ENABLE) {
2157 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2158 (val_aux & PLLE_AUX_PLLP_SEL))
2159 WARN(1, "pll_e enabled with unsupported parent %s\n",
2160 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2163 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2164 pll_writel(val_aux, pll_params->aux_reg, pll);
2167 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2168 &tegra_clk_plle_tegra210_ops);
2175 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
2176 const char *parent_name, void __iomem *clk_base,
2177 void __iomem *pmc, unsigned long flags,
2178 struct tegra_clk_pll_params *pll_params,
2181 struct clk *parent, *clk;
2182 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2183 struct tegra_clk_pll *pll;
2184 unsigned long parent_rate;
2187 return ERR_PTR(-EINVAL);
2189 parent = __clk_lookup(parent_name);
2191 WARN(1, "parent clk %s of %s must be registered first\n",
2193 return ERR_PTR(-EINVAL);
2196 parent_rate = clk_get_rate(parent);
2198 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2200 if (pll_params->adjust_vco)
2201 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2204 pll_params->flags |= TEGRA_PLL_BYPASS;
2205 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2207 return ERR_CAST(pll);
2209 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2210 &tegra_clk_pll_ops);
2217 struct clk *tegra_clk_register_pllxc_tegra210(const char *name,
2218 const char *parent_name, void __iomem *clk_base,
2219 void __iomem *pmc, unsigned long flags,
2220 struct tegra_clk_pll_params *pll_params,
2223 struct tegra_clk_pll *pll;
2224 struct clk *clk, *parent;
2225 unsigned long parent_rate;
2227 parent = __clk_lookup(parent_name);
2229 WARN(1, "parent clk %s of %s must be registered first\n",
2231 return ERR_PTR(-EINVAL);
2234 if (!pll_params->pdiv_tohw)
2235 return ERR_PTR(-EINVAL);
2237 parent_rate = clk_get_rate(parent);
2239 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2241 if (pll_params->adjust_vco)
2242 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2245 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2247 return ERR_CAST(pll);
2249 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2250 &tegra_clk_pll_ops);
2257 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
2258 const char *parent_name, void __iomem *clk_base,
2259 unsigned long flags,
2260 struct tegra_clk_pll_params *pll_params,
2263 struct tegra_clk_pll *pll;
2264 struct clk *clk, *parent;
2265 struct tegra_clk_pll_freq_table cfg;
2266 unsigned long parent_rate;
2270 if (!pll_params->div_nmp)
2271 return ERR_PTR(-EINVAL);
2273 parent = __clk_lookup(parent_name);
2275 WARN(1, "parent clk %s of %s must be registered first\n",
2277 return ERR_PTR(-EINVAL);
2280 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2282 return ERR_CAST(pll);
2284 val = pll_readl_base(pll);
2285 val &= ~PLLSS_REF_SRC_SEL_MASK;
2286 pll_writel_base(val, pll);
2288 parent_rate = clk_get_rate(parent);
2290 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2292 if (pll_params->adjust_vco)
2293 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2296 /* initialize PLL to minimum rate */
2298 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2299 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2301 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2305 return ERR_PTR(-EINVAL);
2308 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2310 _update_pll_mnp(pll, &cfg);
2312 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2314 val = pll_readl_base(pll);
2315 if (val & PLL_BASE_ENABLE) {
2316 if (val & BIT(pll_params->iddq_bit_idx)) {
2317 WARN(1, "%s is on but IDDQ set\n", name);
2319 return ERR_PTR(-EINVAL);
2322 val |= BIT(pll_params->iddq_bit_idx);
2324 val &= ~PLLSS_LOCK_OVERRIDE;
2325 pll_writel_base(val, pll);
2327 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2328 &tegra_clk_pll_ops);
2336 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2337 void __iomem *clk_base, void __iomem *pmc,
2338 unsigned long flags,
2339 struct tegra_clk_pll_params *pll_params,
2342 struct tegra_clk_pll *pll;
2343 struct clk *clk, *parent;
2344 unsigned long parent_rate;
2346 if (!pll_params->pdiv_tohw)
2347 return ERR_PTR(-EINVAL);
2349 parent = __clk_lookup(parent_name);
2351 WARN(1, "parent clk %s of %s must be registered first\n",
2353 return ERR_PTR(-EINVAL);
2356 parent_rate = clk_get_rate(parent);
2358 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2360 if (pll_params->adjust_vco)
2361 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2364 pll_params->flags |= TEGRA_PLL_BYPASS;
2365 pll_params->flags |= TEGRA_PLLMB;
2366 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2368 return ERR_CAST(pll);
2370 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2371 &tegra_clk_pll_ops);