2 * This header provides IDs for clocks common between several Tegra SoCs
4 #ifndef _TEGRA_CLK_ID_H
5 #define _TEGRA_CLK_ID_H
47 tegra_clk_clk_out_1_mux,
49 tegra_clk_clk_out_2_mux,
51 tegra_clk_clk_out_3_mux,
96 tegra_clk_hda2codec_2x,
97 tegra_clk_hda2codec_2x_8,
100 tegra_clk_hdmi_audio,
149 tegra_clk_pll_a_out0,
155 tegra_clk_pll_c4_out0,
156 tegra_clk_pll_c4_out1,
157 tegra_clk_pll_c4_out2,
158 tegra_clk_pll_c4_out3,
159 tegra_clk_pll_c_out1,
162 tegra_clk_pll_d2_out0,
163 tegra_clk_pll_d_out0,
165 tegra_clk_pll_e_out0,
168 tegra_clk_pll_m_out1,
171 tegra_clk_pll_p_out1,
172 tegra_clk_pll_p_out2,
173 tegra_clk_pll_p_out2_int,
174 tegra_clk_pll_p_out3,
175 tegra_clk_pll_p_out4,
176 tegra_clk_pll_p_out4_cpu,
177 tegra_clk_pll_p_out5,
178 tegra_clk_pll_p_out_hsio,
179 tegra_clk_pll_p_out_xusb,
180 tegra_clk_pll_p_out_cpu,
181 tegra_clk_pll_p_out_adsp,
183 tegra_clk_pll_re_out,
184 tegra_clk_pll_re_vco,
187 tegra_clk_pll_u_out1,
188 tegra_clk_pll_u_out2,
190 tegra_clk_pll_u_480m,
194 tegra_clk_pll_x_out0,
202 tegra_clk_sata_oob_8,
220 tegra_clk_sdmmc_legacy,
235 tegra_clk_soc_therm_8,
239 tegra_clk_sor1_brick,
244 tegra_clk_spdif_in_8,
245 tegra_clk_spdif_in_sync,
268 tegra_clk_usb2_hsic_trk,
284 tegra_clk_vimclk_sync,
286 tegra_clk_vi_sensor_8,
287 tegra_clk_vi_sensor_9,
288 tegra_clk_vi_sensor2,
289 tegra_clk_vi_sensor2_8,
291 tegra_clk_xusb_dev_src,
292 tegra_clk_xusb_dev_src_8,
293 tegra_clk_xusb_falcon_src,
294 tegra_clk_xusb_falcon_src_8,
295 tegra_clk_xusb_fs_src,
298 tegra_clk_xusb_host_src,
299 tegra_clk_xusb_host_src_8,
300 tegra_clk_xusb_hs_src,
301 tegra_clk_xusb_hs_src_4,
303 tegra_clk_xusb_ss_src,
304 tegra_clk_xusb_ss_src_8,
305 tegra_clk_xusb_ss_div2,
306 tegra_clk_xusb_ssp_src,
311 #endif /* _TEGRA_CLK_ID_H */