drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/of_address.h>
   9 #include <linux/platform_device.h>
  10
  11 #include "ccu_common.h"
  12 #include "ccu_gate.h"
  13 #include "ccu_reset.h"
  14
  15 #include "ccu-sun9i-a80-usb.h"
  16
  17 static SUNXI_CCU_GATE(bus_hci0_clk, "bus-hci0", "bus-usb", 0x0, BIT(1), 0);
  18 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", 0x0, BIT(2), 0);
  19 static SUNXI_CCU_GATE(bus_hci1_clk, "bus-hci1", "bus-usb", 0x0, BIT(3), 0);
  20 static SUNXI_CCU_GATE(bus_hci2_clk, "bus-hci2", "bus-usb", 0x0, BIT(5), 0);
  21 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M", 0x0, BIT(6), 0);
  22
  23 static SUNXI_CCU_GATE(usb0_phy_clk, "usb0-phy", "osc24M", 0x4, BIT(1), 0);
  24 static SUNXI_CCU_GATE(usb1_hsic_clk, "usb1-hsic", "osc24M", 0x4, BIT(2), 0);
  25 static SUNXI_CCU_GATE(usb1_phy_clk, "usb1-phy", "osc24M", 0x4, BIT(3), 0);
  26 static SUNXI_CCU_GATE(usb2_hsic_clk, "usb2-hsic", "osc24M", 0x4, BIT(4), 0);
  27 static SUNXI_CCU_GATE(usb2_phy_clk, "usb2-phy", "osc24M", 0x4, BIT(5), 0);
  28 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "osc24M", 0x4, BIT(10), 0);
  29
  30 static struct ccu_common *sun9i_a80_usb_clks[] = {
  31         &bus_hci0_clk.common,
  32         &usb_ohci0_clk.common,
  33         &bus_hci1_clk.common,
  34         &bus_hci2_clk.common,
  35         &usb_ohci2_clk.common,
  36
  37         &usb0_phy_clk.common,
  38         &usb1_hsic_clk.common,
  39         &usb1_phy_clk.common,
  40         &usb2_hsic_clk.common,
  41         &usb2_phy_clk.common,
  42         &usb_hsic_clk.common,
  43 };
  44
  45 static struct clk_hw_onecell_data sun9i_a80_usb_hw_clks = {
  46         .hws    = {
  47                 [CLK_BUS_HCI0]  = &bus_hci0_clk.common.hw,
  48                 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
  49                 [CLK_BUS_HCI1]  = &bus_hci1_clk.common.hw,
  50                 [CLK_BUS_HCI2]  = &bus_hci2_clk.common.hw,
  51                 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
  52
  53                 [CLK_USB0_PHY]  = &usb0_phy_clk.common.hw,
  54                 [CLK_USB1_HSIC] = &usb1_hsic_clk.common.hw,
  55                 [CLK_USB1_PHY]  = &usb1_phy_clk.common.hw,
  56                 [CLK_USB2_HSIC] = &usb2_hsic_clk.common.hw,
  57                 [CLK_USB2_PHY]  = &usb2_phy_clk.common.hw,
  58                 [CLK_USB_HSIC]  = &usb_hsic_clk.common.hw,
  59         },
  60         .num    = CLK_NUMBER,
  61 };
  62
  63 static struct ccu_reset_map sun9i_a80_usb_resets[] = {
  64         [RST_USB0_HCI]          = { 0x0, BIT(17) },
  65         [RST_USB1_HCI]          = { 0x0, BIT(18) },
  66         [RST_USB2_HCI]          = { 0x0, BIT(19) },
  67
  68         [RST_USB0_PHY]          = { 0x4, BIT(17) },
  69         [RST_USB1_HSIC]         = { 0x4, BIT(18) },
  70         [RST_USB1_PHY]          = { 0x4, BIT(19) },
  71         [RST_USB2_HSIC]         = { 0x4, BIT(20) },
  72         [RST_USB2_PHY]          = { 0x4, BIT(21) },
  73 };
  74
  75 static const struct sunxi_ccu_desc sun9i_a80_usb_clk_desc = {
  76         .ccu_clks       = sun9i_a80_usb_clks,
  77         .num_ccu_clks   = ARRAY_SIZE(sun9i_a80_usb_clks),
  78
  79         .hw_clks        = &sun9i_a80_usb_hw_clks,
  80
  81         .resets         = sun9i_a80_usb_resets,
  82         .num_resets     = ARRAY_SIZE(sun9i_a80_usb_resets),
  83 };
  84
  85 static int sun9i_a80_usb_clk_probe(struct platform_device *pdev)
  86 {
  87         struct resource *res;
  88         struct clk *bus_clk;
  89         void __iomem *reg;
  90         int ret;
  91
  92         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  93         reg = devm_ioremap_resource(&pdev->dev, res);
  94         if (IS_ERR(reg))
  95                 return PTR_ERR(reg);
  96
  97         bus_clk = devm_clk_get(&pdev->dev, "bus");
  98         if (IS_ERR(bus_clk)) {
  99                 ret = PTR_ERR(bus_clk);
 100                 if (ret != -EPROBE_DEFER)
 101                         dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret);
 102                 return ret;
 103         }
 104
 105         /* The bus clock needs to be enabled for us to access the registers */
 106         ret = clk_prepare_enable(bus_clk);
 107         if (ret) {
 108                 dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret);
 109                 return ret;
 110         }
 111
 112         ret = sunxi_ccu_probe(pdev->dev.of_node, reg,
 113                               &sun9i_a80_usb_clk_desc);
 114         if (ret)
 115                 goto err_disable_clk;
 116
 117         return 0;
 118
 119 err_disable_clk:
 120         clk_disable_unprepare(bus_clk);
 121         return ret;
 122 }
 123
 124 static const struct of_device_id sun9i_a80_usb_clk_ids[] = {
 125         { .compatible = "allwinner,sun9i-a80-usb-clks" },
 126         { }
 127 };
 128
 129 static struct platform_driver sun9i_a80_usb_clk_driver = {
 130         .probe  = sun9i_a80_usb_clk_probe,
 131         .driver = {
 132                 .name   = "sun9i-a80-usb-clks",
 133                 .of_match_table = sun9i_a80_usb_clk_ids,
 134         },
 135 };
 136 builtin_platform_driver(sun9i_a80_usb_clk_driver);