2 * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
16 #include <linux/platform_device.h>
18 #include "ccu_common.h"
19 #include "ccu_reset.h"
26 #include "ccu-sun8i-r.h"
28 static const char * const ar100_parents[] = { "osc32k", "osc24M",
29 "pll-periph0", "iosc" };
30 static const char * const a83t_ar100_parents[] = { "osc16M-d512", "osc24M",
31 "pll-periph0", "iosc" };
32 static const struct ccu_mux_var_prediv ar100_predivs[] = {
33 { .index = 2, .shift = 8, .width = 5 },
36 static struct ccu_div ar100_clk = {
37 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
43 .var_predivs = ar100_predivs,
44 .n_var_predivs = ARRAY_SIZE(ar100_predivs),
49 .features = CCU_FEATURE_VARIABLE_PREDIV,
50 .hw.init = CLK_HW_INIT_PARENTS("ar100",
57 static struct ccu_div a83t_ar100_clk = {
58 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
64 .var_predivs = ar100_predivs,
65 .n_var_predivs = ARRAY_SIZE(ar100_predivs),
70 .features = CCU_FEATURE_VARIABLE_PREDIV,
71 .hw.init = CLK_HW_INIT_PARENTS("ar100",
78 static CLK_FIXED_FACTOR(ahb0_clk, "ahb0", "ar100", 1, 1, 0);
80 static struct ccu_div apb0_clk = {
81 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
85 .hw.init = CLK_HW_INIT("apb0",
92 static SUNXI_CCU_M(a83t_apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);
94 static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
96 static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0",
98 static SUNXI_CCU_GATE(apb0_timer_clk, "apb0-timer", "apb0",
100 static SUNXI_CCU_GATE(apb0_rsb_clk, "apb0-rsb", "apb0",
102 static SUNXI_CCU_GATE(apb0_uart_clk, "apb0-uart", "apb0",
104 static SUNXI_CCU_GATE(apb0_i2c_clk, "apb0-i2c", "apb0",
106 static SUNXI_CCU_GATE(apb0_twd_clk, "apb0-twd", "apb0",
109 static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
110 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
111 r_mod0_default_parents, 0x54,
118 static const char *const a83t_r_mod0_parents[] = { "osc16M", "osc24M" };
119 static const struct ccu_mux_fixed_prediv a83t_ir_predivs[] = {
120 { .index = 0, .div = 16 },
122 static struct ccu_mp a83t_ir_clk = {
125 .m = _SUNXI_CCU_DIV(0, 4),
126 .p = _SUNXI_CCU_DIV(16, 2),
131 .fixed_predivs = a83t_ir_predivs,
132 .n_predivs = ARRAY_SIZE(a83t_ir_predivs),
137 .features = CCU_FEATURE_VARIABLE_PREDIV,
138 .hw.init = CLK_HW_INIT_PARENTS("ir",
145 static struct ccu_common *sun8i_a83t_r_ccu_clks[] = {
146 &a83t_ar100_clk.common,
147 &a83t_apb0_clk.common,
148 &apb0_pio_clk.common,
150 &apb0_timer_clk.common,
151 &apb0_rsb_clk.common,
152 &apb0_uart_clk.common,
153 &apb0_i2c_clk.common,
154 &apb0_twd_clk.common,
158 static struct ccu_common *sun8i_h3_r_ccu_clks[] = {
161 &apb0_pio_clk.common,
163 &apb0_timer_clk.common,
164 &apb0_uart_clk.common,
165 &apb0_i2c_clk.common,
166 &apb0_twd_clk.common,
170 static struct ccu_common *sun50i_a64_r_ccu_clks[] = {
173 &apb0_pio_clk.common,
175 &apb0_timer_clk.common,
176 &apb0_rsb_clk.common,
177 &apb0_uart_clk.common,
178 &apb0_i2c_clk.common,
179 &apb0_twd_clk.common,
183 static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = {
185 [CLK_AR100] = &a83t_ar100_clk.common.hw,
186 [CLK_AHB0] = &ahb0_clk.hw,
187 [CLK_APB0] = &a83t_apb0_clk.common.hw,
188 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
189 [CLK_APB0_IR] = &apb0_ir_clk.common.hw,
190 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
191 [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw,
192 [CLK_APB0_UART] = &apb0_uart_clk.common.hw,
193 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
194 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
195 [CLK_IR] = &a83t_ir_clk.common.hw,
200 static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = {
202 [CLK_AR100] = &ar100_clk.common.hw,
203 [CLK_AHB0] = &ahb0_clk.hw,
204 [CLK_APB0] = &apb0_clk.common.hw,
205 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
206 [CLK_APB0_IR] = &apb0_ir_clk.common.hw,
207 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
208 [CLK_APB0_UART] = &apb0_uart_clk.common.hw,
209 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
210 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
211 [CLK_IR] = &ir_clk.common.hw,
216 static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = {
218 [CLK_AR100] = &ar100_clk.common.hw,
219 [CLK_AHB0] = &ahb0_clk.hw,
220 [CLK_APB0] = &apb0_clk.common.hw,
221 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
222 [CLK_APB0_IR] = &apb0_ir_clk.common.hw,
223 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
224 [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw,
225 [CLK_APB0_UART] = &apb0_uart_clk.common.hw,
226 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
227 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
228 [CLK_IR] = &ir_clk.common.hw,
233 static struct ccu_reset_map sun8i_a83t_r_ccu_resets[] = {
234 [RST_APB0_IR] = { 0xb0, BIT(1) },
235 [RST_APB0_TIMER] = { 0xb0, BIT(2) },
236 [RST_APB0_RSB] = { 0xb0, BIT(3) },
237 [RST_APB0_UART] = { 0xb0, BIT(4) },
238 [RST_APB0_I2C] = { 0xb0, BIT(6) },
241 static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = {
242 [RST_APB0_IR] = { 0xb0, BIT(1) },
243 [RST_APB0_TIMER] = { 0xb0, BIT(2) },
244 [RST_APB0_UART] = { 0xb0, BIT(4) },
245 [RST_APB0_I2C] = { 0xb0, BIT(6) },
248 static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = {
249 [RST_APB0_IR] = { 0xb0, BIT(1) },
250 [RST_APB0_TIMER] = { 0xb0, BIT(2) },
251 [RST_APB0_RSB] = { 0xb0, BIT(3) },
252 [RST_APB0_UART] = { 0xb0, BIT(4) },
253 [RST_APB0_I2C] = { 0xb0, BIT(6) },
256 static const struct sunxi_ccu_desc sun8i_a83t_r_ccu_desc = {
257 .ccu_clks = sun8i_a83t_r_ccu_clks,
258 .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_r_ccu_clks),
260 .hw_clks = &sun8i_a83t_r_hw_clks,
262 .resets = sun8i_a83t_r_ccu_resets,
263 .num_resets = ARRAY_SIZE(sun8i_a83t_r_ccu_resets),
266 static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = {
267 .ccu_clks = sun8i_h3_r_ccu_clks,
268 .num_ccu_clks = ARRAY_SIZE(sun8i_h3_r_ccu_clks),
270 .hw_clks = &sun8i_h3_r_hw_clks,
272 .resets = sun8i_h3_r_ccu_resets,
273 .num_resets = ARRAY_SIZE(sun8i_h3_r_ccu_resets),
276 static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = {
277 .ccu_clks = sun50i_a64_r_ccu_clks,
278 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_r_ccu_clks),
280 .hw_clks = &sun50i_a64_r_hw_clks,
282 .resets = sun50i_a64_r_ccu_resets,
283 .num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets),
286 static void __init sunxi_r_ccu_init(struct device_node *node,
287 const struct sunxi_ccu_desc *desc)
291 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
293 pr_err("%s: Could not map the clock registers\n",
294 of_node_full_name(node));
298 sunxi_ccu_probe(node, reg, desc);
301 static void __init sun8i_a83t_r_ccu_setup(struct device_node *node)
303 sunxi_r_ccu_init(node, &sun8i_a83t_r_ccu_desc);
305 CLK_OF_DECLARE(sun8i_a83t_r_ccu, "allwinner,sun8i-a83t-r-ccu",
306 sun8i_a83t_r_ccu_setup);
308 static void __init sun8i_h3_r_ccu_setup(struct device_node *node)
310 sunxi_r_ccu_init(node, &sun8i_h3_r_ccu_desc);
312 CLK_OF_DECLARE(sun8i_h3_r_ccu, "allwinner,sun8i-h3-r-ccu",
313 sun8i_h3_r_ccu_setup);
315 static void __init sun50i_a64_r_ccu_setup(struct device_node *node)
317 sunxi_r_ccu_init(node, &sun50i_a64_r_ccu_desc);
319 CLK_OF_DECLARE(sun50i_a64_r_ccu, "allwinner,sun50i-a64-r-ccu",
320 sun50i_a64_r_ccu_setup);