2 * Copyright 2013 Emilio López
4 * Emilio López <emilio@elopez.com.ar>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
20 #include <linux/of_address.h>
21 #include <linux/reset-controller.h>
22 #include <linux/spinlock.h>
24 #include "clk-factors.h"
26 static DEFINE_SPINLOCK(clk_lock);
28 /* Maximum number of parents our clocks have */
29 #define SUNXI_MAX_PARENTS 5
32 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
33 * PLL1 rate is calculated as follows
34 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
35 * parent_rate is always 24Mhz
38 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
39 u8 *n, u8 *k, u8 *m, u8 *p)
43 /* Normalize value to a 6M multiple */
44 div = *freq / 6000000;
45 *freq = 6000000 * div;
47 /* we were called to round the frequency, we can now return */
51 /* m is always zero for pll1 */
54 /* k is 1 only on these cases */
55 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
60 /* p will be 3 for divs under 10 */
64 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
65 else if (div < 20 || (div < 32 && (div & 1)))
68 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
69 * of divs between 40-62 */
70 else if (div < 40 || (div < 64 && (div & 2)))
73 /* any other entries have p = 0 */
77 /* calculate a suitable n based on k and p */
84 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
85 * PLL1 rate is calculated as follows
86 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
87 * parent_rate should always be 24MHz
89 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
90 u8 *n, u8 *k, u8 *m, u8 *p)
93 * We can operate only on MHz, this will make our life easier
96 u32 freq_mhz = *freq / 1000000;
97 u32 parent_freq_mhz = parent_rate / 1000000;
100 * Round down the frequency to the closest multiple of either
103 u32 round_freq_6 = round_down(freq_mhz, 6);
104 u32 round_freq_16 = round_down(freq_mhz, 16);
106 if (round_freq_6 > round_freq_16)
107 freq_mhz = round_freq_6;
109 freq_mhz = round_freq_16;
111 *freq = freq_mhz * 1000000;
114 * If the factors pointer are null, we were just called to
115 * round down the frequency.
121 /* If the frequency is a multiple of 32 MHz, k is always 3 */
122 if (!(freq_mhz % 32))
124 /* If the frequency is a multiple of 9 MHz, k is always 2 */
125 else if (!(freq_mhz % 9))
127 /* If the frequency is a multiple of 8 MHz, k is always 1 */
128 else if (!(freq_mhz % 8))
130 /* Otherwise, we don't use the k factor */
135 * If the frequency is a multiple of 2 but not a multiple of
136 * 3, m is 3. This is the first time we use 6 here, yet we
137 * will use it on several other places.
138 * We use this number because it's the lowest frequency we can
139 * generate (with n = 0, k = 0, m = 3), so every other frequency
140 * somehow relates to this frequency.
142 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
145 * If the frequency is a multiple of 6MHz, but the factor is
148 else if ((freq_mhz / 6) & 1)
150 /* Otherwise, we end up with m = 1 */
154 /* Calculate n thanks to the above factors we already got */
155 *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
158 * If n end up being outbound, and that we can still decrease
161 if ((*n + 1) > 31 && (*m + 1) > 1) {
162 *n = (*n + 1) / 2 - 1;
163 *m = (*m + 1) / 2 - 1;
168 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
169 * PLL1 rate is calculated as follows
170 * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
171 * parent_rate is always 24Mhz
174 static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate,
175 u8 *n, u8 *k, u8 *m, u8 *p)
179 /* Normalize value to a 6M multiple */
180 div = *freq / 6000000;
181 *freq = 6000000 * div;
183 /* we were called to round the frequency, we can now return */
187 /* m is always zero for pll1 */
190 /* k is 1 only on these cases */
191 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
196 /* p will be 2 for divs under 20 and odd divs under 32 */
197 if (div < 20 || (div < 32 && (div & 1)))
200 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
201 * of divs between 40-62 */
202 else if (div < 40 || (div < 64 && (div & 2)))
205 /* any other entries have p = 0 */
209 /* calculate a suitable n based on k and p */
216 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
217 * PLL5 rate is calculated as follows
218 * rate = parent_rate * n * (k + 1)
219 * parent_rate is always 24Mhz
222 static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
223 u8 *n, u8 *k, u8 *m, u8 *p)
227 /* Normalize value to a parent_rate multiple (24M) */
228 div = *freq / parent_rate;
229 *freq = parent_rate * div;
231 /* we were called to round the frequency, we can now return */
237 else if (div / 2 < 31)
239 else if (div / 3 < 31)
244 *n = DIV_ROUND_UP(div, (*k+1));
248 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
249 * PLL6 rate is calculated as follows
250 * rate = parent_rate * n * (k + 1) / 2
251 * parent_rate is always 24Mhz
254 static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
255 u8 *n, u8 *k, u8 *m, u8 *p)
260 * We always have 24MHz / 2, so we can just say that our
261 * parent clock is 12MHz.
263 parent_rate = parent_rate / 2;
265 /* Normalize value to a parent_rate multiple (24M / 2) */
266 div = *freq / parent_rate;
267 *freq = parent_rate * div;
269 /* we were called to round the frequency, we can now return */
277 *n = DIV_ROUND_UP(div, (*k+1));
281 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
282 * APB1 rate is calculated as follows
283 * rate = (parent_rate >> p) / (m + 1);
286 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
287 u8 *n, u8 *k, u8 *m, u8 *p)
291 if (parent_rate < *freq)
294 parent_rate = DIV_ROUND_UP(parent_rate, *freq);
297 if (parent_rate > 32)
300 if (parent_rate <= 4)
302 else if (parent_rate <= 8)
304 else if (parent_rate <= 16)
309 calcm = (parent_rate >> calcp) - 1;
311 *freq = (parent_rate >> calcp) / (calcm + 1);
313 /* we were called to round the frequency, we can now return */
325 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
326 * CLK_OUT rate is calculated as follows
327 * rate = (parent_rate >> p) / (m + 1);
330 static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
331 u8 *n, u8 *k, u8 *m, u8 *p)
333 u8 div, calcm, calcp;
335 /* These clocks can only divide, so we will never be able to achieve
336 * frequencies higher than the parent frequency */
337 if (*freq > parent_rate)
340 div = DIV_ROUND_UP(parent_rate, *freq);
344 else if (div / 2 < 32)
346 else if (div / 4 < 32)
351 calcm = DIV_ROUND_UP(div, 1 << calcp);
353 *freq = (parent_rate >> calcp) / calcm;
355 /* we were called to round the frequency, we can now return */
364 * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
367 void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output)
369 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
370 #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
372 struct clk_hw *hw = __clk_get_hw(clk);
373 struct clk_composite *composite = to_clk_composite(hw);
374 struct clk_hw *rate_hw = composite->rate_hw;
375 struct clk_factors *factors = to_clk_factors(rate_hw);
376 unsigned long flags = 0;
380 spin_lock_irqsave(factors->lock, flags);
382 reg = readl(factors->reg);
384 /* set sample clock phase control */
386 reg |= ((sample & 0x7) << 20);
388 /* set output clock phase control */
390 reg |= ((output & 0x7) << 8);
392 writel(reg, factors->reg);
395 spin_unlock_irqrestore(factors->lock, flags);
397 EXPORT_SYMBOL(clk_sunxi_mmc_phase_control);
401 * sunxi_factors_clk_setup() - Setup function for factor clocks
404 static struct clk_factors_config sun4i_pll1_config = {
415 static struct clk_factors_config sun6i_a31_pll1_config = {
424 static struct clk_factors_config sun8i_a23_pll1_config = {
436 static struct clk_factors_config sun4i_pll5_config = {
443 static struct clk_factors_config sun6i_a31_pll6_config = {
450 static struct clk_factors_config sun4i_apb1_config = {
457 /* user manual says "n" but it's really "p" */
458 static struct clk_factors_config sun7i_a20_out_config = {
465 static const struct factors_data sun4i_pll1_data __initconst = {
467 .table = &sun4i_pll1_config,
468 .getter = sun4i_get_pll1_factors,
471 static const struct factors_data sun6i_a31_pll1_data __initconst = {
473 .table = &sun6i_a31_pll1_config,
474 .getter = sun6i_a31_get_pll1_factors,
477 static const struct factors_data sun8i_a23_pll1_data __initconst = {
479 .table = &sun8i_a23_pll1_config,
480 .getter = sun8i_a23_get_pll1_factors,
483 static const struct factors_data sun7i_a20_pll4_data __initconst = {
485 .table = &sun4i_pll5_config,
486 .getter = sun4i_get_pll5_factors,
489 static const struct factors_data sun4i_pll5_data __initconst = {
491 .table = &sun4i_pll5_config,
492 .getter = sun4i_get_pll5_factors,
496 static const struct factors_data sun4i_pll6_data __initconst = {
498 .table = &sun4i_pll5_config,
499 .getter = sun4i_get_pll5_factors,
503 static const struct factors_data sun6i_a31_pll6_data __initconst = {
505 .table = &sun6i_a31_pll6_config,
506 .getter = sun6i_a31_get_pll6_factors,
509 static const struct factors_data sun4i_apb1_data __initconst = {
510 .table = &sun4i_apb1_config,
511 .getter = sun4i_get_apb1_factors,
514 static const struct factors_data sun7i_a20_out_data __initconst = {
517 .table = &sun7i_a20_out_config,
518 .getter = sun7i_a20_get_out_factors,
521 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
522 const struct factors_data *data)
524 return sunxi_factors_register(node, data, &clk_lock);
530 * sunxi_mux_clk_setup() - Setup function for muxes
533 #define SUNXI_MUX_GATE_WIDTH 2
539 static const struct mux_data sun4i_cpu_mux_data __initconst = {
543 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
547 static const struct mux_data sun4i_apb1_mux_data __initconst = {
551 static void __init sunxi_mux_clk_setup(struct device_node *node,
552 struct mux_data *data)
555 const char *clk_name = node->name;
556 const char *parents[SUNXI_MAX_PARENTS];
560 reg = of_iomap(node, 0);
562 while (i < SUNXI_MAX_PARENTS &&
563 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
566 of_property_read_string(node, "clock-output-names", &clk_name);
568 clk = clk_register_mux(NULL, clk_name, parents, i,
569 CLK_SET_RATE_NO_REPARENT, reg,
570 data->shift, SUNXI_MUX_GATE_WIDTH,
574 of_clk_add_provider(node, of_clk_src_simple_get, clk);
575 clk_register_clkdev(clk, clk_name, NULL);
582 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
589 const struct clk_div_table *table;
592 static const struct div_data sun4i_axi_data __initconst = {
598 static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
599 { .val = 0, .div = 1 },
600 { .val = 1, .div = 2 },
601 { .val = 2, .div = 3 },
602 { .val = 3, .div = 4 },
603 { .val = 4, .div = 4 },
604 { .val = 5, .div = 4 },
605 { .val = 6, .div = 4 },
606 { .val = 7, .div = 4 },
610 static const struct div_data sun8i_a23_axi_data __initconst = {
612 .table = sun8i_a23_axi_table,
615 static const struct div_data sun4i_ahb_data __initconst = {
621 static const struct clk_div_table sun4i_apb0_table[] __initconst = {
622 { .val = 0, .div = 2 },
623 { .val = 1, .div = 2 },
624 { .val = 2, .div = 4 },
625 { .val = 3, .div = 8 },
629 static const struct div_data sun4i_apb0_data __initconst = {
633 .table = sun4i_apb0_table,
636 static const struct div_data sun6i_a31_apb2_div_data __initconst = {
642 static void __init sunxi_divider_clk_setup(struct device_node *node,
643 struct div_data *data)
646 const char *clk_name = node->name;
647 const char *clk_parent;
650 reg = of_iomap(node, 0);
652 clk_parent = of_clk_get_parent_name(node, 0);
654 of_property_read_string(node, "clock-output-names", &clk_name);
656 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
657 reg, data->shift, data->width,
658 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
659 data->table, &clk_lock);
661 of_clk_add_provider(node, of_clk_src_simple_get, clk);
662 clk_register_clkdev(clk, clk_name, NULL);
669 * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
672 struct gates_reset_data {
675 struct reset_controller_dev rcdev;
678 static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
681 struct gates_reset_data *data = container_of(rcdev,
682 struct gates_reset_data,
687 spin_lock_irqsave(data->lock, flags);
689 reg = readl(data->reg);
690 writel(reg & ~BIT(id), data->reg);
692 spin_unlock_irqrestore(data->lock, flags);
697 static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
700 struct gates_reset_data *data = container_of(rcdev,
701 struct gates_reset_data,
706 spin_lock_irqsave(data->lock, flags);
708 reg = readl(data->reg);
709 writel(reg | BIT(id), data->reg);
711 spin_unlock_irqrestore(data->lock, flags);
716 static struct reset_control_ops sunxi_gates_reset_ops = {
717 .assert = sunxi_gates_reset_assert,
718 .deassert = sunxi_gates_reset_deassert,
722 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
725 #define SUNXI_GATES_MAX_SIZE 64
728 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
732 static const struct gates_data sun4i_axi_gates_data __initconst = {
736 static const struct gates_data sun4i_ahb_gates_data __initconst = {
737 .mask = {0x7F77FFF, 0x14FB3F},
740 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
741 .mask = {0x147667e7, 0x185915},
744 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
745 .mask = {0x107067e7, 0x185111},
748 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
749 .mask = {0xEDFE7F62, 0x794F931},
752 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
753 .mask = { 0x12f77fff, 0x16ff3f },
756 static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
757 .mask = {0x25386742, 0x2505111},
760 static const struct gates_data sun4i_apb0_gates_data __initconst = {
764 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
768 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
772 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
776 static const struct gates_data sun4i_apb1_gates_data __initconst = {
780 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
784 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
788 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
792 static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
796 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
800 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
801 .mask = { 0xff80ff },
804 static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
808 static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
813 static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
818 static const struct gates_data sun6i_a31_usb_gates_data __initconst = {
819 .mask = { BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8) },
820 .reset_mask = BIT(2) | BIT(1) | BIT(0),
823 static void __init sunxi_gates_clk_setup(struct device_node *node,
824 struct gates_data *data)
826 struct clk_onecell_data *clk_data;
827 struct gates_reset_data *reset_data;
828 const char *clk_parent;
829 const char *clk_name;
835 reg = of_iomap(node, 0);
837 clk_parent = of_clk_get_parent_name(node, 0);
839 /* Worst-case size approximation and memory allocation */
840 qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
841 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
844 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
845 if (!clk_data->clks) {
850 for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
851 of_property_read_string_index(node, "clock-output-names",
854 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
856 reg + 4 * (i/32), i % 32,
858 WARN_ON(IS_ERR(clk_data->clks[i]));
859 clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
864 /* Adjust to the real max */
865 clk_data->clk_num = i;
867 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
869 /* Register a reset controler for gates with reset bits */
870 if (data->reset_mask == 0)
873 reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
877 reset_data->reg = reg;
878 reset_data->lock = &clk_lock;
879 reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
880 reset_data->rcdev.ops = &sunxi_gates_reset_ops;
881 reset_data->rcdev.of_node = node;
882 reset_controller_register(&reset_data->rcdev);
888 * sunxi_divs_clk_setup() helper data
891 #define SUNXI_DIVS_MAX_QTY 2
892 #define SUNXI_DIVISOR_WIDTH 2
895 const struct factors_data *factors; /* data for the factor clock */
897 u8 fixed; /* is it a fixed divisor? if not... */
898 struct clk_div_table *table; /* is it a table based divisor? */
899 u8 shift; /* otherwise it's a normal divisor with this shift */
900 u8 pow; /* is it power-of-two based? */
901 u8 gate; /* is it independently gateable? */
902 } div[SUNXI_DIVS_MAX_QTY];
905 static struct clk_div_table pll6_sata_tbl[] = {
906 { .val = 0, .div = 6, },
907 { .val = 1, .div = 12, },
908 { .val = 2, .div = 18, },
909 { .val = 3, .div = 24, },
913 static const struct divs_data pll5_divs_data __initconst = {
914 .factors = &sun4i_pll5_data,
916 { .shift = 0, .pow = 0, }, /* M, DDR */
917 { .shift = 16, .pow = 1, }, /* P, other */
921 static const struct divs_data pll6_divs_data __initconst = {
922 .factors = &sun4i_pll6_data,
924 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
925 { .fixed = 2 }, /* P, other */
930 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
932 * These clocks look something like this
933 * ________________________
934 * | ___divisor 1---|----> to consumer
935 * parent >--| pll___/___divisor 2---|----> to consumer
936 * | \_______________|____> to consumer
937 * |________________________|
940 static void __init sunxi_divs_clk_setup(struct device_node *node,
941 struct divs_data *data)
943 struct clk_onecell_data *clk_data;
945 const char *clk_name;
946 struct clk **clks, *pclk;
947 struct clk_hw *gate_hw, *rate_hw;
948 const struct clk_ops *rate_ops;
949 struct clk_gate *gate = NULL;
950 struct clk_fixed_factor *fix_factor;
951 struct clk_divider *divider;
956 /* Set up factor clock that we will be dividing */
957 pclk = sunxi_factors_clk_setup(node, data->factors);
958 parent = __clk_get_name(pclk);
960 reg = of_iomap(node, 0);
962 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
966 clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL);
970 clk_data->clks = clks;
972 /* It's not a good idea to have automatic reparenting changing
974 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
976 for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
977 if (of_property_read_string_index(node, "clock-output-names",
985 /* If this leaf clock can be gated, create a gate */
986 if (data->div[i].gate) {
987 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
992 gate->bit_idx = data->div[i].gate;
993 gate->lock = &clk_lock;
998 /* Leaves can be fixed or configurable divisors */
999 if (data->div[i].fixed) {
1000 fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1004 fix_factor->mult = 1;
1005 fix_factor->div = data->div[i].fixed;
1007 rate_hw = &fix_factor->hw;
1008 rate_ops = &clk_fixed_factor_ops;
1010 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1014 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1017 divider->shift = data->div[i].shift;
1018 divider->width = SUNXI_DIVISOR_WIDTH;
1019 divider->flags = flags;
1020 divider->lock = &clk_lock;
1021 divider->table = data->div[i].table;
1023 rate_hw = ÷r->hw;
1024 rate_ops = &clk_divider_ops;
1027 /* Wrap the (potential) gate and the divisor on a composite
1028 * clock to unify them */
1029 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1032 gate_hw, &clk_gate_ops,
1035 WARN_ON(IS_ERR(clk_data->clks[i]));
1036 clk_register_clkdev(clks[i], clk_name, NULL);
1039 /* The last clock available on the getter is the parent */
1042 /* Adjust to the real max */
1043 clk_data->clk_num = i;
1045 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1059 /* Matches for factors clocks */
1060 static const struct of_device_id clk_factors_match[] __initconst = {
1061 {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
1062 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
1063 {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
1064 {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
1065 {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
1066 {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
1067 {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
1071 /* Matches for divider clocks */
1072 static const struct of_device_id clk_div_match[] __initconst = {
1073 {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
1074 {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
1075 {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
1076 {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
1077 {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
1081 /* Matches for divided outputs */
1082 static const struct of_device_id clk_divs_match[] __initconst = {
1083 {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
1084 {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
1088 /* Matches for mux clocks */
1089 static const struct of_device_id clk_mux_match[] __initconst = {
1090 {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
1091 {.compatible = "allwinner,sun4i-a10-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
1092 {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
1096 /* Matches for gate clocks */
1097 static const struct of_device_id clk_gates_match[] __initconst = {
1098 {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
1099 {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
1100 {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
1101 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
1102 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
1103 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
1104 {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
1105 {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
1106 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
1107 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
1108 {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
1109 {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
1110 {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
1111 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
1112 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
1113 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
1114 {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
1115 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
1116 {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
1117 {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
1118 {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
1119 {.compatible = "allwinner,sun6i-a31-usb-clk", .data = &sun6i_a31_usb_gates_data,},
1123 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
1126 struct device_node *np;
1127 const struct div_data *data;
1128 const struct of_device_id *match;
1129 void (*setup_function)(struct device_node *, const void *) = function;
1131 for_each_matching_node_and_match(np, clk_match, &match) {
1133 setup_function(np, data);
1137 static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
1141 /* Register factor clocks */
1142 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
1144 /* Register divider clocks */
1145 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
1147 /* Register divided output clocks */
1148 of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1150 /* Register mux clocks */
1151 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
1153 /* Register gate clocks */
1154 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
1156 /* Protect the clocks that needs to stay on */
1157 for (i = 0; i < nclocks; i++) {
1158 struct clk *clk = clk_get(NULL, clocks[i]);
1161 clk_prepare_enable(clk);
1165 static const char *sun4i_a10_critical_clocks[] __initdata = {
1170 static void __init sun4i_a10_init_clocks(struct device_node *node)
1172 sunxi_init_clocks(sun4i_a10_critical_clocks,
1173 ARRAY_SIZE(sun4i_a10_critical_clocks));
1175 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks);
1177 static const char *sun5i_critical_clocks[] __initdata = {
1182 static void __init sun5i_init_clocks(struct device_node *node)
1184 sunxi_init_clocks(sun5i_critical_clocks,
1185 ARRAY_SIZE(sun5i_critical_clocks));
1187 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks);
1188 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks);
1189 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks);
1191 static const char *sun6i_critical_clocks[] __initdata = {
1196 static void __init sun6i_init_clocks(struct device_node *node)
1198 sunxi_init_clocks(sun6i_critical_clocks,
1199 ARRAY_SIZE(sun6i_critical_clocks));
1201 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
1202 CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);